.. | .. |
---|
| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
---|
1 | 2 | /* |
---|
2 | 3 | * RTL8XXXU mac80211 USB driver - 8723b specific subdriver |
---|
3 | 4 | * |
---|
.. | .. |
---|
10 | 11 | * rtl8723au driver. As the Realtek 8xxx chips are very similar in |
---|
11 | 12 | * their programming interface, I have started adding support for |
---|
12 | 13 | * additional 8xxx chips like the 8192cu, 8188cus, etc. |
---|
13 | | - * |
---|
14 | | - * This program is free software; you can redistribute it and/or modify it |
---|
15 | | - * under the terms of version 2 of the GNU General Public License as |
---|
16 | | - * published by the Free Software Foundation. |
---|
17 | | - * |
---|
18 | | - * This program is distributed in the hope that it will be useful, but WITHOUT |
---|
19 | | - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
---|
20 | | - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
---|
21 | | - * more details. |
---|
22 | 14 | */ |
---|
23 | 15 | |
---|
24 | 16 | #include <linux/init.h> |
---|
.. | .. |
---|
890 | 882 | u32 i, val32; |
---|
891 | 883 | int path_a_ok /*, path_b_ok */; |
---|
892 | 884 | int retry = 2; |
---|
893 | | - const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { |
---|
| 885 | + static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { |
---|
894 | 886 | REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, |
---|
895 | 887 | REG_RX_WAIT_CCA, REG_TX_CCK_RFON, |
---|
896 | 888 | REG_TX_CCK_BBON, REG_TX_OFDM_RFON, |
---|
.. | .. |
---|
900 | 892 | REG_RX_TO_RX, REG_STANDBY, |
---|
901 | 893 | REG_SLEEP, REG_PMPD_ANAEN |
---|
902 | 894 | }; |
---|
903 | | - const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { |
---|
| 895 | + static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { |
---|
904 | 896 | REG_TXPAUSE, REG_BEACON_CTRL, |
---|
905 | 897 | REG_BEACON_CTRL_1, REG_GPIO_MUXCFG |
---|
906 | 898 | }; |
---|
907 | | - const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { |
---|
| 899 | + static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { |
---|
908 | 900 | REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, |
---|
909 | 901 | REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, |
---|
910 | 902 | REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, |
---|
.. | .. |
---|
1533 | 1525 | /* |
---|
1534 | 1526 | * WLAN action by PTA |
---|
1535 | 1527 | */ |
---|
1536 | | - rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04); |
---|
| 1528 | + rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x0c); |
---|
1537 | 1529 | |
---|
1538 | 1530 | /* |
---|
1539 | 1531 | * BT select S0/S1 controlled by WiFi |
---|
.. | .. |
---|
1576 | 1568 | rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv)); |
---|
1577 | 1569 | |
---|
1578 | 1570 | /* |
---|
1579 | | - * 0x280, 0x00, 0x200, 0x80 - not clear |
---|
| 1571 | + * Different settings per different antenna position. |
---|
| 1572 | + * Antenna Position: | Normal Inverse |
---|
| 1573 | + * -------------------------------------------------- |
---|
| 1574 | + * Antenna switch to BT: | 0x280, 0x00 |
---|
| 1575 | + * Antenna switch to WiFi: | 0x0, 0x280 |
---|
| 1576 | + * Antenna switch to PTA: | 0x200, 0x80 |
---|
1580 | 1577 | */ |
---|
1581 | | - rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00); |
---|
| 1578 | + rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x80); |
---|
1582 | 1579 | |
---|
1583 | 1580 | /* |
---|
1584 | 1581 | * Software control, antenna at WiFi side |
---|
1585 | 1582 | */ |
---|
1586 | | -#ifdef NEED_PS_TDMA |
---|
1587 | 1583 | rtl8723bu_set_ps_tdma(priv, 0x08, 0x00, 0x00, 0x00, 0x00); |
---|
1588 | | -#endif |
---|
1589 | 1584 | |
---|
1590 | 1585 | rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); |
---|
1591 | 1586 | rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555); |
---|