.. | .. |
---|
529 | 529 | ee->ee_n_piers[mode]++; |
---|
530 | 530 | |
---|
531 | 531 | freq2 = (val >> 8) & 0xff; |
---|
532 | | - if (!freq2) |
---|
| 532 | + if (!freq2 || i >= max) |
---|
533 | 533 | break; |
---|
534 | 534 | |
---|
535 | 535 | pc[i++].freq = ath5k_eeprom_bin2freq(ee, |
---|
.. | .. |
---|
745 | 745 | break; |
---|
746 | 746 | } |
---|
747 | 747 | } |
---|
| 748 | + |
---|
| 749 | + if (idx == AR5K_EEPROM_N_PD_CURVES) |
---|
| 750 | + goto err_out; |
---|
748 | 751 | |
---|
749 | 752 | ee->ee_pd_gains[mode] = 1; |
---|
750 | 753 | |
---|
.. | .. |
---|
1172 | 1175 | offset += ath5k_pdgains_size_2413(ee, |
---|
1173 | 1176 | AR5K_EEPROM_MODE_11B) + |
---|
1174 | 1177 | AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2; |
---|
1175 | | - /* fall through */ |
---|
| 1178 | + fallthrough; |
---|
1176 | 1179 | case AR5K_EEPROM_MODE_11B: |
---|
1177 | 1180 | if (AR5K_EEPROM_HDR_11A(ee->ee_header)) |
---|
1178 | 1181 | offset += ath5k_pdgains_size_2413(ee, |
---|
1179 | 1182 | AR5K_EEPROM_MODE_11A) + |
---|
1180 | 1183 | AR5K_EEPROM_N_5GHZ_CHAN / 2; |
---|
1181 | | - /* fall through */ |
---|
| 1184 | + fallthrough; |
---|
1182 | 1185 | case AR5K_EEPROM_MODE_11A: |
---|
1183 | 1186 | break; |
---|
1184 | 1187 | default: |
---|
.. | .. |
---|
1707 | 1710 | struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; |
---|
1708 | 1711 | u32 offset; |
---|
1709 | 1712 | u16 val; |
---|
1710 | | - int ret = 0, i; |
---|
| 1713 | + int i; |
---|
1711 | 1714 | |
---|
1712 | 1715 | offset = AR5K_EEPROM_CTL(ee->ee_version) + |
---|
1713 | 1716 | AR5K_EEPROM_N_CTLS(ee->ee_version); |
---|
.. | .. |
---|
1730 | 1733 | } |
---|
1731 | 1734 | } |
---|
1732 | 1735 | |
---|
1733 | | - return ret; |
---|
| 1736 | + return 0; |
---|
1734 | 1737 | } |
---|
1735 | 1738 | |
---|
1736 | 1739 | |
---|