~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,9 +1,5 @@
1		-/*
2		- * This file is subject to the terms and conditions of the GNU General Public
3		- * License. See the file "COPYING" in the main directory of this archive
4		- * for more details.
5		- *
6		- * Driver for SGI's IOC3 based Ethernet cards as found in the PCI card.
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+/* Driver for SGI's IOC3 based Ethernet cards as found in the PCI card.
7	3	*
8	4	* Copyright (C) 1999, 2000, 01, 03, 06 Ralf Baechle
9	5	* Copyright (C) 1995, 1999, 2000, 2001 by Silicon Graphics, Inc.
..	..	@@ -15,13 +11,9 @@
15	11	*
16	12	* To do:
17	13	*
18		- * o Handle allocation failures in ioc3_alloc_skb() more gracefully.
19		- * o Handle allocation failures in ioc3_init_rings().
20	14	* o Use prefetching for large packets. What is a good lower limit for
21	15	* prefetching?
22		- * o We're probably allocating a bit too much memory.
23	16	* o Use hardware checksums.
24		- * o Convert to using a IOC3 meta driver.
25	17	* o Which PHYs might possibly be attached to the IOC3 in real live,
26	18	* which workarounds are required for them? Do we ever have Lucent's?
27	19	* o For the 2.5 branch kill the mii-tool ioctls.
..	..	@@ -35,52 +27,67 @@
35	27	#include <linux/mm.h>
36	28	#include <linux/errno.h>
37	29	#include <linux/module.h>
38		-#include <linux/pci.h>
	30	+#include <linux/init.h>
	31	+#include <linux/crc16.h>
39	32	#include <linux/crc32.h>
40	33	#include <linux/mii.h>
41	34	#include <linux/in.h>
	35	+#include <linux/io.h>
42	36	#include <linux/ip.h>
43	37	#include <linux/tcp.h>
44	38	#include <linux/udp.h>
45		-#include <linux/dma-mapping.h>
46	39	#include <linux/gfp.h>
47		-
48		-#ifdef CONFIG_SERIAL_8250
49		-#include <linux/serial_core.h>
50		-#include <linux/serial_8250.h>
51		-#include <linux/serial_reg.h>
52		-#endif
53		-
54	40	#include <linux/netdevice.h>
55	41	#include <linux/etherdevice.h>
56	42	#include <linux/ethtool.h>
57	43	#include <linux/skbuff.h>
	44	+#include <linux/dma-mapping.h>
	45	+#include <linux/platform_device.h>
	46	+#include <linux/nvmem-consumer.h>
	47	+
58	48	#include <net/ip.h>
59	49
60		-#include <asm/byteorder.h>
61		-#include <asm/io.h>
62		-#include <asm/pgtable.h>
63		-#include <linux/uaccess.h>
64		-#include <asm/sn/types.h>
65	50	#include <asm/sn/ioc3.h>
66	51	#include <asm/pci/bridge.h>
67	52
68		-/*
69		- * 64 RX buffers. This is tunable in the range of 16 <= x < 512. The
70		- * value must be a power of two.
71		- */
72		-#define RX_BUFFS 64
	53	+#define CRC16_INIT 0
	54	+#define CRC16_VALID 0xb001
73	55
74		-#define ETCSR_FD ((17<<ETCSR_IPGR2_SHIFT) \| (11<<ETCSR_IPGR1_SHIFT) \| 21)
75		-#define ETCSR_HD ((21<<ETCSR_IPGR2_SHIFT) \| (21<<ETCSR_IPGR1_SHIFT) \| 21)
	56	+/* Number of RX buffers. This is tunable in the range of 16 <= x < 512.
	57	+ * The value must be a power of two.
	58	+ */
	59	+#define RX_BUFFS 64
	60	+#define RX_RING_ENTRIES 512 /* fixed in hardware */
	61	+#define RX_RING_MASK (RX_RING_ENTRIES - 1)
	62	+#define RX_RING_SIZE (RX_RING_ENTRIES * sizeof(u64))
	63	+
	64	+/* 128 TX buffers (not tunable) */
	65	+#define TX_RING_ENTRIES 128
	66	+#define TX_RING_MASK (TX_RING_ENTRIES - 1)
	67	+#define TX_RING_SIZE (TX_RING_ENTRIES * sizeof(struct ioc3_etxd))
	68	+
	69	+/* IOC3 does dma transfers in 128 byte blocks */
	70	+#define IOC3_DMA_XFER_LEN 128UL
	71	+
	72	+/* Every RX buffer starts with 8 byte descriptor data */
	73	+#define RX_OFFSET (sizeof(struct ioc3_erxbuf) + NET_IP_ALIGN)
	74	+#define RX_BUF_SIZE (13 * IOC3_DMA_XFER_LEN)
	75	+
	76	+#define ETCSR_FD ((21 << ETCSR_IPGR2_SHIFT) \| (21 << ETCSR_IPGR1_SHIFT) \| 21)
	77	+#define ETCSR_HD ((17 << ETCSR_IPGR2_SHIFT) \| (11 << ETCSR_IPGR1_SHIFT) \| 21)
76	78
77	79	/* Private per NIC data of the driver. */
78	80	struct ioc3_private {
79		- struct ioc3 *regs;
	81	+ struct ioc3_ethregs *regs;
	82	+ struct device *dma_dev;
	83	+ u32 *ssram;
80	84	unsigned long rxr; / pointer to receiver ring */
	85	+ void *tx_ring;
81	86	struct ioc3_etxd *txr;
82		- struct sk_buff *rx_skbs[512];
83		- struct sk_buff *tx_skbs[128];
	87	+ dma_addr_t rxr_dma;
	88	+ dma_addr_t txr_dma;
	89	+ struct sk_buff *rx_skbs[RX_RING_ENTRIES];
	90	+ struct sk_buff *tx_skbs[TX_RING_ENTRIES];
84	91	int rx_ci; /* RX consumer index */
85	92	int rx_pi; /* RX producer index */
86	93	int tx_ci; /* TX consumer index */
..	..	@@ -90,9 +97,6 @@
90	97	spinlock_t ioc3_lock;
91	98	struct mii_if_info mii;
92	99
93		- struct net_device *dev;
94		- struct pci_dev *pdev;
95		-
96	100	/* Members used by autonegotiation */
97	101	struct timer_list ioc3_timer;
98	102	};
..	..	@@ -100,352 +104,138 @@
100	104	static int ioc3_ioctl(struct net_device dev, struct ifreq rq, int cmd);
101	105	static void ioc3_set_multicast_list(struct net_device *dev);
102	106	static netdev_tx_t ioc3_start_xmit(struct sk_buff skb, struct net_device dev);
103		-static void ioc3_timeout(struct net_device *dev);
	107	+static void ioc3_timeout(struct net_device *dev, unsigned int txqueue);
104	108	static inline unsigned int ioc3_hash(const unsigned char *addr);
	109	+static void ioc3_start(struct ioc3_private *ip);
105	110	static inline void ioc3_stop(struct ioc3_private *ip);
106	111	static void ioc3_init(struct net_device *dev);
	112	+static int ioc3_alloc_rx_bufs(struct net_device *dev);
	113	+static void ioc3_free_rx_bufs(struct ioc3_private *ip);
	114	+static inline void ioc3_clean_tx_ring(struct ioc3_private *ip);
107	115
108		-static const char ioc3_str[] = "IOC3 Ethernet";
109	116	static const struct ethtool_ops ioc3_ethtool_ops;
110		-
111		-/* We use this to acquire receive skb's that we can DMA directly into. */
112		-
113		-#define IOC3_CACHELINE 128UL
114	117
115	118	static inline unsigned long aligned_rx_skb_addr(unsigned long addr)
116	119	{
117		- return (~addr + 1) & (IOC3_CACHELINE - 1UL);
	120	+ return (~addr + 1) & (IOC3_DMA_XFER_LEN - 1UL);
118	121	}
119	122
120		-static inline struct sk_buff * ioc3_alloc_skb(unsigned long length,
121		- unsigned int gfp_mask)
	123	+static inline int ioc3_alloc_skb(struct ioc3_private ip, struct sk_buff *skb,
	124	+ struct ioc3_erxbuf *rxb, dma_addr_t rxb_dma)
122	125	{
123		- struct sk_buff *skb;
	126	+ struct sk_buff *new_skb;
	127	+ dma_addr_t d;
	128	+ int offset;
124	129
125		- skb = alloc_skb(length + IOC3_CACHELINE - 1, gfp_mask);
126		- if (likely(skb)) {
127		- int offset = aligned_rx_skb_addr((unsigned long) skb->data);
128		- if (offset)
129		- skb_reserve(skb, offset);
	130	+ new_skb = alloc_skb(RX_BUF_SIZE + IOC3_DMA_XFER_LEN - 1, GFP_ATOMIC);
	131	+ if (!new_skb)
	132	+ return -ENOMEM;
	133	+
	134	+ /* ensure buffer is aligned to IOC3_DMA_XFER_LEN */
	135	+ offset = aligned_rx_skb_addr((unsigned long)new_skb->data);
	136	+ if (offset)
	137	+ skb_reserve(new_skb, offset);
	138	+
	139	+ d = dma_map_single(ip->dma_dev, new_skb->data,
	140	+ RX_BUF_SIZE, DMA_FROM_DEVICE);
	141	+
	142	+ if (dma_mapping_error(ip->dma_dev, d)) {
	143	+ dev_kfree_skb_any(new_skb);
	144	+ return -ENOMEM;
130	145	}
131		-
132		- return skb;
133		-}
134		-
135		-static inline unsigned long ioc3_map(void *ptr, unsigned long vdev)
136		-{
137		-#ifdef CONFIG_SGI_IP27
138		- vdev <<= 57; /* Shift to PCI64_ATTR_VIRTUAL */
139		-
140		- return vdev \| (0xaUL << PCI64_ATTR_TARG_SHFT) \| PCI64_ATTR_PREF \|
141		- ((unsigned long)ptr & TO_PHYS_MASK);
142		-#else
143		- return virt_to_bus(ptr);
144		-#endif
145		-}
146		-
147		-/* BEWARE: The IOC3 documentation documents the size of rx buffers as
148		- 1644 while it's actually 1664. This one was nasty to track down ... */
149		-#define RX_OFFSET 10
150		-#define RX_BUF_ALLOC_SIZE (1664 + RX_OFFSET + IOC3_CACHELINE)
151		-
152		-/* DMA barrier to separate cached and uncached accesses. */
153		-#define BARRIER() \
154		- __asm__("sync" ::: "memory")
155		-
156		-
157		-#define IOC3_SIZE 0x100000
158		-
159		-/*
160		- * IOC3 is a big endian device
161		- *
162		- * Unorthodox but makes the users of these macros more readable - the pointer
163		- * to the IOC3's memory mapped registers is expected as struct ioc3 * ioc3
164		- * in the environment.
165		- */
166		-#define ioc3_r_mcr() be32_to_cpu(ioc3->mcr)
167		-#define ioc3_w_mcr(v) do { ioc3->mcr = cpu_to_be32(v); } while (0)
168		-#define ioc3_w_gpcr_s(v) do { ioc3->gpcr_s = cpu_to_be32(v); } while (0)
169		-#define ioc3_r_emcr() be32_to_cpu(ioc3->emcr)
170		-#define ioc3_w_emcr(v) do { ioc3->emcr = cpu_to_be32(v); } while (0)
171		-#define ioc3_r_eisr() be32_to_cpu(ioc3->eisr)
172		-#define ioc3_w_eisr(v) do { ioc3->eisr = cpu_to_be32(v); } while (0)
173		-#define ioc3_r_eier() be32_to_cpu(ioc3->eier)
174		-#define ioc3_w_eier(v) do { ioc3->eier = cpu_to_be32(v); } while (0)
175		-#define ioc3_r_ercsr() be32_to_cpu(ioc3->ercsr)
176		-#define ioc3_w_ercsr(v) do { ioc3->ercsr = cpu_to_be32(v); } while (0)
177		-#define ioc3_r_erbr_h() be32_to_cpu(ioc3->erbr_h)
178		-#define ioc3_w_erbr_h(v) do { ioc3->erbr_h = cpu_to_be32(v); } while (0)
179		-#define ioc3_r_erbr_l() be32_to_cpu(ioc3->erbr_l)
180		-#define ioc3_w_erbr_l(v) do { ioc3->erbr_l = cpu_to_be32(v); } while (0)
181		-#define ioc3_r_erbar() be32_to_cpu(ioc3->erbar)
182		-#define ioc3_w_erbar(v) do { ioc3->erbar = cpu_to_be32(v); } while (0)
183		-#define ioc3_r_ercir() be32_to_cpu(ioc3->ercir)
184		-#define ioc3_w_ercir(v) do { ioc3->ercir = cpu_to_be32(v); } while (0)
185		-#define ioc3_r_erpir() be32_to_cpu(ioc3->erpir)
186		-#define ioc3_w_erpir(v) do { ioc3->erpir = cpu_to_be32(v); } while (0)
187		-#define ioc3_r_ertr() be32_to_cpu(ioc3->ertr)
188		-#define ioc3_w_ertr(v) do { ioc3->ertr = cpu_to_be32(v); } while (0)
189		-#define ioc3_r_etcsr() be32_to_cpu(ioc3->etcsr)
190		-#define ioc3_w_etcsr(v) do { ioc3->etcsr = cpu_to_be32(v); } while (0)
191		-#define ioc3_r_ersr() be32_to_cpu(ioc3->ersr)
192		-#define ioc3_w_ersr(v) do { ioc3->ersr = cpu_to_be32(v); } while (0)
193		-#define ioc3_r_etcdc() be32_to_cpu(ioc3->etcdc)
194		-#define ioc3_w_etcdc(v) do { ioc3->etcdc = cpu_to_be32(v); } while (0)
195		-#define ioc3_r_ebir() be32_to_cpu(ioc3->ebir)
196		-#define ioc3_w_ebir(v) do { ioc3->ebir = cpu_to_be32(v); } while (0)
197		-#define ioc3_r_etbr_h() be32_to_cpu(ioc3->etbr_h)
198		-#define ioc3_w_etbr_h(v) do { ioc3->etbr_h = cpu_to_be32(v); } while (0)
199		-#define ioc3_r_etbr_l() be32_to_cpu(ioc3->etbr_l)
200		-#define ioc3_w_etbr_l(v) do { ioc3->etbr_l = cpu_to_be32(v); } while (0)
201		-#define ioc3_r_etcir() be32_to_cpu(ioc3->etcir)
202		-#define ioc3_w_etcir(v) do { ioc3->etcir = cpu_to_be32(v); } while (0)
203		-#define ioc3_r_etpir() be32_to_cpu(ioc3->etpir)
204		-#define ioc3_w_etpir(v) do { ioc3->etpir = cpu_to_be32(v); } while (0)
205		-#define ioc3_r_emar_h() be32_to_cpu(ioc3->emar_h)
206		-#define ioc3_w_emar_h(v) do { ioc3->emar_h = cpu_to_be32(v); } while (0)
207		-#define ioc3_r_emar_l() be32_to_cpu(ioc3->emar_l)
208		-#define ioc3_w_emar_l(v) do { ioc3->emar_l = cpu_to_be32(v); } while (0)
209		-#define ioc3_r_ehar_h() be32_to_cpu(ioc3->ehar_h)
210		-#define ioc3_w_ehar_h(v) do { ioc3->ehar_h = cpu_to_be32(v); } while (0)
211		-#define ioc3_r_ehar_l() be32_to_cpu(ioc3->ehar_l)
212		-#define ioc3_w_ehar_l(v) do { ioc3->ehar_l = cpu_to_be32(v); } while (0)
213		-#define ioc3_r_micr() be32_to_cpu(ioc3->micr)
214		-#define ioc3_w_micr(v) do { ioc3->micr = cpu_to_be32(v); } while (0)
215		-#define ioc3_r_midr_r() be32_to_cpu(ioc3->midr_r)
216		-#define ioc3_w_midr_r(v) do { ioc3->midr_r = cpu_to_be32(v); } while (0)
217		-#define ioc3_r_midr_w() be32_to_cpu(ioc3->midr_w)
218		-#define ioc3_w_midr_w(v) do { ioc3->midr_w = cpu_to_be32(v); } while (0)
219		-
220		-static inline u32 mcr_pack(u32 pulse, u32 sample)
221		-{
222		- return (pulse << 10) \| (sample << 2);
223		-}
224		-
225		-static int nic_wait(struct ioc3 *ioc3)
226		-{
227		- u32 mcr;
228		-
229		- do {
230		- mcr = ioc3_r_mcr();
231		- } while (!(mcr & 2));
232		-
233		- return mcr & 1;
234		-}
235		-
236		-static int nic_reset(struct ioc3 *ioc3)
237		-{
238		- int presence;
239		-
240		- ioc3_w_mcr(mcr_pack(500, 65));
241		- presence = nic_wait(ioc3);
242		-
243		- ioc3_w_mcr(mcr_pack(0, 500));
244		- nic_wait(ioc3);
245		-
246		- return presence;
247		-}
248		-
249		-static inline int nic_read_bit(struct ioc3 *ioc3)
250		-{
251		- int result;
252		-
253		- ioc3_w_mcr(mcr_pack(6, 13));
254		- result = nic_wait(ioc3);
255		- ioc3_w_mcr(mcr_pack(0, 100));
256		- nic_wait(ioc3);
257		-
258		- return result;
259		-}
260		-
261		-static inline void nic_write_bit(struct ioc3 *ioc3, int bit)
262		-{
263		- if (bit)
264		- ioc3_w_mcr(mcr_pack(6, 110));
265		- else
266		- ioc3_w_mcr(mcr_pack(80, 30));
267		-
268		- nic_wait(ioc3);
269		-}
270		-
271		-/*
272		- * Read a byte from an iButton device
273		- */
274		-static u32 nic_read_byte(struct ioc3 *ioc3)
275		-{
276		- u32 result = 0;
277		- int i;
278		-
279		- for (i = 0; i < 8; i++)
280		- result = (result >> 1) \| (nic_read_bit(ioc3) << 7);
281		-
282		- return result;
283		-}
284		-
285		-/*
286		- * Write a byte to an iButton device
287		- */
288		-static void nic_write_byte(struct ioc3 *ioc3, int byte)
289		-{
290		- int i, bit;
291		-
292		- for (i = 8; i; i--) {
293		- bit = byte & 1;
294		- byte >>= 1;
295		-
296		- nic_write_bit(ioc3, bit);
297		- }
298		-}
299		-
300		-static u64 nic_find(struct ioc3 ioc3, int last)
301		-{
302		- int a, b, index, disc;
303		- u64 address = 0;
304		-
305		- nic_reset(ioc3);
306		- /* Search ROM. */
307		- nic_write_byte(ioc3, 0xf0);
308		-
309		- /* Algorithm from ``Book of iButton Standards''. */
310		- for (index = 0, disc = 0; index < 64; index++) {
311		- a = nic_read_bit(ioc3);
312		- b = nic_read_bit(ioc3);
313		-
314		- if (a && b) {
315		- printk("NIC search failed (not fatal).\n");
316		- *last = 0;
317		- return 0;
318		- }
319		-
320		- if (!a && !b) {
321		- if (index == *last) {
322		- address \|= 1UL << index;
323		- } else if (index > *last) {
324		- address &= ~(1UL << index);
325		- disc = index;
326		- } else if ((address & (1UL << index)) == 0)
327		- disc = index;
328		- nic_write_bit(ioc3, address & (1UL << index));
329		- continue;
330		- } else {
331		- if (a)
332		- address \|= 1UL << index;
333		- else
334		- address &= ~(1UL << index);
335		- nic_write_bit(ioc3, a);
336		- continue;
337		- }
338		- }
339		-
340		- *last = disc;
341		-
342		- return address;
343		-}
344		-
345		-static int nic_init(struct ioc3 *ioc3)
346		-{
347		- const char *unknown = "unknown";
348		- const char *type = unknown;
349		- u8 crc;
350		- u8 serial[6];
351		- int save = 0, i;
352		-
353		- while (1) {
354		- u64 reg;
355		- reg = nic_find(ioc3, &save);
356		-
357		- switch (reg & 0xff) {
358		- case 0x91:
359		- type = "DS1981U";
360		- break;
361		- default:
362		- if (save == 0) {
363		- /* Let the caller try again. */
364		- return -1;
365		- }
366		- continue;
367		- }
368		-
369		- nic_reset(ioc3);
370		-
371		- /* Match ROM. */
372		- nic_write_byte(ioc3, 0x55);
373		- for (i = 0; i < 8; i++)
374		- nic_write_byte(ioc3, (reg >> (i << 3)) & 0xff);
375		-
376		- reg >>= 8; /* Shift out type. */
377		- for (i = 0; i < 6; i++) {
378		- serial[i] = reg & 0xff;
379		- reg >>= 8;
380		- }
381		- crc = reg & 0xff;
382		- break;
383		- }
384		-
385		- printk("Found %s NIC", type);
386		- if (type != unknown)
387		- printk (" registration number %pM, CRC %02x", serial, crc);
388		- printk(".\n");
	146	+ *rxb_dma = d;
	147	+ rxb = (struct ioc3_erxbuf )new_skb->data;
	148	+ skb_reserve(new_skb, RX_OFFSET);
	149	+ *skb = new_skb;
389	150
390	151	return 0;
391	152	}
392	153
393		-/*
394		- * Read the NIC (Number-In-a-Can) device used to store the MAC address on
395		- * SN0 / SN00 nodeboards and PCI cards.
396		- */
397		-static void ioc3_get_eaddr_nic(struct ioc3_private *ip)
	154	+#ifdef CONFIG_PCI_XTALK_BRIDGE
	155	+static inline unsigned long ioc3_map(dma_addr_t addr, unsigned long attr)
398	156	{
399		- struct ioc3 *ioc3 = ip->regs;
400		- u8 nic[14];
401		- int tries = 2; /* There may be some problem with the battery? */
402		- int i;
403		-
404		- ioc3_w_gpcr_s(1 << 21);
405		-
406		- while (tries--) {
407		- if (!nic_init(ioc3))
408		- break;
409		- udelay(500);
410		- }
411		-
412		- if (tries < 0) {
413		- printk("Failed to read MAC address\n");
414		- return;
415		- }
416		-
417		- /* Read Memory. */
418		- nic_write_byte(ioc3, 0xf0);
419		- nic_write_byte(ioc3, 0x00);
420		- nic_write_byte(ioc3, 0x00);
421		-
422		- for (i = 13; i >= 0; i--)
423		- nic[i] = nic_read_byte(ioc3);
424		-
425		- for (i = 2; i < 8; i++)
426		- ip->dev->dev_addr[i - 2] = nic[i];
	157	+ return (addr & ~PCI64_ATTR_BAR) \| attr;
427	158	}
428	159
429		-/*
430		- * Ok, this is hosed by design. It's necessary to know what machine the
431		- * NIC is in in order to know how to read the NIC address. We also have
432		- * to know if it's a PCI card or a NIC in on the node board ...
433		- */
434		-static void ioc3_get_eaddr(struct ioc3_private *ip)
	160	+#define ERBAR_VAL (ERBAR_BARRIER_BIT << ERBAR_RXBARR_SHIFT)
	161	+#else
	162	+static inline unsigned long ioc3_map(dma_addr_t addr, unsigned long attr)
435	163	{
436		- ioc3_get_eaddr_nic(ip);
	164	+ return addr;
	165	+}
437	166
438		- printk("Ethernet address is %pM.\n", ip->dev->dev_addr);
	167	+#define ERBAR_VAL 0
	168	+#endif
	169	+
	170	+static int ioc3eth_nvmem_match(struct device dev, const void data)
	171	+{
	172	+ const char *name = dev_name(dev);
	173	+ const char *prefix = data;
	174	+ int prefix_len;
	175	+
	176	+ prefix_len = strlen(prefix);
	177	+ if (strlen(name) < (prefix_len + 3))
	178	+ return 0;
	179	+
	180	+ if (memcmp(prefix, name, prefix_len) != 0)
	181	+ return 0;
	182	+
	183	+ /* found nvmem device which is attached to our ioc3
	184	+ * now check for one wire family code 09, 89 and 91
	185	+ */
	186	+ if (memcmp(name + prefix_len, "09-", 3) == 0)
	187	+ return 1;
	188	+ if (memcmp(name + prefix_len, "89-", 3) == 0)
	189	+ return 1;
	190	+ if (memcmp(name + prefix_len, "91-", 3) == 0)
	191	+ return 1;
	192	+
	193	+ return 0;
	194	+}
	195	+
	196	+static int ioc3eth_get_mac_addr(struct resource *res, u8 mac_addr[6])
	197	+{
	198	+ struct nvmem_device *nvmem;
	199	+ char prefix[24];
	200	+ u8 prom[16];
	201	+ int ret;
	202	+ int i;
	203	+
	204	+ snprintf(prefix, sizeof(prefix), "ioc3-%012llx-",
	205	+ res->start & ~0xffff);
	206	+
	207	+ nvmem = nvmem_device_find(prefix, ioc3eth_nvmem_match);
	208	+ if (IS_ERR(nvmem))
	209	+ return PTR_ERR(nvmem);
	210	+
	211	+ ret = nvmem_device_read(nvmem, 0, 16, prom);
	212	+ nvmem_device_put(nvmem);
	213	+ if (ret < 0)
	214	+ return ret;
	215	+
	216	+ /* check, if content is valid */
	217	+ if (prom[0] != 0x0a \|\|
	218	+ crc16(CRC16_INIT, prom, 13) != CRC16_VALID)
	219	+ return -EINVAL;
	220	+
	221	+ for (i = 0; i < 6; i++)
	222	+ mac_addr[i] = prom[10 - i];
	223	+
	224	+ return 0;
439	225	}
440	226
441	227	static void __ioc3_set_mac_address(struct net_device *dev)
442	228	{
443	229	struct ioc3_private *ip = netdev_priv(dev);
444		- struct ioc3 *ioc3 = ip->regs;
445	230
446		- ioc3_w_emar_h((dev->dev_addr[5] << 8) \| dev->dev_addr[4]);
447		- ioc3_w_emar_l((dev->dev_addr[3] << 24) \| (dev->dev_addr[2] << 16) \|
448		- (dev->dev_addr[1] << 8) \| dev->dev_addr[0]);
	231	+ writel((dev->dev_addr[5] << 8) \|
	232	+ dev->dev_addr[4],
	233	+ &ip->regs->emar_h);
	234	+ writel((dev->dev_addr[3] << 24) \|
	235	+ (dev->dev_addr[2] << 16) \|
	236	+ (dev->dev_addr[1] << 8) \|
	237	+ dev->dev_addr[0],
	238	+ &ip->regs->emar_l);
449	239	}
450	240
451	241	static int ioc3_set_mac_address(struct net_device dev, void addr)
..	..	@@ -462,31 +252,35 @@
462	252	return 0;
463	253	}
464	254
465		-/*
466		- * Caller must hold the ioc3_lock ever for MII readers. This is also
	255	+/* Caller must hold the ioc3_lock ever for MII readers. This is also
467	256	* used to protect the transmitter side but it's low contention.
468	257	*/
469	258	static int ioc3_mdio_read(struct net_device *dev, int phy, int reg)
470	259	{
471	260	struct ioc3_private *ip = netdev_priv(dev);
472		- struct ioc3 *ioc3 = ip->regs;
	261	+ struct ioc3_ethregs *regs = ip->regs;
473	262
474		- while (ioc3_r_micr() & MICR_BUSY);
475		- ioc3_w_micr((phy << MICR_PHYADDR_SHIFT) \| reg \| MICR_READTRIG);
476		- while (ioc3_r_micr() & MICR_BUSY);
	263	+ while (readl(&regs->micr) & MICR_BUSY)
	264	+ ;
	265	+ writel((phy << MICR_PHYADDR_SHIFT) \| reg \| MICR_READTRIG,
	266	+ &regs->micr);
	267	+ while (readl(&regs->micr) & MICR_BUSY)
	268	+ ;
477	269
478		- return ioc3_r_midr_r() & MIDR_DATA_MASK;
	270	+ return readl(&regs->midr_r) & MIDR_DATA_MASK;
479	271	}
480	272
481	273	static void ioc3_mdio_write(struct net_device *dev, int phy, int reg, int data)
482	274	{
483	275	struct ioc3_private *ip = netdev_priv(dev);
484		- struct ioc3 *ioc3 = ip->regs;
	276	+ struct ioc3_ethregs *regs = ip->regs;
485	277
486		- while (ioc3_r_micr() & MICR_BUSY);
487		- ioc3_w_midr_w(data);
488		- ioc3_w_micr((phy << MICR_PHYADDR_SHIFT) \| reg);
489		- while (ioc3_r_micr() & MICR_BUSY);
	278	+ while (readl(&regs->micr) & MICR_BUSY)
	279	+ ;
	280	+ writel(data, &regs->midr_w);
	281	+ writel((phy << MICR_PHYADDR_SHIFT) \| reg, &regs->micr);
	282	+ while (readl(&regs->micr) & MICR_BUSY)
	283	+ ;
490	284	}
491	285
492	286	static int ioc3_mii_init(struct ioc3_private *ip);
..	..	@@ -494,23 +288,22 @@
494	288	static struct net_device_stats ioc3_get_stats(struct net_device dev)
495	289	{
496	290	struct ioc3_private *ip = netdev_priv(dev);
497		- struct ioc3 *ioc3 = ip->regs;
	291	+ struct ioc3_ethregs *regs = ip->regs;
498	292
499		- dev->stats.collisions += (ioc3_r_etcdc() & ETCDC_COLLCNT_MASK);
	293	+ dev->stats.collisions += readl(&regs->etcdc) & ETCDC_COLLCNT_MASK;
500	294	return &dev->stats;
501	295	}
502	296
503		-static void ioc3_tcpudp_checksum(struct sk_buff *skb, uint32_t hwsum, int len)
	297	+static void ioc3_tcpudp_checksum(struct sk_buff *skb, u32 hwsum, int len)
504	298	{
505	299	struct ethhdr *eh = eth_hdr(skb);
506		- uint32_t csum, ehsum;
507	300	unsigned int proto;
508		- struct iphdr *ih;
509		- uint16_t *ew;
510	301	unsigned char *cp;
	302	+ struct iphdr *ih;
	303	+ u32 csum, ehsum;
	304	+ u16 *ew;
511	305
512		- /*
513		- * Did hardware handle the checksum at all? The cases we can handle
	306	+ /* Did hardware handle the checksum at all? The cases we can handle
514	307	* are:
515	308	*
516	309	* - TCP and UDP checksums of IPv4 only.
..	..	@@ -526,7 +319,7 @@
526	319	if (eh->h_proto != htons(ETH_P_IP))
527	320	return;
528	321
529		- ih = (struct iphdr ) ((char )eh + ETH_HLEN);
	322	+ ih = (struct iphdr )((char )eh + ETH_HLEN);
530	323	if (ip_is_fragment(ih))
531	324	return;
532	325
..	..	@@ -537,12 +330,12 @@
537	330	/* Same as tx - compute csum of pseudo header */
538	331	csum = hwsum +
539	332	(ih->tot_len - (ih->ihl << 2)) +
540		- htons((uint16_t)ih->protocol) +
	333	+ htons((u16)ih->protocol) +
541	334	(ih->saddr >> 16) + (ih->saddr & 0xffff) +
542	335	(ih->daddr >> 16) + (ih->daddr & 0xffff);
543	336
544	337	/* Sum up ethernet dest addr, src addr and protocol */
545		- ew = (uint16_t *) eh;
	338	+ ew = (u16 *)eh;
546	339	ehsum = ew[0] + ew[1] + ew[2] + ew[3] + ew[4] + ew[5] + ew[6];
547	340
548	341	ehsum = (ehsum & 0xffff) + (ehsum >> 16);
..	..	@@ -551,14 +344,15 @@
551	344	csum += 0xffff ^ ehsum;
552	345
553	346	/* In the next step we also subtract the 1's complement
554		- checksum of the trailing ethernet CRC. */
	347	+ * checksum of the trailing ethernet CRC.
	348	+ */
555	349	cp = (char )eh + len; / points at trailing CRC */
556	350	if (len & 1) {
557		- csum += 0xffff ^ (uint16_t) ((cp[1] << 8) \| cp[0]);
558		- csum += 0xffff ^ (uint16_t) ((cp[3] << 8) \| cp[2]);
	351	+ csum += 0xffff ^ (u16)((cp[1] << 8) \| cp[0]);
	352	+ csum += 0xffff ^ (u16)((cp[3] << 8) \| cp[2]);
559	353	} else {
560		- csum += 0xffff ^ (uint16_t) ((cp[0] << 8) \| cp[1]);
561		- csum += 0xffff ^ (uint16_t) ((cp[2] << 8) \| cp[3]);
	354	+ csum += 0xffff ^ (u16)((cp[0] << 8) \| cp[1]);
	355	+ csum += 0xffff ^ (u16)((cp[2] << 8) \| cp[3]);
562	356	}
563	357
564	358	csum = (csum & 0xffff) + (csum >> 16);
..	..	@@ -572,10 +366,10 @@
572	366	{
573	367	struct ioc3_private *ip = netdev_priv(dev);
574	368	struct sk_buff skb, new_skb;
575		- struct ioc3 *ioc3 = ip->regs;
576	369	int rx_entry, n_entry, len;
577	370	struct ioc3_erxbuf *rxb;
578	371	unsigned long *rxr;
	372	+ dma_addr_t d;
579	373	u32 w0, err;
580	374
581	375	rxr = ip->rxr; /* Ring base */
..	..	@@ -583,64 +377,67 @@
583	377	n_entry = ip->rx_pi;
584	378
585	379	skb = ip->rx_skbs[rx_entry];
586		- rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
	380	+ rxb = (struct ioc3_erxbuf *)(skb->data - RX_OFFSET);
587	381	w0 = be32_to_cpu(rxb->w0);
588	382
589	383	while (w0 & ERXBUF_V) {
590	384	err = be32_to_cpu(rxb->err); /* It's valid ... */
591	385	if (err & ERXBUF_GOODPKT) {
592	386	len = ((w0 >> ERXBUF_BYTECNT_SHIFT) & 0x7ff) - 4;
593		- skb_trim(skb, len);
	387	+ skb_put(skb, len);
594	388	skb->protocol = eth_type_trans(skb, dev);
595	389
596		- new_skb = ioc3_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
597		- if (!new_skb) {
	390	+ if (ioc3_alloc_skb(ip, &new_skb, &rxb, &d)) {
598	391	/* Ouch, drop packet and just recycle packet
599		- to keep the ring filled. */
	392	+ * to keep the ring filled.
	393	+ */
600	394	dev->stats.rx_dropped++;
601	395	new_skb = skb;
	396	+ d = rxr[rx_entry];
602	397	goto next;
603	398	}
604	399
605	400	if (likely(dev->features & NETIF_F_RXCSUM))
606	401	ioc3_tcpudp_checksum(skb,
607		- w0 & ERXBUF_IPCKSUM_MASK, len);
	402	+ w0 & ERXBUF_IPCKSUM_MASK,
	403	+ len);
	404	+
	405	+ dma_unmap_single(ip->dma_dev, rxr[rx_entry],
	406	+ RX_BUF_SIZE, DMA_FROM_DEVICE);
608	407
609	408	netif_rx(skb);
610	409
611	410	ip->rx_skbs[rx_entry] = NULL; /* Poison */
612	411
613		- /* Because we reserve afterwards. */
614		- skb_put(new_skb, (1664 + RX_OFFSET));
615		- rxb = (struct ioc3_erxbuf *) new_skb->data;
616		- skb_reserve(new_skb, RX_OFFSET);
617		-
618	412	dev->stats.rx_packets++; /* Statistics */
619	413	dev->stats.rx_bytes += len;
620	414	} else {
621	415	/* The frame is invalid and the skb never
622		- reached the network layer so we can just
623		- recycle it. */
	416	+ * reached the network layer so we can just
	417	+ * recycle it.
	418	+ */
624	419	new_skb = skb;
	420	+ d = rxr[rx_entry];
625	421	dev->stats.rx_errors++;
626	422	}
627	423	if (err & ERXBUF_CRCERR) /* Statistics */
628	424	dev->stats.rx_crc_errors++;
629	425	if (err & ERXBUF_FRAMERR)
630	426	dev->stats.rx_frame_errors++;
	427	+
631	428	next:
632	429	ip->rx_skbs[n_entry] = new_skb;
633		- rxr[n_entry] = cpu_to_be64(ioc3_map(rxb, 1));
	430	+ rxr[n_entry] = cpu_to_be64(ioc3_map(d, PCI64_ATTR_BAR));
634	431	rxb->w0 = 0; /* Clear valid flag */
635		- n_entry = (n_entry + 1) & 511; /* Update erpir */
	432	+ n_entry = (n_entry + 1) & RX_RING_MASK; /* Update erpir */
636	433
637	434	/* Now go on to the next ring entry. */
638		- rx_entry = (rx_entry + 1) & 511;
	435	+ rx_entry = (rx_entry + 1) & RX_RING_MASK;
639	436	skb = ip->rx_skbs[rx_entry];
640		- rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
	437	+ rxb = (struct ioc3_erxbuf *)(skb->data - RX_OFFSET);
641	438	w0 = be32_to_cpu(rxb->w0);
642	439	}
643		- ioc3_w_erpir((n_entry << 3) \| ERPIR_ARM);
	440	+ writel((n_entry << 3) \| ERPIR_ARM, &ip->regs->erpir);
644	441	ip->rx_pi = n_entry;
645	442	ip->rx_ci = rx_entry;
646	443	}
..	..	@@ -648,16 +445,16 @@
648	445	static inline void ioc3_tx(struct net_device *dev)
649	446	{
650	447	struct ioc3_private *ip = netdev_priv(dev);
	448	+ struct ioc3_ethregs *regs = ip->regs;
651	449	unsigned long packets, bytes;
652		- struct ioc3 *ioc3 = ip->regs;
653	450	int tx_entry, o_entry;
654	451	struct sk_buff *skb;
655	452	u32 etcir;
656	453
657	454	spin_lock(&ip->ioc3_lock);
658		- etcir = ioc3_r_etcir();
	455	+ etcir = readl(&regs->etcir);
659	456
660		- tx_entry = (etcir >> 7) & 127;
	457	+ tx_entry = (etcir >> 7) & TX_RING_MASK;
661	458	o_entry = ip->tx_ci;
662	459	packets = 0;
663	460	bytes = 0;
..	..	@@ -666,28 +463,27 @@
666	463	packets++;
667	464	skb = ip->tx_skbs[o_entry];
668	465	bytes += skb->len;
669		- dev_kfree_skb_irq(skb);
	466	+ dev_consume_skb_irq(skb);
670	467	ip->tx_skbs[o_entry] = NULL;
671	468
672		- o_entry = (o_entry + 1) & 127; /* Next */
	469	+ o_entry = (o_entry + 1) & TX_RING_MASK; /* Next */
673	470
674		- etcir = ioc3_r_etcir(); /* More pkts sent? */
675		- tx_entry = (etcir >> 7) & 127;
	471	+ etcir = readl(&regs->etcir); /* More pkts sent? */
	472	+ tx_entry = (etcir >> 7) & TX_RING_MASK;
676	473	}
677	474
678	475	dev->stats.tx_packets += packets;
679	476	dev->stats.tx_bytes += bytes;
680	477	ip->txqlen -= packets;
681	478
682		- if (ip->txqlen < 128)
	479	+ if (netif_queue_stopped(dev) && ip->txqlen < TX_RING_ENTRIES)
683	480	netif_wake_queue(dev);
684	481
685	482	ip->tx_ci = o_entry;
686	483	spin_unlock(&ip->ioc3_lock);
687	484	}
688	485
689		-/*
690		- * Deal with fatal IOC3 errors. This condition might be caused by a hard or
	486	+/* Deal with fatal IOC3 errors. This condition might be caused by a hard or
691	487	* software problems, so we should try to recover
692	488	* more gracefully if this ever happens. In theory we might be flooded
693	489	* with such error interrupts if something really goes wrong, so we might
..	..	@@ -696,25 +492,33 @@
696	492	static void ioc3_error(struct net_device *dev, u32 eisr)
697	493	{
698	494	struct ioc3_private *ip = netdev_priv(dev);
699		- unsigned char *iface = dev->name;
700	495
701	496	spin_lock(&ip->ioc3_lock);
702	497
703	498	if (eisr & EISR_RXOFLO)
704		- printk(KERN_ERR "%s: RX overflow.\n", iface);
	499	+ net_err_ratelimited("%s: RX overflow.\n", dev->name);
705	500	if (eisr & EISR_RXBUFOFLO)
706		- printk(KERN_ERR "%s: RX buffer overflow.\n", iface);
	501	+ net_err_ratelimited("%s: RX buffer overflow.\n", dev->name);
707	502	if (eisr & EISR_RXMEMERR)
708		- printk(KERN_ERR "%s: RX PCI error.\n", iface);
	503	+ net_err_ratelimited("%s: RX PCI error.\n", dev->name);
709	504	if (eisr & EISR_RXPARERR)
710		- printk(KERN_ERR "%s: RX SSRAM parity error.\n", iface);
	505	+ net_err_ratelimited("%s: RX SSRAM parity error.\n", dev->name);
711	506	if (eisr & EISR_TXBUFUFLO)
712		- printk(KERN_ERR "%s: TX buffer underflow.\n", iface);
	507	+ net_err_ratelimited("%s: TX buffer underflow.\n", dev->name);
713	508	if (eisr & EISR_TXMEMERR)
714		- printk(KERN_ERR "%s: TX PCI error.\n", iface);
	509	+ net_err_ratelimited("%s: TX PCI error.\n", dev->name);
715	510
716	511	ioc3_stop(ip);
	512	+ ioc3_free_rx_bufs(ip);
	513	+ ioc3_clean_tx_ring(ip);
	514	+
717	515	ioc3_init(dev);
	516	+ if (ioc3_alloc_rx_bufs(dev)) {
	517	+ netdev_err(dev, "%s: rx buffer allocation failed\n", __func__);
	518	+ spin_unlock(&ip->ioc3_lock);
	519	+ return;
	520	+ }
	521	+ ioc3_start(ip);
718	522	ioc3_mii_init(ip);
719	523
720	524	netif_wake_queue(dev);
..	..	@@ -723,45 +527,45 @@
723	527	}
724	528
725	529	/* The interrupt handler does all of the Rx thread work and cleans up
726		- after the Tx thread. */
727		-static irqreturn_t ioc3_interrupt(int irq, void *_dev)
	530	+ * after the Tx thread.
	531	+ */
	532	+static irqreturn_t ioc3_interrupt(int irq, void *dev_id)
728	533	{
729		- struct net_device dev = (struct net_device )_dev;
730		- struct ioc3_private *ip = netdev_priv(dev);
731		- struct ioc3 *ioc3 = ip->regs;
732		- const u32 enabled = EISR_RXTIMERINT \| EISR_RXOFLO \| EISR_RXBUFOFLO \|
733		- EISR_RXMEMERR \| EISR_RXPARERR \| EISR_TXBUFUFLO \|
734		- EISR_TXEXPLICIT \| EISR_TXMEMERR;
	534	+ struct ioc3_private *ip = netdev_priv(dev_id);
	535	+ struct ioc3_ethregs *regs = ip->regs;
735	536	u32 eisr;
736	537
737		- eisr = ioc3_r_eisr() & enabled;
738		-
739		- ioc3_w_eisr(eisr);
740		- (void) ioc3_r_eisr(); /* Flush */
	538	+ eisr = readl(&regs->eisr);
	539	+ writel(eisr, &regs->eisr);
	540	+ readl(&regs->eisr); /* Flush */
741	541
742	542	if (eisr & (EISR_RXOFLO \| EISR_RXBUFOFLO \| EISR_RXMEMERR \|
743		- EISR_RXPARERR \| EISR_TXBUFUFLO \| EISR_TXMEMERR))
744		- ioc3_error(dev, eisr);
	543	+ EISR_RXPARERR \| EISR_TXBUFUFLO \| EISR_TXMEMERR))
	544	+ ioc3_error(dev_id, eisr);
745	545	if (eisr & EISR_RXTIMERINT)
746		- ioc3_rx(dev);
	546	+ ioc3_rx(dev_id);
747	547	if (eisr & EISR_TXEXPLICIT)
748		- ioc3_tx(dev);
	548	+ ioc3_tx(dev_id);
749	549
750	550	return IRQ_HANDLED;
751	551	}
752	552
753	553	static inline void ioc3_setup_duplex(struct ioc3_private *ip)
754	554	{
755		- struct ioc3 *ioc3 = ip->regs;
	555	+ struct ioc3_ethregs *regs = ip->regs;
	556	+
	557	+ spin_lock_irq(&ip->ioc3_lock);
756	558
757	559	if (ip->mii.full_duplex) {
758		- ioc3_w_etcsr(ETCSR_FD);
	560	+ writel(ETCSR_FD, &regs->etcsr);
759	561	ip->emcr \|= EMCR_DUPLEX;
760	562	} else {
761		- ioc3_w_etcsr(ETCSR_HD);
	563	+ writel(ETCSR_HD, &regs->etcsr);
762	564	ip->emcr &= ~EMCR_DUPLEX;
763	565	}
764		- ioc3_w_emcr(ip->emcr);
	566	+ writel(ip->emcr, &regs->emcr);
	567	+
	568	+ spin_unlock_irq(&ip->ioc3_lock);
765	569	}
766	570
767	571	static void ioc3_timer(struct timer_list *t)
..	..	@@ -772,72 +576,54 @@
772	576	mii_check_media(&ip->mii, 1, 0);
773	577	ioc3_setup_duplex(ip);
774	578
775		- ip->ioc3_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2s */
	579	+ ip->ioc3_timer.expires = jiffies + ((12 * HZ) / 10); /* 1.2s */
776	580	add_timer(&ip->ioc3_timer);
777	581	}
778	582
779		-/*
780		- * Try to find a PHY. There is no apparent relation between the MII addresses
	583	+/* Try to find a PHY. There is no apparent relation between the MII addresses
781	584	* in the SGI documentation and what we find in reality, so we simply probe
782		- * for the PHY. It seems IOC3 PHYs usually live on address 31. One of my
783		- * onboard IOC3s has the special oddity that probing doesn't seem to find it
784		- * yet the interface seems to work fine, so if probing fails we for now will
785		- * simply default to PHY 31 instead of bailing out.
	585	+ * for the PHY.
786	586	*/
787	587	static int ioc3_mii_init(struct ioc3_private *ip)
788	588	{
789		- int i, found = 0, res = 0;
790		- int ioc3_phy_workaround = 1;
791	589	u16 word;
	590	+ int i;
792	591
793	592	for (i = 0; i < 32; i++) {
794		- word = ioc3_mdio_read(ip->dev, i, MII_PHYSID1);
	593	+ word = ioc3_mdio_read(ip->mii.dev, i, MII_PHYSID1);
795	594
796	595	if (word != 0xffff && word != 0x0000) {
797		- found = 1;
798		- break; /* Found a PHY */
	596	+ ip->mii.phy_id = i;
	597	+ return 0;
799	598	}
800	599	}
801		-
802		- if (!found) {
803		- if (ioc3_phy_workaround)
804		- i = 31;
805		- else {
806		- ip->mii.phy_id = -1;
807		- res = -ENODEV;
808		- goto out;
809		- }
810		- }
811		-
812		- ip->mii.phy_id = i;
813		-
814		-out:
815		- return res;
	600	+ ip->mii.phy_id = -1;
	601	+ return -ENODEV;
816	602	}
817	603
818	604	static void ioc3_mii_start(struct ioc3_private *ip)
819	605	{
820		- ip->ioc3_timer.expires = jiffies + (12 * HZ)/10; /* 1.2 sec. */
	606	+ ip->ioc3_timer.expires = jiffies + (12 * HZ) / 10; /* 1.2 sec. */
821	607	add_timer(&ip->ioc3_timer);
822	608	}
823	609
824		-static inline void ioc3_clean_rx_ring(struct ioc3_private *ip)
	610	+static inline void ioc3_tx_unmap(struct ioc3_private *ip, int entry)
825	611	{
826		- struct sk_buff *skb;
827		- int i;
	612	+ struct ioc3_etxd *desc;
	613	+ u32 cmd, bufcnt, len;
828	614
829		- for (i = ip->rx_ci; i & 15; i++) {
830		- ip->rx_skbs[ip->rx_pi] = ip->rx_skbs[ip->rx_ci];
831		- ip->rxr[ip->rx_pi++] = ip->rxr[ip->rx_ci++];
	615	+ desc = &ip->txr[entry];
	616	+ cmd = be32_to_cpu(desc->cmd);
	617	+ bufcnt = be32_to_cpu(desc->bufcnt);
	618	+ if (cmd & ETXD_B1V) {
	619	+ len = (bufcnt & ETXD_B1CNT_MASK) >> ETXD_B1CNT_SHIFT;
	620	+ dma_unmap_single(ip->dma_dev, be64_to_cpu(desc->p1),
	621	+ len, DMA_TO_DEVICE);
832	622	}
833		- ip->rx_pi &= 511;
834		- ip->rx_ci &= 511;
835		-
836		- for (i = ip->rx_ci; i != ip->rx_pi; i = (i+1) & 511) {
837		- struct ioc3_erxbuf *rxb;
838		- skb = ip->rx_skbs[i];
839		- rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
840		- rxb->w0 = 0;
	623	+ if (cmd & ETXD_B2V) {
	624	+ len = (bufcnt & ETXD_B2CNT_MASK) >> ETXD_B2CNT_SHIFT;
	625	+ dma_unmap_single(ip->dma_dev, be64_to_cpu(desc->p2),
	626	+ len, DMA_TO_DEVICE);
841	627	}
842	628	}
843	629
..	..	@@ -846,9 +632,10 @@
846	632	struct sk_buff *skb;
847	633	int i;
848	634
849		- for (i=0; i < 128; i++) {
	635	+ for (i = 0; i < TX_RING_ENTRIES; i++) {
850	636	skb = ip->tx_skbs[i];
851	637	if (skb) {
	638	+ ioc3_tx_unmap(ip, i);
852	639	ip->tx_skbs[i] = NULL;
853	640	dev_kfree_skb_any(skb);
854	641	}
..	..	@@ -858,194 +645,152 @@
858	645	ip->tx_ci = 0;
859	646	}
860	647
861		-static void ioc3_free_rings(struct ioc3_private *ip)
	648	+static void ioc3_free_rx_bufs(struct ioc3_private *ip)
862	649	{
863		- struct sk_buff *skb;
864	650	int rx_entry, n_entry;
	651	+ struct sk_buff *skb;
865	652
866		- if (ip->txr) {
867		- ioc3_clean_tx_ring(ip);
868		- free_pages((unsigned long)ip->txr, 2);
869		- ip->txr = NULL;
870		- }
	653	+ n_entry = ip->rx_ci;
	654	+ rx_entry = ip->rx_pi;
871	655
872		- if (ip->rxr) {
873		- n_entry = ip->rx_ci;
874		- rx_entry = ip->rx_pi;
875		-
876		- while (n_entry != rx_entry) {
877		- skb = ip->rx_skbs[n_entry];
878		- if (skb)
879		- dev_kfree_skb_any(skb);
880		-
881		- n_entry = (n_entry + 1) & 511;
	656	+ while (n_entry != rx_entry) {
	657	+ skb = ip->rx_skbs[n_entry];
	658	+ if (skb) {
	659	+ dma_unmap_single(ip->dma_dev,
	660	+ be64_to_cpu(ip->rxr[n_entry]),
	661	+ RX_BUF_SIZE, DMA_FROM_DEVICE);
	662	+ dev_kfree_skb_any(skb);
882	663	}
883		- free_page((unsigned long)ip->rxr);
884		- ip->rxr = NULL;
	664	+ n_entry = (n_entry + 1) & RX_RING_MASK;
885	665	}
886	666	}
887	667
888		-static void ioc3_alloc_rings(struct net_device *dev)
	668	+static int ioc3_alloc_rx_bufs(struct net_device *dev)
889	669	{
890	670	struct ioc3_private *ip = netdev_priv(dev);
891	671	struct ioc3_erxbuf *rxb;
892		- unsigned long *rxr;
	672	+ dma_addr_t d;
893	673	int i;
894	674
895		- if (ip->rxr == NULL) {
896		- /* Allocate and initialize rx ring. 4kb = 512 entries */
897		- ip->rxr = (unsigned long *) get_zeroed_page(GFP_ATOMIC);
898		- rxr = ip->rxr;
899		- if (!rxr)
900		- printk("ioc3_alloc_rings(): get_zeroed_page() failed!\n");
	675	+ /* Now the rx buffers. The RX ring may be larger but
	676	+ * we only allocate 16 buffers for now. Need to tune
	677	+ * this for performance and memory later.
	678	+ */
	679	+ for (i = 0; i < RX_BUFFS; i++) {
	680	+ if (ioc3_alloc_skb(ip, &ip->rx_skbs[i], &rxb, &d))
	681	+ return -ENOMEM;
901	682
902		- /* Now the rx buffers. The RX ring may be larger but
903		- we only allocate 16 buffers for now. Need to tune
904		- this for performance and memory later. */
905		- for (i = 0; i < RX_BUFFS; i++) {
906		- struct sk_buff *skb;
907		-
908		- skb = ioc3_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
909		- if (!skb) {
910		- show_free_areas(0, NULL);
911		- continue;
912		- }
913		-
914		- ip->rx_skbs[i] = skb;
915		-
916		- /* Because we reserve afterwards. */
917		- skb_put(skb, (1664 + RX_OFFSET));
918		- rxb = (struct ioc3_erxbuf *) skb->data;
919		- rxr[i] = cpu_to_be64(ioc3_map(rxb, 1));
920		- skb_reserve(skb, RX_OFFSET);
921		- }
922		- ip->rx_ci = 0;
923		- ip->rx_pi = RX_BUFFS;
	683	+ rxb->w0 = 0; /* Clear valid flag */
	684	+ ip->rxr[i] = cpu_to_be64(ioc3_map(d, PCI64_ATTR_BAR));
924	685	}
	686	+ ip->rx_ci = 0;
	687	+ ip->rx_pi = RX_BUFFS;
925	688
926		- if (ip->txr == NULL) {
927		- /* Allocate and initialize tx rings. 16kb = 128 bufs. */
928		- ip->txr = (struct ioc3_etxd *)__get_free_pages(GFP_KERNEL, 2);
929		- if (!ip->txr)
930		- printk("ioc3_alloc_rings(): __get_free_pages() failed!\n");
931		- ip->tx_pi = 0;
932		- ip->tx_ci = 0;
933		- }
934		-}
935		-
936		-static void ioc3_init_rings(struct net_device *dev)
937		-{
938		- struct ioc3_private *ip = netdev_priv(dev);
939		- struct ioc3 *ioc3 = ip->regs;
940		- unsigned long ring;
941		-
942		- ioc3_free_rings(ip);
943		- ioc3_alloc_rings(dev);
944		-
945		- ioc3_clean_rx_ring(ip);
946		- ioc3_clean_tx_ring(ip);
947		-
948		- /* Now the rx ring base, consume & produce registers. */
949		- ring = ioc3_map(ip->rxr, 0);
950		- ioc3_w_erbr_h(ring >> 32);
951		- ioc3_w_erbr_l(ring & 0xffffffff);
952		- ioc3_w_ercir(ip->rx_ci << 3);
953		- ioc3_w_erpir((ip->rx_pi << 3) \| ERPIR_ARM);
954		-
955		- ring = ioc3_map(ip->txr, 0);
956		-
957		- ip->txqlen = 0; /* nothing queued */
958		-
959		- /* Now the tx ring base, consume & produce registers. */
960		- ioc3_w_etbr_h(ring >> 32);
961		- ioc3_w_etbr_l(ring & 0xffffffff);
962		- ioc3_w_etpir(ip->tx_pi << 7);
963		- ioc3_w_etcir(ip->tx_ci << 7);
964		- (void) ioc3_r_etcir(); /* Flush */
	689	+ return 0;
965	690	}
966	691
967	692	static inline void ioc3_ssram_disc(struct ioc3_private *ip)
968	693	{
969		- struct ioc3 *ioc3 = ip->regs;
970		- volatile u32 *ssram0 = &ioc3->ssram[0x0000];
971		- volatile u32 *ssram1 = &ioc3->ssram[0x4000];
972		- unsigned int pattern = 0x5555;
	694	+ struct ioc3_ethregs *regs = ip->regs;
	695	+ u32 *ssram0 = &ip->ssram[0x0000];
	696	+ u32 *ssram1 = &ip->ssram[0x4000];
	697	+ u32 pattern = 0x5555;
973	698
974	699	/* Assume the larger size SSRAM and enable parity checking */
975		- ioc3_w_emcr(ioc3_r_emcr() \| (EMCR_BUFSIZ \| EMCR_RAMPAR));
	700	+ writel(readl(&regs->emcr) \| (EMCR_BUFSIZ \| EMCR_RAMPAR), &regs->emcr);
	701	+ readl(&regs->emcr); /* Flush */
976	702
977		- *ssram0 = pattern;
978		- *ssram1 = ~pattern & IOC3_SSRAM_DM;
	703	+ writel(pattern, ssram0);
	704	+ writel(~pattern & IOC3_SSRAM_DM, ssram1);
979	705
980		- if ((*ssram0 & IOC3_SSRAM_DM) != pattern \|\|
981		- (*ssram1 & IOC3_SSRAM_DM) != (~pattern & IOC3_SSRAM_DM)) {
	706	+ if ((readl(ssram0) & IOC3_SSRAM_DM) != pattern \|\|
	707	+ (readl(ssram1) & IOC3_SSRAM_DM) != (~pattern & IOC3_SSRAM_DM)) {
982	708	/* set ssram size to 64 KB */
983		- ip->emcr = EMCR_RAMPAR;
984		- ioc3_w_emcr(ioc3_r_emcr() & ~EMCR_BUFSIZ);
985		- } else
986		- ip->emcr = EMCR_BUFSIZ \| EMCR_RAMPAR;
	709	+ ip->emcr \|= EMCR_RAMPAR;
	710	+ writel(readl(&regs->emcr) & ~EMCR_BUFSIZ, &regs->emcr);
	711	+ } else {
	712	+ ip->emcr \|= EMCR_BUFSIZ \| EMCR_RAMPAR;
	713	+ }
987	714	}
988	715
989	716	static void ioc3_init(struct net_device *dev)
990	717	{
991	718	struct ioc3_private *ip = netdev_priv(dev);
992		- struct ioc3 *ioc3 = ip->regs;
	719	+ struct ioc3_ethregs *regs = ip->regs;
993	720
994	721	del_timer_sync(&ip->ioc3_timer); /* Kill if running */
995	722
996		- ioc3_w_emcr(EMCR_RST); /* Reset */
997		- (void) ioc3_r_emcr(); /* Flush WB */
	723	+ writel(EMCR_RST, &regs->emcr); /* Reset */
	724	+ readl(&regs->emcr); /* Flush WB */
998	725	udelay(4); /* Give it time ... */
999		- ioc3_w_emcr(0);
1000		- (void) ioc3_r_emcr();
	726	+ writel(0, &regs->emcr);
	727	+ readl(&regs->emcr);
1001	728
1002	729	/* Misc registers */
1003		-#ifdef CONFIG_SGI_IP27
1004		- ioc3_w_erbar(PCI64_ATTR_BAR >> 32); /* Barrier on last store */
1005		-#else
1006		- ioc3_w_erbar(0); /* Let PCI API get it right */
1007		-#endif
1008		- (void) ioc3_r_etcdc(); /* Clear on read */
1009		- ioc3_w_ercsr(15); /* RX low watermark */
1010		- ioc3_w_ertr(0); /* Interrupt immediately */
	730	+ writel(ERBAR_VAL, &regs->erbar);
	731	+ readl(&regs->etcdc); /* Clear on read */
	732	+ writel(15, &regs->ercsr); /* RX low watermark */
	733	+ writel(0, &regs->ertr); /* Interrupt immediately */
1011	734	__ioc3_set_mac_address(dev);
1012		- ioc3_w_ehar_h(ip->ehar_h);
1013		- ioc3_w_ehar_l(ip->ehar_l);
1014		- ioc3_w_ersr(42); /* XXX should be random */
	735	+ writel(ip->ehar_h, &regs->ehar_h);
	736	+ writel(ip->ehar_l, &regs->ehar_l);
	737	+ writel(42, &regs->ersr); /* XXX should be random */
	738	+}
1015	739
1016		- ioc3_init_rings(dev);
	740	+static void ioc3_start(struct ioc3_private *ip)
	741	+{
	742	+ struct ioc3_ethregs *regs = ip->regs;
	743	+ unsigned long ring;
	744	+
	745	+ /* Now the rx ring base, consume & produce registers. */
	746	+ ring = ioc3_map(ip->rxr_dma, PCI64_ATTR_PREC);
	747	+ writel(ring >> 32, &regs->erbr_h);
	748	+ writel(ring & 0xffffffff, &regs->erbr_l);
	749	+ writel(ip->rx_ci << 3, &regs->ercir);
	750	+ writel((ip->rx_pi << 3) \| ERPIR_ARM, &regs->erpir);
	751	+
	752	+ ring = ioc3_map(ip->txr_dma, PCI64_ATTR_PREC);
	753	+
	754	+ ip->txqlen = 0; /* nothing queued */
	755	+
	756	+ /* Now the tx ring base, consume & produce registers. */
	757	+ writel(ring >> 32, &regs->etbr_h);
	758	+ writel(ring & 0xffffffff, &regs->etbr_l);
	759	+ writel(ip->tx_pi << 7, &regs->etpir);
	760	+ writel(ip->tx_ci << 7, &regs->etcir);
	761	+ readl(&regs->etcir); /* Flush */
1017	762
1018	763	ip->emcr \|= ((RX_OFFSET / 2) << EMCR_RXOFF_SHIFT) \| EMCR_TXDMAEN \|
1019		- EMCR_TXEN \| EMCR_RXDMAEN \| EMCR_RXEN \| EMCR_PADEN;
1020		- ioc3_w_emcr(ip->emcr);
1021		- ioc3_w_eier(EISR_RXTIMERINT \| EISR_RXOFLO \| EISR_RXBUFOFLO \|
1022		- EISR_RXMEMERR \| EISR_RXPARERR \| EISR_TXBUFUFLO \|
1023		- EISR_TXEXPLICIT \| EISR_TXMEMERR);
1024		- (void) ioc3_r_eier();
	764	+ EMCR_TXEN \| EMCR_RXDMAEN \| EMCR_RXEN \| EMCR_PADEN;
	765	+ writel(ip->emcr, &regs->emcr);
	766	+ writel(EISR_RXTIMERINT \| EISR_RXOFLO \| EISR_RXBUFOFLO \|
	767	+ EISR_RXMEMERR \| EISR_RXPARERR \| EISR_TXBUFUFLO \|
	768	+ EISR_TXEXPLICIT \| EISR_TXMEMERR, &regs->eier);
	769	+ readl(&regs->eier);
1025	770	}
1026	771
1027	772	static inline void ioc3_stop(struct ioc3_private *ip)
1028	773	{
1029		- struct ioc3 *ioc3 = ip->regs;
	774	+ struct ioc3_ethregs *regs = ip->regs;
1030	775
1031		- ioc3_w_emcr(0); /* Shutup */
1032		- ioc3_w_eier(0); /* Disable interrupts */
1033		- (void) ioc3_r_eier(); /* Flush */
	776	+ writel(0, &regs->emcr); /* Shutup */
	777	+ writel(0, &regs->eier); /* Disable interrupts */
	778	+ readl(&regs->eier); /* Flush */
1034	779	}
1035	780
1036	781	static int ioc3_open(struct net_device *dev)
1037	782	{
1038	783	struct ioc3_private *ip = netdev_priv(dev);
1039	784
1040		- if (request_irq(dev->irq, ioc3_interrupt, IRQF_SHARED, ioc3_str, dev)) {
1041		- printk(KERN_ERR "%s: Can't get irq %d\n", dev->name, dev->irq);
1042		-
1043		- return -EAGAIN;
1044		- }
1045		-
1046	785	ip->ehar_h = 0;
1047	786	ip->ehar_l = 0;
	787	+
1048	788	ioc3_init(dev);
	789	+ if (ioc3_alloc_rx_bufs(dev)) {
	790	+ netdev_err(dev, "%s: rx buffer allocation failed\n", __func__);
	791	+ return -ENOMEM;
	792	+ }
	793	+ ioc3_start(ip);
1049	794	ioc3_mii_start(ip);
1050	795
1051	796	netif_start_queue(dev);
..	..	@@ -1061,152 +806,12 @@
1061	806	netif_stop_queue(dev);
1062	807
1063	808	ioc3_stop(ip);
1064		- free_irq(dev->irq, dev);
1065	809
1066		- ioc3_free_rings(ip);
	810	+ ioc3_free_rx_bufs(ip);
	811	+ ioc3_clean_tx_ring(ip);
	812	+
1067	813	return 0;
1068	814	}
1069		-
1070		-/*
1071		- * MENET cards have four IOC3 chips, which are attached to two sets of
1072		- * PCI slot resources each: the primary connections are on slots
1073		- * 0..3 and the secondaries are on 4..7
1074		- *
1075		- * All four ethernets are brought out to connectors; six serial ports
1076		- * (a pair from each of the first three IOC3s) are brought out to
1077		- * MiniDINs; all other subdevices are left swinging in the wind, leave
1078		- * them disabled.
1079		- */
1080		-
1081		-static int ioc3_adjacent_is_ioc3(struct pci_dev *pdev, int slot)
1082		-{
1083		- struct pci_dev *dev = pci_get_slot(pdev->bus, PCI_DEVFN(slot, 0));
1084		- int ret = 0;
1085		-
1086		- if (dev) {
1087		- if (dev->vendor == PCI_VENDOR_ID_SGI &&
1088		- dev->device == PCI_DEVICE_ID_SGI_IOC3)
1089		- ret = 1;
1090		- pci_dev_put(dev);
1091		- }
1092		-
1093		- return ret;
1094		-}
1095		-
1096		-static int ioc3_is_menet(struct pci_dev *pdev)
1097		-{
1098		- return pdev->bus->parent == NULL &&
1099		- ioc3_adjacent_is_ioc3(pdev, 0) &&
1100		- ioc3_adjacent_is_ioc3(pdev, 1) &&
1101		- ioc3_adjacent_is_ioc3(pdev, 2);
1102		-}
1103		-
1104		-#ifdef CONFIG_SERIAL_8250
1105		-/*
1106		- * Note about serial ports and consoles:
1107		- * For console output, everyone uses the IOC3 UARTA (offset 0x178)
1108		- * connected to the master node (look in ip27_setup_console() and
1109		- * ip27prom_console_write()).
1110		- *
1111		- * For serial (/dev/ttyS0 etc), we can not have hardcoded serial port
1112		- * addresses on a partitioned machine. Since we currently use the ioc3
1113		- * serial ports, we use dynamic serial port discovery that the serial.c
1114		- * driver uses for pci/pnp ports (there is an entry for the SGI ioc3
1115		- * boards in pci_boards[]). Unfortunately, UARTA's pio address is greater
1116		- * than UARTB's, although UARTA on o200s has traditionally been known as
1117		- * port 0. So, we just use one serial port from each ioc3 (since the
1118		- * serial driver adds addresses to get to higher ports).
1119		- *
1120		- * The first one to do a register_console becomes the preferred console
1121		- * (if there is no kernel command line console= directive). /dev/console
1122		- * (ie 5, 1) is then "aliased" into the device number returned by the
1123		- * "device" routine referred to in this console structure
1124		- * (ip27prom_console_dev).
1125		- *
1126		- * Also look in ip27-pci.c:pci_fixup_ioc3() for some comments on working
1127		- * around ioc3 oddities in this respect.
1128		- *
1129		- * The IOC3 serials use a 22MHz clock rate with an additional divider which
1130		- * can be programmed in the SCR register if the DLAB bit is set.
1131		- *
1132		- * Register to interrupt zero because we share the interrupt with
1133		- * the serial driver which we don't properly support yet.
1134		- *
1135		- * Can't use UPF_IOREMAP as the whole of IOC3 resources have already been
1136		- * registered.
1137		- */
1138		-static void ioc3_8250_register(struct ioc3_uartregs __iomem *uart)
1139		-{
1140		-#define COSMISC_CONSTANT 6
1141		-
1142		- struct uart_8250_port port = {
1143		- .port = {
1144		- .irq = 0,
1145		- .flags = UPF_SKIP_TEST \| UPF_BOOT_AUTOCONF,
1146		- .iotype = UPIO_MEM,
1147		- .regshift = 0,
1148		- .uartclk = (22000000 << 1) / COSMISC_CONSTANT,
1149		-
1150		- .membase = (unsigned char __iomem *) uart,
1151		- .mapbase = (unsigned long) uart,
1152		- }
1153		- };
1154		- unsigned char lcr;
1155		-
1156		- lcr = uart->iu_lcr;
1157		- uart->iu_lcr = lcr \| UART_LCR_DLAB;
1158		- uart->iu_scr = COSMISC_CONSTANT,
1159		- uart->iu_lcr = lcr;
1160		- uart->iu_lcr;
1161		- serial8250_register_8250_port(&port);
1162		-}
1163		-
1164		-static void ioc3_serial_probe(struct pci_dev pdev, struct ioc3 ioc3)
1165		-{
1166		- /*
1167		- * We need to recognice and treat the fourth MENET serial as it
1168		- * does not have an SuperIO chip attached to it, therefore attempting
1169		- * to access it will result in bus errors. We call something an
1170		- * MENET if PCI slot 0, 1, 2 and 3 of a master PCI bus all have an IOC3
1171		- * in it. This is paranoid but we want to avoid blowing up on a
1172		- * showhorn PCI box that happens to have 4 IOC3 cards in it so it's
1173		- * not paranoid enough ...
1174		- */
1175		- if (ioc3_is_menet(pdev) && PCI_SLOT(pdev->devfn) == 3)
1176		- return;
1177		-
1178		- /*
1179		- * Switch IOC3 to PIO mode. It probably already was but let's be
1180		- * paranoid
1181		- */
1182		- ioc3->gpcr_s = GPCR_UARTA_MODESEL \| GPCR_UARTB_MODESEL;
1183		- ioc3->gpcr_s;
1184		- ioc3->gppr_6 = 0;
1185		- ioc3->gppr_6;
1186		- ioc3->gppr_7 = 0;
1187		- ioc3->gppr_7;
1188		- ioc3->sscr_a = ioc3->sscr_a & ~SSCR_DMA_EN;
1189		- ioc3->sscr_a;
1190		- ioc3->sscr_b = ioc3->sscr_b & ~SSCR_DMA_EN;
1191		- ioc3->sscr_b;
1192		- /* Disable all SA/B interrupts except for SA/B_INT in SIO_IEC. */
1193		- ioc3->sio_iec &= ~ (SIO_IR_SA_TX_MT \| SIO_IR_SA_RX_FULL \|
1194		- SIO_IR_SA_RX_HIGH \| SIO_IR_SA_RX_TIMER \|
1195		- SIO_IR_SA_DELTA_DCD \| SIO_IR_SA_DELTA_CTS \|
1196		- SIO_IR_SA_TX_EXPLICIT \| SIO_IR_SA_MEMERR);
1197		- ioc3->sio_iec \|= SIO_IR_SA_INT;
1198		- ioc3->sscr_a = 0;
1199		- ioc3->sio_iec &= ~ (SIO_IR_SB_TX_MT \| SIO_IR_SB_RX_FULL \|
1200		- SIO_IR_SB_RX_HIGH \| SIO_IR_SB_RX_TIMER \|
1201		- SIO_IR_SB_DELTA_DCD \| SIO_IR_SB_DELTA_CTS \|
1202		- SIO_IR_SB_TX_EXPLICIT \| SIO_IR_SB_MEMERR);
1203		- ioc3->sio_iec \|= SIO_IR_SB_INT;
1204		- ioc3->sscr_b = 0;
1205		-
1206		- ioc3_8250_register(&ioc3->sregs.uarta);
1207		- ioc3_8250_register(&ioc3->sregs.uartb);
1208		-}
1209		-#endif
1210	815
1211	816	static const struct net_device_ops ioc3_netdev_ops = {
1212	817	.ndo_open = ioc3_open,
..	..	@@ -1220,81 +825,84 @@
1220	825	.ndo_set_mac_address = ioc3_set_mac_address,
1221	826	};
1222	827
1223		-static int ioc3_probe(struct pci_dev pdev, const struct pci_device_id ent)
	828	+static int ioc3eth_probe(struct platform_device *pdev)
1224	829	{
1225		- unsigned int sw_physid1, sw_physid2;
1226		- struct net_device *dev = NULL;
	830	+ u32 sw_physid1, sw_physid2, vendor, model, rev;
1227	831	struct ioc3_private *ip;
1228		- struct ioc3 *ioc3;
1229		- unsigned long ioc3_base, ioc3_size;
1230		- u32 vendor, model, rev;
1231		- int err, pci_using_dac;
	832	+ struct net_device *dev;
	833	+ struct resource *regs;
	834	+ u8 mac_addr[6];
	835	+ int err;
1232	836
1233		- /* Configure DMA attributes. */
1234		- err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1235		- if (!err) {
1236		- pci_using_dac = 1;
1237		- err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1238		- if (err < 0) {
1239		- printk(KERN_ERR "%s: Unable to obtain 64 bit DMA "
1240		- "for consistent allocations\n", pci_name(pdev));
1241		- goto out;
1242		- }
1243		- } else {
1244		- err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1245		- if (err) {
1246		- printk(KERN_ERR "%s: No usable DMA configuration, "
1247		- "aborting.\n", pci_name(pdev));
1248		- goto out;
1249		- }
1250		- pci_using_dac = 0;
	837	+ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	838	+ if (!regs) {
	839	+ dev_err(&pdev->dev, "Invalid resource\n");
	840	+ return -EINVAL;
1251	841	}
1252		-
1253		- if (pci_enable_device(pdev))
1254		- return -ENODEV;
	842	+ /* get mac addr from one wire prom */
	843	+ if (ioc3eth_get_mac_addr(regs, mac_addr))
	844	+ return -EPROBE_DEFER; /* not available yet */
1255	845
1256	846	dev = alloc_etherdev(sizeof(struct ioc3_private));
1257		- if (!dev) {
1258		- err = -ENOMEM;
1259		- goto out_disable;
1260		- }
1261		-
1262		- if (pci_using_dac)
1263		- dev->features \|= NETIF_F_HIGHDMA;
1264		-
1265		- err = pci_request_regions(pdev, "ioc3");
1266		- if (err)
1267		- goto out_free;
	847	+ if (!dev)
	848	+ return -ENOMEM;
1268	849
1269	850	SET_NETDEV_DEV(dev, &pdev->dev);
1270	851
1271	852	ip = netdev_priv(dev);
1272		- ip->dev = dev;
1273		-
1274		- dev->irq = pdev->irq;
1275		-
1276		- ioc3_base = pci_resource_start(pdev, 0);
1277		- ioc3_size = pci_resource_len(pdev, 0);
1278		- ioc3 = (struct ioc3 *) ioremap(ioc3_base, ioc3_size);
1279		- if (!ioc3) {
1280		- printk(KERN_CRIT "ioc3eth(%s): ioremap failed, goodbye.\n",
1281		- pci_name(pdev));
1282		- err = -ENOMEM;
1283		- goto out_res;
	853	+ ip->dma_dev = pdev->dev.parent;
	854	+ ip->regs = devm_platform_ioremap_resource(pdev, 0);
	855	+ if (IS_ERR(ip->regs)) {
	856	+ err = PTR_ERR(ip->regs);
	857	+ goto out_free;
1284	858	}
1285		- ip->regs = ioc3;
1286	859
1287		-#ifdef CONFIG_SERIAL_8250
1288		- ioc3_serial_probe(pdev, ioc3);
1289		-#endif
	860	+ ip->ssram = devm_platform_ioremap_resource(pdev, 1);
	861	+ if (IS_ERR(ip->ssram)) {
	862	+ err = PTR_ERR(ip->ssram);
	863	+ goto out_free;
	864	+ }
	865	+
	866	+ dev->irq = platform_get_irq(pdev, 0);
	867	+ if (dev->irq < 0) {
	868	+ err = dev->irq;
	869	+ goto out_free;
	870	+ }
	871	+
	872	+ if (devm_request_irq(&pdev->dev, dev->irq, ioc3_interrupt,
	873	+ IRQF_SHARED, "ioc3-eth", dev)) {
	874	+ dev_err(&pdev->dev, "Can't get irq %d\n", dev->irq);
	875	+ err = -ENODEV;
	876	+ goto out_free;
	877	+ }
1290	878
1291	879	spin_lock_init(&ip->ioc3_lock);
1292	880	timer_setup(&ip->ioc3_timer, ioc3_timer, 0);
1293	881
1294	882	ioc3_stop(ip);
1295		- ioc3_init(dev);
1296	883
1297		- ip->pdev = pdev;
	884	+ /* Allocate rx ring. 4kb = 512 entries, must be 4kb aligned */
	885	+ ip->rxr = dma_alloc_coherent(ip->dma_dev, RX_RING_SIZE, &ip->rxr_dma,
	886	+ GFP_KERNEL);
	887	+ if (!ip->rxr) {
	888	+ pr_err("ioc3-eth: rx ring allocation failed\n");
	889	+ err = -ENOMEM;
	890	+ goto out_stop;
	891	+ }
	892	+
	893	+ /* Allocate tx rings. 16kb = 128 bufs, must be 16kb aligned */
	894	+ ip->tx_ring = dma_alloc_coherent(ip->dma_dev, TX_RING_SIZE + SZ_16K - 1,
	895	+ &ip->txr_dma, GFP_KERNEL);
	896	+ if (!ip->tx_ring) {
	897	+ pr_err("ioc3-eth: tx ring allocation failed\n");
	898	+ err = -ENOMEM;
	899	+ goto out_stop;
	900	+ }
	901	+ /* Align TX ring */
	902	+ ip->txr = PTR_ALIGN(ip->tx_ring, SZ_16K);
	903	+ ip->txr_dma = ALIGN(ip->txr_dma, SZ_16K);
	904	+
	905	+ ioc3_init(dev);
1298	906
1299	907	ip->mii.phy_id_mask = 0x1f;
1300	908	ip->mii.reg_num_mask = 0x1f;
..	..	@@ -1305,22 +913,21 @@
1305	913	ioc3_mii_init(ip);
1306	914
1307	915	if (ip->mii.phy_id == -1) {
1308		- printk(KERN_CRIT "ioc3-eth(%s): Didn't find a PHY, goodbye.\n",
1309		- pci_name(pdev));
	916	+ netdev_err(dev, "Didn't find a PHY, goodbye.\n");
1310	917	err = -ENODEV;
1311	918	goto out_stop;
1312	919	}
1313	920
1314	921	ioc3_mii_start(ip);
1315	922	ioc3_ssram_disc(ip);
1316		- ioc3_get_eaddr(ip);
	923	+ memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
1317	924
1318	925	/* The IOC3-specific entries in the device structure. */
1319	926	dev->watchdog_timeo = 5 * HZ;
1320	927	dev->netdev_ops = &ioc3_netdev_ops;
1321	928	dev->ethtool_ops = &ioc3_ethtool_ops;
1322	929	dev->hw_features = NETIF_F_IP_CSUM \| NETIF_F_RXCSUM;
1323		- dev->features = NETIF_F_IP_CSUM;
	930	+ dev->features = NETIF_F_IP_CSUM \| NETIF_F_HIGHDMA;
1324	931
1325	932	sw_physid1 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID1);
1326	933	sw_physid2 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID2);
..	..	@@ -1335,73 +942,52 @@
1335	942	vendor = (sw_physid1 << 12) \| (sw_physid2 >> 4);
1336	943	model = (sw_physid2 >> 4) & 0x3f;
1337	944	rev = sw_physid2 & 0xf;
1338		- printk(KERN_INFO "%s: Using PHY %d, vendor 0x%x, model %d, "
1339		- "rev %d.\n", dev->name, ip->mii.phy_id, vendor, model, rev);
1340		- printk(KERN_INFO "%s: IOC3 SSRAM has %d kbyte.\n", dev->name,
1341		- ip->emcr & EMCR_BUFSIZ ? 128 : 64);
	945	+ netdev_info(dev, "Using PHY %d, vendor 0x%x, model %d, rev %d.\n",
	946	+ ip->mii.phy_id, vendor, model, rev);
	947	+ netdev_info(dev, "IOC3 SSRAM has %d kbyte.\n",
	948	+ ip->emcr & EMCR_BUFSIZ ? 128 : 64);
1342	949
1343	950	return 0;
1344	951
1345	952	out_stop:
1346		- ioc3_stop(ip);
1347	953	del_timer_sync(&ip->ioc3_timer);
1348		- ioc3_free_rings(ip);
1349		-out_res:
1350		- pci_release_regions(pdev);
	954	+ if (ip->rxr)
	955	+ dma_free_coherent(ip->dma_dev, RX_RING_SIZE, ip->rxr,
	956	+ ip->rxr_dma);
	957	+ if (ip->tx_ring)
	958	+ dma_free_coherent(ip->dma_dev, TX_RING_SIZE + SZ_16K - 1, ip->tx_ring,
	959	+ ip->txr_dma);
1351	960	out_free:
1352	961	free_netdev(dev);
1353		-out_disable:
1354		- /*
1355		- * We should call pci_disable_device(pdev); here if the IOC3 wasn't
1356		- * such a weird device ...
1357		- */
1358		-out:
1359	962	return err;
1360	963	}
1361	964
1362		-static void ioc3_remove_one(struct pci_dev *pdev)
	965	+static int ioc3eth_remove(struct platform_device *pdev)
1363	966	{
1364		- struct net_device *dev = pci_get_drvdata(pdev);
	967	+ struct net_device *dev = platform_get_drvdata(pdev);
1365	968	struct ioc3_private *ip = netdev_priv(dev);
1366		- struct ioc3 *ioc3 = ip->regs;
	969	+
	970	+ dma_free_coherent(ip->dma_dev, RX_RING_SIZE, ip->rxr, ip->rxr_dma);
	971	+ dma_free_coherent(ip->dma_dev, TX_RING_SIZE + SZ_16K - 1, ip->tx_ring, ip->txr_dma);
1367	972
1368	973	unregister_netdev(dev);
1369	974	del_timer_sync(&ip->ioc3_timer);
1370		-
1371		- iounmap(ioc3);
1372		- pci_release_regions(pdev);
1373	975	free_netdev(dev);
1374		- /*
1375		- * We should call pci_disable_device(pdev); here if the IOC3 wasn't
1376		- * such a weird device ...
1377		- */
	976	+
	977	+ return 0;
1378	978	}
1379	979
1380		-static const struct pci_device_id ioc3_pci_tbl[] = {
1381		- { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, PCI_ANY_ID, PCI_ANY_ID },
1382		- { 0 }
1383		-};
1384		-MODULE_DEVICE_TABLE(pci, ioc3_pci_tbl);
1385		-
1386		-static struct pci_driver ioc3_driver = {
1387		- .name = "ioc3-eth",
1388		- .id_table = ioc3_pci_tbl,
1389		- .probe = ioc3_probe,
1390		- .remove = ioc3_remove_one,
1391		-};
1392	980
1393	981	static netdev_tx_t ioc3_start_xmit(struct sk_buff skb, struct net_device dev)
1394	982	{
1395		- unsigned long data;
1396	983	struct ioc3_private *ip = netdev_priv(dev);
1397		- struct ioc3 *ioc3 = ip->regs;
1398		- unsigned int len;
1399	984	struct ioc3_etxd *desc;
1400		- uint32_t w0 = 0;
	985	+ unsigned long data;
	986	+ unsigned int len;
1401	987	int produce;
	988	+ u32 w0 = 0;
1402	989
1403		- /*
1404		- * IOC3 has a fairly simple minded checksumming hardware which simply
	990	+ /* IOC3 has a fairly simple minded checksumming hardware which simply
1405	991	* adds up the 1's complement checksum for the entire packet and
1406	992	* inserts it at an offset which can be specified in the descriptor
1407	993	* into the transmit packet. This means we have to compensate for the
..	..	@@ -1412,25 +998,23 @@
1412	998	const struct iphdr *ih = ip_hdr(skb);
1413	999	const int proto = ntohs(ih->protocol);
1414	1000	unsigned int csoff;
1415		- uint32_t csum, ehsum;
1416		- uint16_t *eh;
	1001	+ u32 csum, ehsum;
	1002	+ u16 *eh;
1417	1003
1418	1004	/* The MAC header. skb->mac seem the logic approach
1419		- to find the MAC header - except it's a NULL pointer ... */
1420		- eh = (uint16_t *) skb->data;
	1005	+ * to find the MAC header - except it's a NULL pointer ...
	1006	+ */
	1007	+ eh = (u16 *)skb->data;
1421	1008
1422	1009	/* Sum up dest addr, src addr and protocol */
1423	1010	ehsum = eh[0] + eh[1] + eh[2] + eh[3] + eh[4] + eh[5] + eh[6];
1424	1011
1425		- /* Fold ehsum. can't use csum_fold which negates also ... */
1426		- ehsum = (ehsum & 0xffff) + (ehsum >> 16);
1427		- ehsum = (ehsum & 0xffff) + (ehsum >> 16);
1428		-
1429	1012	/* Skip IP header; it's sum is always zero and was
1430		- already filled in by ip_output.c */
	1013	+ * already filled in by ip_output.c
	1014	+ */
1431	1015	csum = csum_tcpudp_nofold(ih->saddr, ih->daddr,
1432		- ih->tot_len - (ih->ihl << 2),
1433		- proto, 0xffff ^ ehsum);
	1016	+ ih->tot_len - (ih->ihl << 2),
	1017	+ proto, csum_fold(ehsum));
1434	1018
1435	1019	csum = (csum & 0xffff) + (csum >> 16); /* Fold again */
1436	1020	csum = (csum & 0xffff) + (csum >> 16);
..	..	@@ -1450,7 +1034,7 @@
1450	1034
1451	1035	spin_lock_irq(&ip->ioc3_lock);
1452	1036
1453		- data = (unsigned long) skb->data;
	1037	+ data = (unsigned long)skb->data;
1454	1038	len = skb->len;
1455	1039
1456	1040	produce = ip->tx_pi;
..	..	@@ -1470,47 +1054,78 @@
1470	1054	unsigned long b2 = (data \| 0x3fffUL) + 1UL;
1471	1055	unsigned long s1 = b2 - data;
1472	1056	unsigned long s2 = data + len - b2;
	1057	+ dma_addr_t d1, d2;
1473	1058
1474	1059	desc->cmd = cpu_to_be32(len \| ETXD_INTWHENDONE \|
1475		- ETXD_B1V \| ETXD_B2V \| w0);
	1060	+ ETXD_B1V \| ETXD_B2V \| w0);
1476	1061	desc->bufcnt = cpu_to_be32((s1 << ETXD_B1CNT_SHIFT) \|
1477		- (s2 << ETXD_B2CNT_SHIFT));
1478		- desc->p1 = cpu_to_be64(ioc3_map(skb->data, 1));
1479		- desc->p2 = cpu_to_be64(ioc3_map((void *) b2, 1));
	1062	+ (s2 << ETXD_B2CNT_SHIFT));
	1063	+ d1 = dma_map_single(ip->dma_dev, skb->data, s1, DMA_TO_DEVICE);
	1064	+ if (dma_mapping_error(ip->dma_dev, d1))
	1065	+ goto drop_packet;
	1066	+ d2 = dma_map_single(ip->dma_dev, (void *)b2, s1, DMA_TO_DEVICE);
	1067	+ if (dma_mapping_error(ip->dma_dev, d2)) {
	1068	+ dma_unmap_single(ip->dma_dev, d1, len, DMA_TO_DEVICE);
	1069	+ goto drop_packet;
	1070	+ }
	1071	+ desc->p1 = cpu_to_be64(ioc3_map(d1, PCI64_ATTR_PREF));
	1072	+ desc->p2 = cpu_to_be64(ioc3_map(d2, PCI64_ATTR_PREF));
1480	1073	} else {
	1074	+ dma_addr_t d;
	1075	+
1481	1076	/* Normal sized packet that doesn't cross a page boundary. */
1482	1077	desc->cmd = cpu_to_be32(len \| ETXD_INTWHENDONE \| ETXD_B1V \| w0);
1483	1078	desc->bufcnt = cpu_to_be32(len << ETXD_B1CNT_SHIFT);
1484		- desc->p1 = cpu_to_be64(ioc3_map(skb->data, 1));
	1079	+ d = dma_map_single(ip->dma_dev, skb->data, len, DMA_TO_DEVICE);
	1080	+ if (dma_mapping_error(ip->dma_dev, d))
	1081	+ goto drop_packet;
	1082	+ desc->p1 = cpu_to_be64(ioc3_map(d, PCI64_ATTR_PREF));
1485	1083	}
1486	1084
1487		- BARRIER();
	1085	+ mb(); /* make sure all descriptor changes are visible */
1488	1086
1489	1087	ip->tx_skbs[produce] = skb; /* Remember skb */
1490		- produce = (produce + 1) & 127;
	1088	+ produce = (produce + 1) & TX_RING_MASK;
1491	1089	ip->tx_pi = produce;
1492		- ioc3_w_etpir(produce << 7); /* Fire ... */
	1090	+ writel(produce << 7, &ip->regs->etpir); /* Fire ... */
1493	1091
1494	1092	ip->txqlen++;
1495	1093
1496		- if (ip->txqlen >= 127)
	1094	+ if (ip->txqlen >= (TX_RING_ENTRIES - 1))
1497	1095	netif_stop_queue(dev);
	1096	+
	1097	+ spin_unlock_irq(&ip->ioc3_lock);
	1098	+
	1099	+ return NETDEV_TX_OK;
	1100	+
	1101	+drop_packet:
	1102	+ dev_kfree_skb_any(skb);
	1103	+ dev->stats.tx_dropped++;
1498	1104
1499	1105	spin_unlock_irq(&ip->ioc3_lock);
1500	1106
1501	1107	return NETDEV_TX_OK;
1502	1108	}
1503	1109
1504		-static void ioc3_timeout(struct net_device *dev)
	1110	+static void ioc3_timeout(struct net_device *dev, unsigned int txqueue)
1505	1111	{
1506	1112	struct ioc3_private *ip = netdev_priv(dev);
1507	1113
1508		- printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
	1114	+ netdev_err(dev, "transmit timed out, resetting\n");
1509	1115
1510	1116	spin_lock_irq(&ip->ioc3_lock);
1511	1117
1512	1118	ioc3_stop(ip);
	1119	+ ioc3_free_rx_bufs(ip);
	1120	+ ioc3_clean_tx_ring(ip);
	1121	+
1513	1122	ioc3_init(dev);
	1123	+ if (ioc3_alloc_rx_bufs(dev)) {
	1124	+ netdev_err(dev, "%s: rx buffer allocation failed\n", __func__);
	1125	+ spin_unlock_irq(&ip->ioc3_lock);
	1126	+ return;
	1127	+ }
	1128	+ ioc3_start(ip);
1514	1129	ioc3_mii_init(ip);
1515	1130	ioc3_mii_start(ip);
1516	1131
..	..	@@ -1519,16 +1134,14 @@
1519	1134	netif_wake_queue(dev);
1520	1135	}
1521	1136
1522		-/*
1523		- * Given a multicast ethernet address, this routine calculates the
	1137	+/* Given a multicast ethernet address, this routine calculates the
1524	1138	* address's bit index in the logical address filter mask
1525	1139	*/
1526		-
1527	1140	static inline unsigned int ioc3_hash(const unsigned char *addr)
1528	1141	{
1529	1142	unsigned int temp = 0;
1530		- u32 crc;
1531	1143	int bits;
	1144	+ u32 crc;
1532	1145
1533	1146	crc = ether_crc_le(ETH_ALEN, addr);
1534	1147
..	..	@@ -1542,14 +1155,13 @@
1542	1155	return temp;
1543	1156	}
1544	1157
1545		-static void ioc3_get_drvinfo (struct net_device *dev,
1546		- struct ethtool_drvinfo *info)
	1158	+static void ioc3_get_drvinfo(struct net_device *dev,
	1159	+ struct ethtool_drvinfo *info)
1547	1160	{
1548		- struct ioc3_private *ip = netdev_priv(dev);
1549		-
1550	1161	strlcpy(info->driver, IOC3_NAME, sizeof(info->driver));
1551	1162	strlcpy(info->version, IOC3_VERSION, sizeof(info->version));
1552		- strlcpy(info->bus_info, pci_name(ip->pdev), sizeof(info->bus_info));
	1163	+ strlcpy(info->bus_info, pci_name(to_pci_dev(dev->dev.parent)),
	1164	+ sizeof(info->bus_info));
1553	1165	}
1554	1166
1555	1167	static int ioc3_get_link_ksettings(struct net_device *dev,
..	..	@@ -1623,27 +1235,28 @@
1623	1235
1624	1236	static void ioc3_set_multicast_list(struct net_device *dev)
1625	1237	{
1626		- struct netdev_hw_addr *ha;
1627	1238	struct ioc3_private *ip = netdev_priv(dev);
1628		- struct ioc3 *ioc3 = ip->regs;
	1239	+ struct ioc3_ethregs *regs = ip->regs;
	1240	+ struct netdev_hw_addr *ha;
1629	1241	u64 ehar = 0;
1630	1242
1631		- netif_stop_queue(dev); /* Lock out others. */
	1243	+ spin_lock_irq(&ip->ioc3_lock);
1632	1244
1633	1245	if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1634	1246	ip->emcr \|= EMCR_PROMISC;
1635		- ioc3_w_emcr(ip->emcr);
1636		- (void) ioc3_r_emcr();
	1247	+ writel(ip->emcr, &regs->emcr);
	1248	+ readl(&regs->emcr);
1637	1249	} else {
1638	1250	ip->emcr &= ~EMCR_PROMISC;
1639		- ioc3_w_emcr(ip->emcr); /* Clear promiscuous. */
1640		- (void) ioc3_r_emcr();
	1251	+ writel(ip->emcr, &regs->emcr); /* Clear promiscuous. */
	1252	+ readl(&regs->emcr);
1641	1253
1642	1254	if ((dev->flags & IFF_ALLMULTI) \|\|
1643	1255	(netdev_mc_count(dev) > 64)) {
1644	1256	/* Too many for hashing to make sense or we want all
1645		- multicast packets anyway, so skip computing all the
1646		- hashes and just accept all packets. */
	1257	+ * multicast packets anyway, so skip computing all the
	1258	+ * hashes and just accept all packets.
	1259	+ */
1647	1260	ip->ehar_h = 0xffffffff;
1648	1261	ip->ehar_l = 0xffffffff;
1649	1262	} else {
..	..	@@ -1653,14 +1266,23 @@
1653	1266	ip->ehar_h = ehar >> 32;
1654	1267	ip->ehar_l = ehar & 0xffffffff;
1655	1268	}
1656		- ioc3_w_ehar_h(ip->ehar_h);
1657		- ioc3_w_ehar_l(ip->ehar_l);
	1269	+ writel(ip->ehar_h, &regs->ehar_h);
	1270	+ writel(ip->ehar_l, &regs->ehar_l);
1658	1271	}
1659	1272
1660		- netif_wake_queue(dev); /* Let us get going again. */
	1273	+ spin_unlock_irq(&ip->ioc3_lock);
1661	1274	}
1662	1275
1663		-module_pci_driver(ioc3_driver);
	1276	+static struct platform_driver ioc3eth_driver = {
	1277	+ .probe = ioc3eth_probe,
	1278	+ .remove = ioc3eth_remove,
	1279	+ .driver = {
	1280	+ .name = "ioc3-eth",
	1281	+ }
	1282	+};
	1283	+
	1284	+module_platform_driver(ioc3eth_driver);
	1285	+
1664	1286	MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
1665	1287	MODULE_DESCRIPTION("SGI IOC3 Ethernet driver");
1666	1288	MODULE_LICENSE("GPL");