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2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da 
 kernel/drivers/net/ethernet/sfc/mcdi_pcol.h
....@@ -1,10 +1,8 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /****************************************************************************
23  * Driver for Solarflare network controllers and boards
3
- * Copyright 2009-2013 Solarflare Communications Inc.
4
- *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms of the GNU General Public License version 2 as published
7
- * by the Free Software Foundation, incorporated herein by reference.
4
+ * Copyright 2009-2018 Solarflare Communications Inc.
5
+ * Copyright 2019-2020 Xilinx Inc.
86  */
97 
108 
....@@ -386,14 +384,19 @@
386384 #define          MCDI_EVENT_LEVEL_FATAL 0x3
387385 #define       MCDI_EVENT_DATA_OFST 0
388386 #define       MCDI_EVENT_DATA_LEN 4
387
+#define        MCDI_EVENT_CMDDONE_SEQ_OFST 0
389388 #define        MCDI_EVENT_CMDDONE_SEQ_LBN 0
390389 #define        MCDI_EVENT_CMDDONE_SEQ_WIDTH 8
390
+#define        MCDI_EVENT_CMDDONE_DATALEN_OFST 0
391391 #define        MCDI_EVENT_CMDDONE_DATALEN_LBN 8
392392 #define        MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8
393
+#define        MCDI_EVENT_CMDDONE_ERRNO_OFST 0
393394 #define        MCDI_EVENT_CMDDONE_ERRNO_LBN 16
394395 #define        MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8
396
+#define        MCDI_EVENT_LINKCHANGE_LP_CAP_OFST 0
395397 #define        MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0
396398 #define        MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16
399
+#define        MCDI_EVENT_LINKCHANGE_SPEED_OFST 0
397400 #define        MCDI_EVENT_LINKCHANGE_SPEED_LBN 16
398401 #define        MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4
399402 /* enum: Link is down or link speed could not be determined */
....@@ -412,26 +415,36 @@
412415 #define          MCDI_EVENT_LINKCHANGE_SPEED_50G 0x6
413416 /* enum: 100Gbs */
414417 #define          MCDI_EVENT_LINKCHANGE_SPEED_100G 0x7
418
+#define        MCDI_EVENT_LINKCHANGE_FCNTL_OFST 0
415419 #define        MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20
416420 #define        MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4
421
+#define        MCDI_EVENT_LINKCHANGE_LINK_FLAGS_OFST 0
417422 #define        MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24
418423 #define        MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8
424
+#define        MCDI_EVENT_SENSOREVT_MONITOR_OFST 0
419425 #define        MCDI_EVENT_SENSOREVT_MONITOR_LBN 0
420426 #define        MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8
427
+#define        MCDI_EVENT_SENSOREVT_STATE_OFST 0
421428 #define        MCDI_EVENT_SENSOREVT_STATE_LBN 8
422429 #define        MCDI_EVENT_SENSOREVT_STATE_WIDTH 8
430
+#define        MCDI_EVENT_SENSOREVT_VALUE_OFST 0
423431 #define        MCDI_EVENT_SENSOREVT_VALUE_LBN 16
424432 #define        MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16
433
+#define        MCDI_EVENT_FWALERT_DATA_OFST 0
425434 #define        MCDI_EVENT_FWALERT_DATA_LBN 8
426435 #define        MCDI_EVENT_FWALERT_DATA_WIDTH 24
436
+#define        MCDI_EVENT_FWALERT_REASON_OFST 0
427437 #define        MCDI_EVENT_FWALERT_REASON_LBN 0
428438 #define        MCDI_EVENT_FWALERT_REASON_WIDTH 8
429439 /* enum: SRAM Access. */
430440 #define          MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1
441
+#define        MCDI_EVENT_FLR_VF_OFST 0
431442 #define        MCDI_EVENT_FLR_VF_LBN 0
432443 #define        MCDI_EVENT_FLR_VF_WIDTH 8
444
+#define        MCDI_EVENT_TX_ERR_TXQ_OFST 0
433445 #define        MCDI_EVENT_TX_ERR_TXQ_LBN 0
434446 #define        MCDI_EVENT_TX_ERR_TXQ_WIDTH 12
447
+#define        MCDI_EVENT_TX_ERR_TYPE_OFST 0
435448 #define        MCDI_EVENT_TX_ERR_TYPE_LBN 12
436449 #define        MCDI_EVENT_TX_ERR_TYPE_WIDTH 4
437450 /* enum: Descriptor loader reported failure */
....@@ -446,12 +459,16 @@
446459 #define          MCDI_EVENT_TX_OPT_IN_PKT 0x8
447460 /* enum: DMA or PIO data access error */
448461 #define          MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9
462
+#define        MCDI_EVENT_TX_ERR_INFO_OFST 0
449463 #define        MCDI_EVENT_TX_ERR_INFO_LBN 16
450464 #define        MCDI_EVENT_TX_ERR_INFO_WIDTH 16
465
+#define        MCDI_EVENT_TX_FLUSH_TO_DRIVER_OFST 0
451466 #define        MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12
452467 #define        MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1
468
+#define        MCDI_EVENT_TX_FLUSH_TXQ_OFST 0
453469 #define        MCDI_EVENT_TX_FLUSH_TXQ_LBN 0
454470 #define        MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12
471
+#define        MCDI_EVENT_PTP_ERR_TYPE_OFST 0
455472 #define        MCDI_EVENT_PTP_ERR_TYPE_LBN 0
456473 #define        MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8
457474 /* enum: PLL lost lock */
....@@ -462,6 +479,7 @@
462479 #define          MCDI_EVENT_PTP_ERR_FIFO 0x3
463480 /* enum: Merge queue overflow */
464481 #define          MCDI_EVENT_PTP_ERR_QUEUE 0x4
482
+#define        MCDI_EVENT_AOE_ERR_TYPE_OFST 0
465483 #define        MCDI_EVENT_AOE_ERR_TYPE_LBN 0
466484 #define        MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8
467485 /* enum: AOE failed to load - no valid image? */
....@@ -508,8 +526,10 @@
508526 #define          MCDI_EVENT_AOE_FPGA_CLOCKS_PROGRAM_FAILED 0x13
509527 /* enum: Notify that FPGA Controller is alive to serve MCDI requests */
510528 #define          MCDI_EVENT_AOE_FC_RUNNING 0x14
529
+#define        MCDI_EVENT_AOE_ERR_DATA_OFST 0
511530 #define        MCDI_EVENT_AOE_ERR_DATA_LBN 8
512531 #define        MCDI_EVENT_AOE_ERR_DATA_WIDTH 8
532
+#define        MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_OFST 0
513533 #define        MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_LBN 8
514534 #define        MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_WIDTH 8
515535 /* enum: FC Assert happened, but the register information is not available */
....@@ -517,6 +537,7 @@
517537 /* enum: The register information for FC Assert is ready for readinng by driver
518538  */
519539 #define          MCDI_EVENT_AOE_ERR_FC_ASSERT_DATA_READY 0x1
540
+#define        MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_OFST 0
520541 #define        MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_LBN 8
521542 #define        MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_WIDTH 8
522543 /* enum: Reading from NV failed */
....@@ -537,28 +558,38 @@
537558 #define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SIZE 0x7
538559 /* enum: Unsupported DDR rank */
539560 #define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_RANK 0x8
561
+#define        MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_OFST 0
540562 #define        MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_LBN 8
541563 #define        MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_WIDTH 8
542564 /* enum: Primary boot flash */
543565 #define          MCDI_EVENT_AOE_FLASH_TYPE_BOOT_PRIMARY 0x0
544566 /* enum: Secondary boot flash */
545567 #define          MCDI_EVENT_AOE_FLASH_TYPE_BOOT_SECONDARY 0x1
568
+#define        MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_OFST 0
546569 #define        MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_LBN 8
547570 #define        MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_WIDTH 8
571
+#define        MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_OFST 0
548572 #define        MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_LBN 8
549573 #define        MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_WIDTH 8
574
+#define        MCDI_EVENT_RX_ERR_RXQ_OFST 0
550575 #define        MCDI_EVENT_RX_ERR_RXQ_LBN 0
551576 #define        MCDI_EVENT_RX_ERR_RXQ_WIDTH 12
577
+#define        MCDI_EVENT_RX_ERR_TYPE_OFST 0
552578 #define        MCDI_EVENT_RX_ERR_TYPE_LBN 12
553579 #define        MCDI_EVENT_RX_ERR_TYPE_WIDTH 4
580
+#define        MCDI_EVENT_RX_ERR_INFO_OFST 0
554581 #define        MCDI_EVENT_RX_ERR_INFO_LBN 16
555582 #define        MCDI_EVENT_RX_ERR_INFO_WIDTH 16
583
+#define        MCDI_EVENT_RX_FLUSH_TO_DRIVER_OFST 0
556584 #define        MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12
557585 #define        MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1
586
+#define        MCDI_EVENT_RX_FLUSH_RXQ_OFST 0
558587 #define        MCDI_EVENT_RX_FLUSH_RXQ_LBN 0
559588 #define        MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12
589
+#define        MCDI_EVENT_MC_REBOOT_COUNT_OFST 0
560590 #define        MCDI_EVENT_MC_REBOOT_COUNT_LBN 0
561591 #define        MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16
592
+#define        MCDI_EVENT_MUM_ERR_TYPE_OFST 0
562593 #define        MCDI_EVENT_MUM_ERR_TYPE_LBN 0
563594 #define        MCDI_EVENT_MUM_ERR_TYPE_WIDTH 8
564595 /* enum: MUM failed to load - no valid image? */
....@@ -567,10 +598,13 @@
567598 #define          MCDI_EVENT_MUM_ASSERT 0x2
568599 /* enum: MUM not kicking watchdog */
569600 #define          MCDI_EVENT_MUM_WATCHDOG 0x3
601
+#define        MCDI_EVENT_MUM_ERR_DATA_OFST 0
570602 #define        MCDI_EVENT_MUM_ERR_DATA_LBN 8
571603 #define        MCDI_EVENT_MUM_ERR_DATA_WIDTH 8
604
+#define        MCDI_EVENT_DBRET_SEQ_OFST 0
572605 #define        MCDI_EVENT_DBRET_SEQ_LBN 0
573606 #define        MCDI_EVENT_DBRET_SEQ_WIDTH 8
607
+#define        MCDI_EVENT_SUC_ERR_TYPE_OFST 0
574608 #define        MCDI_EVENT_SUC_ERR_TYPE_LBN 0
575609 #define        MCDI_EVENT_SUC_ERR_TYPE_WIDTH 8
576610 /* enum: Corrupted or bad SUC application. */
....@@ -581,14 +615,48 @@
581615 #define          MCDI_EVENT_SUC_EXCEPTION 0x3
582616 /* enum: SUC watchdog timer expired. */
583617 #define          MCDI_EVENT_SUC_WATCHDOG 0x4
618
+#define        MCDI_EVENT_SUC_ERR_ADDRESS_OFST 0
584619 #define        MCDI_EVENT_SUC_ERR_ADDRESS_LBN 8
585620 #define        MCDI_EVENT_SUC_ERR_ADDRESS_WIDTH 24
621
+#define        MCDI_EVENT_SUC_ERR_DATA_OFST 0
586622 #define        MCDI_EVENT_SUC_ERR_DATA_LBN 8
587623 #define        MCDI_EVENT_SUC_ERR_DATA_WIDTH 24
624
+#define        MCDI_EVENT_LINKCHANGE_V2_LP_CAP_OFST 0
625
+#define        MCDI_EVENT_LINKCHANGE_V2_LP_CAP_LBN 0
626
+#define        MCDI_EVENT_LINKCHANGE_V2_LP_CAP_WIDTH 24
627
+#define        MCDI_EVENT_LINKCHANGE_V2_SPEED_OFST 0
628
+#define        MCDI_EVENT_LINKCHANGE_V2_SPEED_LBN 24
629
+#define        MCDI_EVENT_LINKCHANGE_V2_SPEED_WIDTH 4
630
+/*             Enum values, see field(s): */
631
+/*                MCDI_EVENT/LINKCHANGE_SPEED */
632
+#define        MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_OFST 0
633
+#define        MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_LBN 28
634
+#define        MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_WIDTH 1
635
+#define        MCDI_EVENT_LINKCHANGE_V2_FCNTL_OFST 0
636
+#define        MCDI_EVENT_LINKCHANGE_V2_FCNTL_LBN 29
637
+#define        MCDI_EVENT_LINKCHANGE_V2_FCNTL_WIDTH 3
638
+/*             Enum values, see field(s): */
639
+/*                MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */
640
+#define        MCDI_EVENT_MODULECHANGE_LD_CAP_OFST 0
641
+#define        MCDI_EVENT_MODULECHANGE_LD_CAP_LBN 0
642
+#define        MCDI_EVENT_MODULECHANGE_LD_CAP_WIDTH 30
643
+#define        MCDI_EVENT_MODULECHANGE_SEQ_OFST 0
644
+#define        MCDI_EVENT_MODULECHANGE_SEQ_LBN 30
645
+#define        MCDI_EVENT_MODULECHANGE_SEQ_WIDTH 2
588646 #define       MCDI_EVENT_DATA_LBN 0
589647 #define       MCDI_EVENT_DATA_WIDTH 32
648
+/* Alias for PTP_DATA. */
590649 #define       MCDI_EVENT_SRC_LBN 36
591650 #define       MCDI_EVENT_SRC_WIDTH 8
651
+/* Data associated with PTP events which doesn't fit into the main DATA field
652
+ */
653
+#define       MCDI_EVENT_PTP_DATA_LBN 36
654
+#define       MCDI_EVENT_PTP_DATA_WIDTH 8
655
+/* EF100 specific. Defined by QDMA. The phase bit, changes each time round the
656
+ * event ring
657
+ */
658
+#define       MCDI_EVENT_EV_EVQ_PHASE_LBN 59
659
+#define       MCDI_EVENT_EV_EVQ_PHASE_WIDTH 1
592660 #define       MCDI_EVENT_EV_CODE_LBN 60
593661 #define       MCDI_EVENT_EV_CODE_WIDTH 4
594662 #define       MCDI_EVENT_CODE_LBN 44
....@@ -663,6 +731,48 @@
663731 #define          MCDI_EVENT_CODE_DBRET 0x1e
664732 /* enum: The MC has detected a fault on the SUC */
665733 #define          MCDI_EVENT_CODE_SUC 0x1f
734
+/* enum: Link change. This event is sent instead of LINKCHANGE if
735
+ * WANT_V2_LINKCHANGES was set on driver attach.
736
+ */
737
+#define          MCDI_EVENT_CODE_LINKCHANGE_V2 0x20
738
+/* enum: This event is sent if WANT_V2_LINKCHANGES was set on driver attach
739
+ * when the local device capabilities changes. This will usually correspond to
740
+ * a module change.
741
+ */
742
+#define          MCDI_EVENT_CODE_MODULECHANGE 0x21
743
+/* enum: Notification that the sensors have been added and/or removed from the
744
+ * sensor table. This event includes the new sensor table generation count, if
745
+ * this does not match the driver's local copy it is expected to call
746
+ * DYNAMIC_SENSORS_LIST to refresh it.
747
+ */
748
+#define          MCDI_EVENT_CODE_DYNAMIC_SENSORS_CHANGE 0x22
749
+/* enum: Notification that a sensor has changed state as a result of a reading
750
+ * crossing a threshold. This is sent as two events, the first event contains
751
+ * the handle and the sensor's state (in the SRC field), and the second
752
+ * contains the value.
753
+ */
754
+#define          MCDI_EVENT_CODE_DYNAMIC_SENSORS_STATE_CHANGE 0x23
755
+/* enum: Notification that a descriptor proxy function configuration has been
756
+ * pushed to "live" status (visible to host). SRC field contains the handle of
757
+ * the affected descriptor proxy function. DATA field contains the generation
758
+ * count of configuration set applied. See MC_CMD_DESC_PROXY_FUNC_CONFIG_SET /
759
+ * MC_CMD_DESC_PROXY_FUNC_CONFIG_COMMIT and SF-122927-TC for details.
760
+ */
761
+#define          MCDI_EVENT_CODE_DESC_PROXY_FUNC_CONFIG_COMMITTED 0x24
762
+/* enum: Notification that a descriptor proxy function has been reset. SRC
763
+ * field contains the handle of the affected descriptor proxy function. See
764
+ * SF-122927-TC for details.
765
+ */
766
+#define          MCDI_EVENT_CODE_DESC_PROXY_FUNC_RESET 0x25
767
+/* enum: Notification that a driver attached to a descriptor proxy function.
768
+ * SRC field contains the handle of the affected descriptor proxy function. For
769
+ * Virtio proxy functions this message consists of two MCDI events, where the
770
+ * first event's (CONT=1) DATA field carries negotiated virtio feature bits 0
771
+ * to 31 and the second (CONT=0) carries bits 32 to 63. For EF100 proxy
772
+ * functions event length and meaning of DATA field is not yet defined. See
773
+ * SF-122927-TC for details.
774
+ */
775
+#define          MCDI_EVENT_CODE_DESC_PROXY_FUNC_DRIVER_ATTACH 0x26
666776 /* enum: Artificial event generated by host and posted via MC for test
667777  * purposes.
668778  */
....@@ -788,6 +898,48 @@
788898 #define       MCDI_EVENT_DBRET_DATA_LEN 4
789899 #define       MCDI_EVENT_DBRET_DATA_LBN 0
790900 #define       MCDI_EVENT_DBRET_DATA_WIDTH 32
901
+#define       MCDI_EVENT_LINKCHANGE_V2_DATA_OFST 0
902
+#define       MCDI_EVENT_LINKCHANGE_V2_DATA_LEN 4
903
+#define       MCDI_EVENT_LINKCHANGE_V2_DATA_LBN 0
904
+#define       MCDI_EVENT_LINKCHANGE_V2_DATA_WIDTH 32
905
+#define       MCDI_EVENT_MODULECHANGE_DATA_OFST 0
906
+#define       MCDI_EVENT_MODULECHANGE_DATA_LEN 4
907
+#define       MCDI_EVENT_MODULECHANGE_DATA_LBN 0
908
+#define       MCDI_EVENT_MODULECHANGE_DATA_WIDTH 32
909
+/* The new generation count after a sensor has been added or deleted. */
910
+#define       MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_OFST 0
911
+#define       MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_LEN 4
912
+#define       MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_LBN 0
913
+#define       MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_WIDTH 32
914
+/* The handle of a dynamic sensor. */
915
+#define       MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_OFST 0
916
+#define       MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_LEN 4
917
+#define       MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_LBN 0
918
+#define       MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_WIDTH 32
919
+/* The current values of a sensor. */
920
+#define       MCDI_EVENT_DYNAMIC_SENSORS_VALUE_OFST 0
921
+#define       MCDI_EVENT_DYNAMIC_SENSORS_VALUE_LEN 4
922
+#define       MCDI_EVENT_DYNAMIC_SENSORS_VALUE_LBN 0
923
+#define       MCDI_EVENT_DYNAMIC_SENSORS_VALUE_WIDTH 32
924
+/* The current state of a sensor. */
925
+#define       MCDI_EVENT_DYNAMIC_SENSORS_STATE_LBN 36
926
+#define       MCDI_EVENT_DYNAMIC_SENSORS_STATE_WIDTH 8
927
+#define       MCDI_EVENT_DESC_PROXY_DATA_OFST 0
928
+#define       MCDI_EVENT_DESC_PROXY_DATA_LEN 4
929
+#define       MCDI_EVENT_DESC_PROXY_DATA_LBN 0
930
+#define       MCDI_EVENT_DESC_PROXY_DATA_WIDTH 32
931
+/* Generation count of applied configuration set */
932
+#define       MCDI_EVENT_DESC_PROXY_GENERATION_OFST 0
933
+#define       MCDI_EVENT_DESC_PROXY_GENERATION_LEN 4
934
+#define       MCDI_EVENT_DESC_PROXY_GENERATION_LBN 0
935
+#define       MCDI_EVENT_DESC_PROXY_GENERATION_WIDTH 32
936
+/* Virtio features negotiated with the host driver. First event (CONT=1)
937
+ * carries bits 0 to 31. Second event (CONT=0) carries bits 32 to 63.
938
+ */
939
+#define       MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_OFST 0
940
+#define       MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LEN 4
941
+#define       MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LBN 0
942
+#define       MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_WIDTH 32
791943 
792944 /* FCDI_EVENT structuredef */
793945 #define    FCDI_EVENT_LEN 8
....@@ -805,6 +957,7 @@
805957 #define          FCDI_EVENT_LEVEL_FATAL 0x3
806958 #define       FCDI_EVENT_DATA_OFST 0
807959 #define       FCDI_EVENT_DATA_LEN 4
960
+#define        FCDI_EVENT_LINK_STATE_STATUS_OFST 0
808961 #define        FCDI_EVENT_LINK_STATE_STATUS_LBN 0
809962 #define        FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1
810963 #define          FCDI_EVENT_LINK_DOWN 0x0 /* enum */
....@@ -895,7 +1048,9 @@
8951048  */
8961049 #define    FCDI_EXTENDED_EVENT_PPS_LENMIN 16
8971050 #define    FCDI_EXTENDED_EVENT_PPS_LENMAX 248
1051
+#define    FCDI_EXTENDED_EVENT_PPS_LENMAX_MCDI2 1016
8981052 #define    FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num))
1053
+#define    FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_NUM(len) (((len)-8)/8)
8991054 /* Number of timestamps following */
9001055 #define       FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0
9011056 #define       FCDI_EXTENDED_EVENT_PPS_COUNT_LEN 4
....@@ -918,6 +1073,7 @@
9181073 #define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12
9191074 #define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1
9201075 #define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30
1076
+#define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM_MCDI2 126
9211077 #define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64
9221078 #define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64
9231079 
....@@ -937,24 +1093,33 @@
9371093 #define          MUM_EVENT_LEVEL_FATAL 0x3
9381094 #define       MUM_EVENT_DATA_OFST 0
9391095 #define       MUM_EVENT_DATA_LEN 4
1096
+#define        MUM_EVENT_SENSOR_ID_OFST 0
9401097 #define        MUM_EVENT_SENSOR_ID_LBN 0
9411098 #define        MUM_EVENT_SENSOR_ID_WIDTH 8
9421099 /*             Enum values, see field(s): */
9431100 /*                MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
1101
+#define        MUM_EVENT_SENSOR_STATE_OFST 0
9441102 #define        MUM_EVENT_SENSOR_STATE_LBN 8
9451103 #define        MUM_EVENT_SENSOR_STATE_WIDTH 8
1104
+#define        MUM_EVENT_PORT_PHY_READY_OFST 0
9461105 #define        MUM_EVENT_PORT_PHY_READY_LBN 0
9471106 #define        MUM_EVENT_PORT_PHY_READY_WIDTH 1
1107
+#define        MUM_EVENT_PORT_PHY_LINK_UP_OFST 0
9481108 #define        MUM_EVENT_PORT_PHY_LINK_UP_LBN 1
9491109 #define        MUM_EVENT_PORT_PHY_LINK_UP_WIDTH 1
1110
+#define        MUM_EVENT_PORT_PHY_TX_LOL_OFST 0
9501111 #define        MUM_EVENT_PORT_PHY_TX_LOL_LBN 2
9511112 #define        MUM_EVENT_PORT_PHY_TX_LOL_WIDTH 1
1113
+#define        MUM_EVENT_PORT_PHY_RX_LOL_OFST 0
9521114 #define        MUM_EVENT_PORT_PHY_RX_LOL_LBN 3
9531115 #define        MUM_EVENT_PORT_PHY_RX_LOL_WIDTH 1
1116
+#define        MUM_EVENT_PORT_PHY_TX_LOS_OFST 0
9541117 #define        MUM_EVENT_PORT_PHY_TX_LOS_LBN 4
9551118 #define        MUM_EVENT_PORT_PHY_TX_LOS_WIDTH 1
1119
+#define        MUM_EVENT_PORT_PHY_RX_LOS_OFST 0
9561120 #define        MUM_EVENT_PORT_PHY_RX_LOS_LBN 5
9571121 #define        MUM_EVENT_PORT_PHY_RX_LOS_WIDTH 1
1122
+#define        MUM_EVENT_PORT_PHY_TX_FAULT_OFST 0
9581123 #define        MUM_EVENT_PORT_PHY_TX_FAULT_LBN 6
9591124 #define        MUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 1
9601125 #define       MUM_EVENT_DATA_LBN 0
....@@ -1019,6 +1184,7 @@
10191184  * has additional checks to reject insecure calls.
10201185  */
10211186 #define MC_CMD_READ32 0x1
1187
+#undef MC_CMD_0x1_PRIVILEGE_CTG
10221188 
10231189 #define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
10241190 
....@@ -1032,11 +1198,14 @@
10321198 /* MC_CMD_READ32_OUT msgresponse */
10331199 #define    MC_CMD_READ32_OUT_LENMIN 4
10341200 #define    MC_CMD_READ32_OUT_LENMAX 252
1201
+#define    MC_CMD_READ32_OUT_LENMAX_MCDI2 1020
10351202 #define    MC_CMD_READ32_OUT_LEN(num) (0+4*(num))
1203
+#define    MC_CMD_READ32_OUT_BUFFER_NUM(len) (((len)-0)/4)
10361204 #define       MC_CMD_READ32_OUT_BUFFER_OFST 0
10371205 #define       MC_CMD_READ32_OUT_BUFFER_LEN 4
10381206 #define       MC_CMD_READ32_OUT_BUFFER_MINNUM 1
10391207 #define       MC_CMD_READ32_OUT_BUFFER_MAXNUM 63
1208
+#define       MC_CMD_READ32_OUT_BUFFER_MAXNUM_MCDI2 255
10401209 
10411210 
10421211 /***********************************/
....@@ -1044,19 +1213,23 @@
10441213  * Write multiple 32byte words to MC memory.
10451214  */
10461215 #define MC_CMD_WRITE32 0x2
1216
+#undef MC_CMD_0x2_PRIVILEGE_CTG
10471217 
10481218 #define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_INSECURE
10491219 
10501220 /* MC_CMD_WRITE32_IN msgrequest */
10511221 #define    MC_CMD_WRITE32_IN_LENMIN 8
10521222 #define    MC_CMD_WRITE32_IN_LENMAX 252
1223
+#define    MC_CMD_WRITE32_IN_LENMAX_MCDI2 1020
10531224 #define    MC_CMD_WRITE32_IN_LEN(num) (4+4*(num))
1225
+#define    MC_CMD_WRITE32_IN_BUFFER_NUM(len) (((len)-4)/4)
10541226 #define       MC_CMD_WRITE32_IN_ADDR_OFST 0
10551227 #define       MC_CMD_WRITE32_IN_ADDR_LEN 4
10561228 #define       MC_CMD_WRITE32_IN_BUFFER_OFST 4
10571229 #define       MC_CMD_WRITE32_IN_BUFFER_LEN 4
10581230 #define       MC_CMD_WRITE32_IN_BUFFER_MINNUM 1
10591231 #define       MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62
1232
+#define       MC_CMD_WRITE32_IN_BUFFER_MAXNUM_MCDI2 254
10601233 
10611234 /* MC_CMD_WRITE32_OUT msgresponse */
10621235 #define    MC_CMD_WRITE32_OUT_LEN 0
....@@ -1069,6 +1242,7 @@
10691242  * has additional checks to reject insecure calls.
10701243  */
10711244 #define MC_CMD_COPYCODE 0x3
1245
+#undef MC_CMD_0x3_PRIVILEGE_CTG
10721246 
10731247 #define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN
10741248 
....@@ -1093,16 +1267,22 @@
10931267  * below)
10941268  */
10951269 #define          MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc
1270
+#define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_OFST 0
10961271 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 17
10971272 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1
1273
+#define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_OFST 0
10981274 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 2
10991275 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1
1276
+#define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_OFST 0
11001277 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 3
11011278 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1
1279
+#define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_OFST 0
11021280 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4
11031281 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1
1282
+#define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_OFST 0
11041283 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 5
11051284 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1
1285
+#define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_OFST 0
11061286 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_LBN 6
11071287 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_WIDTH 1
11081288 /* Destination address */
....@@ -1125,6 +1305,7 @@
11251305  * Select function for function-specific commands.
11261306  */
11271307 #define MC_CMD_SET_FUNC 0x4
1308
+#undef MC_CMD_0x4_PRIVILEGE_CTG
11281309 
11291310 #define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_INSECURE
11301311 
....@@ -1143,6 +1324,7 @@
11431324  * Get the instruction address from which the MC booted.
11441325  */
11451326 #define MC_CMD_GET_BOOT_STATUS 0x5
1327
+#undef MC_CMD_0x5_PRIVILEGE_CTG
11461328 
11471329 #define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11481330 
....@@ -1158,10 +1340,13 @@
11581340 #define          MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef
11591341 #define       MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4
11601342 #define       MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_LEN 4
1343
+#define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_OFST 4
11611344 #define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0
11621345 #define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1
1346
+#define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_OFST 4
11631347 #define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1
11641348 #define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1
1349
+#define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_OFST 4
11651350 #define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2
11661351 #define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1
11671352 
....@@ -1173,6 +1358,7 @@
11731358  * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS
11741359  */
11751360 #define MC_CMD_GET_ASSERTS 0x6
1361
+#undef MC_CMD_0x6_PRIVILEGE_CTG
11761362 
11771363 #define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11781364 
....@@ -1214,6 +1400,104 @@
12141400 #define       MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136
12151401 #define       MC_CMD_GET_ASSERTS_OUT_RESERVED_LEN 4
12161402 
1403
+/* MC_CMD_GET_ASSERTS_OUT_V2 msgresponse: Extended response for MicroBlaze CPUs
1404
+ * found on Riverhead designs
1405
+ */
1406
+#define    MC_CMD_GET_ASSERTS_OUT_V2_LEN 240
1407
+/* Assertion status flag. */
1408
+#define       MC_CMD_GET_ASSERTS_OUT_V2_GLOBAL_FLAGS_OFST 0
1409
+#define       MC_CMD_GET_ASSERTS_OUT_V2_GLOBAL_FLAGS_LEN 4
1410
+/* enum: No assertions have failed. */
1411
+/*               MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 */
1412
+/* enum: A system-level assertion has failed. */
1413
+/*               MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 */
1414
+/* enum: A thread-level assertion has failed. */
1415
+/*               MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 */
1416
+/* enum: The system was reset by the watchdog. */
1417
+/*               MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 */
1418
+/* enum: An illegal address trap stopped the system (huntington and later) */
1419
+/*               MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 */
1420
+/* Failing PC value */
1421
+#define       MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_OFST 4
1422
+#define       MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_LEN 4
1423
+/* Saved GP regs */
1424
+#define       MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_OFST 8
1425
+#define       MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_LEN 4
1426
+#define       MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_NUM 31
1427
+/* enum: A magic value hinting that the value in this register at the time of
1428
+ * the failure has likely been lost.
1429
+ */
1430
+/*               MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 */
1431
+/* Failing thread address */
1432
+#define       MC_CMD_GET_ASSERTS_OUT_V2_THREAD_OFFS_OFST 132
1433
+#define       MC_CMD_GET_ASSERTS_OUT_V2_THREAD_OFFS_LEN 4
1434
+#define       MC_CMD_GET_ASSERTS_OUT_V2_RESERVED_OFST 136
1435
+#define       MC_CMD_GET_ASSERTS_OUT_V2_RESERVED_LEN 4
1436
+/* Saved Special Function Registers */
1437
+#define       MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_OFST 136
1438
+#define       MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_LEN 4
1439
+#define       MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_NUM 26
1440
+
1441
+/* MC_CMD_GET_ASSERTS_OUT_V3 msgresponse: Extended response with asserted
1442
+ * firmware version information
1443
+ */
1444
+#define    MC_CMD_GET_ASSERTS_OUT_V3_LEN 360
1445
+/* Assertion status flag. */
1446
+#define       MC_CMD_GET_ASSERTS_OUT_V3_GLOBAL_FLAGS_OFST 0
1447
+#define       MC_CMD_GET_ASSERTS_OUT_V3_GLOBAL_FLAGS_LEN 4
1448
+/* enum: No assertions have failed. */
1449
+/*               MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 */
1450
+/* enum: A system-level assertion has failed. */
1451
+/*               MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 */
1452
+/* enum: A thread-level assertion has failed. */
1453
+/*               MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 */
1454
+/* enum: The system was reset by the watchdog. */
1455
+/*               MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 */
1456
+/* enum: An illegal address trap stopped the system (huntington and later) */
1457
+/*               MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 */
1458
+/* Failing PC value */
1459
+#define       MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_OFST 4
1460
+#define       MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_LEN 4
1461
+/* Saved GP regs */
1462
+#define       MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_OFST 8
1463
+#define       MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_LEN 4
1464
+#define       MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_NUM 31
1465
+/* enum: A magic value hinting that the value in this register at the time of
1466
+ * the failure has likely been lost.
1467
+ */
1468
+/*               MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 */
1469
+/* Failing thread address */
1470
+#define       MC_CMD_GET_ASSERTS_OUT_V3_THREAD_OFFS_OFST 132
1471
+#define       MC_CMD_GET_ASSERTS_OUT_V3_THREAD_OFFS_LEN 4
1472
+#define       MC_CMD_GET_ASSERTS_OUT_V3_RESERVED_OFST 136
1473
+#define       MC_CMD_GET_ASSERTS_OUT_V3_RESERVED_LEN 4
1474
+/* Saved Special Function Registers */
1475
+#define       MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_OFST 136
1476
+#define       MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_LEN 4
1477
+#define       MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_NUM 26
1478
+/* MC firmware unique build ID (as binary SHA-1 value) */
1479
+#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_ID_OFST 240
1480
+#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_ID_LEN 20
1481
+/* MC firmware build date (as Unix timestamp) */
1482
+#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_OFST 260
1483
+#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LEN 8
1484
+#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_OFST 260
1485
+#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_OFST 264
1486
+/* MC firmware version number */
1487
+#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_OFST 268
1488
+#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LEN 8
1489
+#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_OFST 268
1490
+#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_OFST 272
1491
+/* MC firmware security level */
1492
+#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_OFST 276
1493
+#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_LEN 4
1494
+/* MC firmware extra version info (as null-terminated US-ASCII string) */
1495
+#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_EXTRA_INFO_OFST 280
1496
+#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_EXTRA_INFO_LEN 16
1497
+/* MC firmware build name (as null-terminated US-ASCII string) */
1498
+#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_NAME_OFST 296
1499
+#define       MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_NAME_LEN 64
1500
+
12171501 
12181502 /***********************************/
12191503 /* MC_CMD_LOG_CTRL
....@@ -1221,6 +1505,7 @@
12211505  * sensor notifications and MCDI completions
12221506  */
12231507 #define MC_CMD_LOG_CTRL 0x7
1508
+#undef MC_CMD_0x7_PRIVILEGE_CTG
12241509 
12251510 #define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12261511 
....@@ -1243,9 +1528,10 @@
12431528 
12441529 /***********************************/
12451530 /* MC_CMD_GET_VERSION
1246
- * Get version information about the MC firmware.
1531
+ * Get version information about adapter components.
12471532  */
12481533 #define MC_CMD_GET_VERSION 0x8
1534
+#undef MC_CMD_0x8_PRIVILEGE_CTG
12491535 
12501536 #define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12511537 
....@@ -1306,12 +1592,107 @@
13061592 #define       MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32
13071593 #define       MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16
13081594 
1595
+/* MC_CMD_GET_VERSION_V2_OUT msgresponse: Extended response providing version
1596
+ * information for all adapter components. For Riverhead based designs, base MC
1597
+ * firmware version fields refer to NMC firmware, while CMC firmware data is in
1598
+ * dedicated CMC fields. Flags indicate which data is present in the response
1599
+ * (depending on which components exist on a particular adapter)
1600
+ */
1601
+#define    MC_CMD_GET_VERSION_V2_OUT_LEN 304
1602
+/*            MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
1603
+/*            MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
1604
+/*            Enum values, see field(s): */
1605
+/*               MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
1606
+#define       MC_CMD_GET_VERSION_V2_OUT_PCOL_OFST 4
1607
+#define       MC_CMD_GET_VERSION_V2_OUT_PCOL_LEN 4
1608
+/* 128bit mask of functions supported by the current firmware */
1609
+#define       MC_CMD_GET_VERSION_V2_OUT_SUPPORTED_FUNCS_OFST 8
1610
+#define       MC_CMD_GET_VERSION_V2_OUT_SUPPORTED_FUNCS_LEN 16
1611
+#define       MC_CMD_GET_VERSION_V2_OUT_VERSION_OFST 24
1612
+#define       MC_CMD_GET_VERSION_V2_OUT_VERSION_LEN 8
1613
+#define       MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_OFST 24
1614
+#define       MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_OFST 28
1615
+/* extra info */
1616
+#define       MC_CMD_GET_VERSION_V2_OUT_EXTRA_OFST 32
1617
+#define       MC_CMD_GET_VERSION_V2_OUT_EXTRA_LEN 16
1618
+/* Flags indicating which extended fields are valid */
1619
+#define       MC_CMD_GET_VERSION_V2_OUT_FLAGS_OFST 48
1620
+#define       MC_CMD_GET_VERSION_V2_OUT_FLAGS_LEN 4
1621
+#define        MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_OFST 48
1622
+#define        MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
1623
+#define        MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1
1624
+#define        MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_OFST 48
1625
+#define        MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1
1626
+#define        MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1
1627
+#define        MC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_OFST 48
1628
+#define        MC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_LBN 2
1629
+#define        MC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1
1630
+#define        MC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_OFST 48
1631
+#define        MC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_LBN 3
1632
+#define        MC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1
1633
+#define        MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_OFST 48
1634
+#define        MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
1635
+#define        MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
1636
+/* MC firmware unique build ID (as binary SHA-1 value) */
1637
+#define       MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_ID_OFST 52
1638
+#define       MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_ID_LEN 20
1639
+/* MC firmware security level */
1640
+#define       MC_CMD_GET_VERSION_V2_OUT_MCFW_SECURITY_LEVEL_OFST 72
1641
+#define       MC_CMD_GET_VERSION_V2_OUT_MCFW_SECURITY_LEVEL_LEN 4
1642
+/* MC firmware build name (as null-terminated US-ASCII string) */
1643
+#define       MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_NAME_OFST 76
1644
+#define       MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_NAME_LEN 64
1645
+/* The SUC firmware version as four numbers - a.b.c.d */
1646
+#define       MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_OFST 140
1647
+#define       MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_LEN 4
1648
+#define       MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_NUM 4
1649
+/* SUC firmware build date (as 64-bit Unix timestamp) */
1650
+#define       MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_OFST 156
1651
+#define       MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LEN 8
1652
+#define       MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_OFST 156
1653
+#define       MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_OFST 160
1654
+/* The ID of the SUC chip. This is specific to the platform but typically
1655
+ * indicates family, memory sizes etc. See SF-116728-SW for further details.
1656
+ */
1657
+#define       MC_CMD_GET_VERSION_V2_OUT_SUCFW_CHIP_ID_OFST 164
1658
+#define       MC_CMD_GET_VERSION_V2_OUT_SUCFW_CHIP_ID_LEN 4
1659
+/* The CMC firmware version as four numbers - a.b.c.d */
1660
+#define       MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_OFST 168
1661
+#define       MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_LEN 4
1662
+#define       MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_NUM 4
1663
+/* CMC firmware build date (as 64-bit Unix timestamp) */
1664
+#define       MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_OFST 184
1665
+#define       MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LEN 8
1666
+#define       MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_OFST 184
1667
+#define       MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_OFST 188
1668
+/* FPGA version as three numbers. On Riverhead based systems this field uses
1669
+ * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):
1670
+ * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
1671
+ * => B, ...) FPGA_VERSION[2]: Sub-revision number
1672
+ */
1673
+#define       MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_OFST 192
1674
+#define       MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_LEN 4
1675
+#define       MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_NUM 3
1676
+/* Extra FPGA revision information (as null-terminated US-ASCII string) */
1677
+#define       MC_CMD_GET_VERSION_V2_OUT_FPGA_EXTRA_OFST 204
1678
+#define       MC_CMD_GET_VERSION_V2_OUT_FPGA_EXTRA_LEN 16
1679
+/* Board name / adapter model (as null-terminated US-ASCII string) */
1680
+#define       MC_CMD_GET_VERSION_V2_OUT_BOARD_NAME_OFST 220
1681
+#define       MC_CMD_GET_VERSION_V2_OUT_BOARD_NAME_LEN 16
1682
+/* Board revision number */
1683
+#define       MC_CMD_GET_VERSION_V2_OUT_BOARD_REVISION_OFST 236
1684
+#define       MC_CMD_GET_VERSION_V2_OUT_BOARD_REVISION_LEN 4
1685
+/* Board serial number (as null-terminated US-ASCII string) */
1686
+#define       MC_CMD_GET_VERSION_V2_OUT_BOARD_SERIAL_OFST 240
1687
+#define       MC_CMD_GET_VERSION_V2_OUT_BOARD_SERIAL_LEN 64
1688
+
13091689 
13101690 /***********************************/
13111691 /* MC_CMD_PTP
13121692  * Perform PTP operation
13131693  */
13141694 #define MC_CMD_PTP 0xb
1695
+#undef MC_CMD_0xb_PRIVILEGE_CTG
13151696 
13161697 #define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13171698 
....@@ -1437,7 +1818,9 @@
14371818 /* MC_CMD_PTP_IN_TRANSMIT msgrequest */
14381819 #define    MC_CMD_PTP_IN_TRANSMIT_LENMIN 13
14391820 #define    MC_CMD_PTP_IN_TRANSMIT_LENMAX 252
1821
+#define    MC_CMD_PTP_IN_TRANSMIT_LENMAX_MCDI2 1020
14401822 #define    MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num))
1823
+#define    MC_CMD_PTP_IN_TRANSMIT_PACKET_NUM(len) (((len)-12)/1)
14411824 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
14421825 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
14431826 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
....@@ -1450,6 +1833,7 @@
14501833 #define       MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1
14511834 #define       MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1
14521835 #define       MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240
1836
+#define       MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM_MCDI2 1008
14531837 
14541838 /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */
14551839 #define    MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8
....@@ -1602,7 +1986,9 @@
16021986 /* MC_CMD_PTP_IN_FPGAWRITE msgrequest */
16031987 #define    MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13
16041988 #define    MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252
1989
+#define    MC_CMD_PTP_IN_FPGAWRITE_LENMAX_MCDI2 1020
16051990 #define    MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num))
1991
+#define    MC_CMD_PTP_IN_FPGAWRITE_BUFFER_NUM(len) (((len)-12)/1)
16061992 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
16071993 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
16081994 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
....@@ -1613,6 +1999,7 @@
16131999 #define       MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1
16142000 #define       MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1
16152001 #define       MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240
2002
+#define       MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM_MCDI2 1008
16162003 
16172004 /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */
16182005 #define    MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16
....@@ -1777,8 +2164,10 @@
17772164 /* Original field containing queue ID. Now extended to include flags. */
17782165 #define       MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8
17792166 #define       MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_LEN 4
2167
+#define        MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_OFST 8
17802168 #define        MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0
17812169 #define        MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 16
2170
+#define        MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_OFST 8
17822171 #define        MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 31
17832172 #define        MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 1
17842173 
....@@ -1943,12 +2332,15 @@
19432332 /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */
19442333 #define    MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20
19452334 #define    MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240
2335
+#define    MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX_MCDI2 1020
19462336 #define    MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num))
2337
+#define    MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_NUM(len) (((len)-0)/20)
19472338 /* A set of host and NIC times */
19482339 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0
19492340 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20
19502341 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1
19512342 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12
2343
+#define       MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM_MCDI2 51
19522344 /* Host time immediately before NIC's hardware clock read */
19532345 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0
19542346 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_LEN 4
....@@ -2025,11 +2417,14 @@
20252417 /* MC_CMD_PTP_OUT_FPGAREAD msgresponse */
20262418 #define    MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1
20272419 #define    MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252
2420
+#define    MC_CMD_PTP_OUT_FPGAREAD_LENMAX_MCDI2 1020
20282421 #define    MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num))
2422
+#define    MC_CMD_PTP_OUT_FPGAREAD_BUFFER_NUM(len) (((len)-0)/1)
20292423 #define       MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0
20302424 #define       MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1
20312425 #define       MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1
20322426 #define       MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252
2427
+#define       MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM_MCDI2 1020
20332428 
20342429 /* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */
20352430 #define    MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4
....@@ -2078,12 +2473,16 @@
20782473 /* Various PTP capabilities */
20792474 #define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 8
20802475 #define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_LEN 4
2476
+#define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_OFST 8
20812477 #define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0
20822478 #define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1
2479
+#define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_OFST 8
20832480 #define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_LBN 1
20842481 #define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_WIDTH 1
2482
+#define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_OFST 8
20852483 #define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_LBN 2
20862484 #define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_WIDTH 1
2485
+#define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_OFST 8
20872486 #define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_LBN 3
20882487 #define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_WIDTH 1
20892488 #define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 12
....@@ -2146,6 +2545,7 @@
21462545  * Read 32bit words from the indirect memory map.
21472546  */
21482547 #define MC_CMD_CSR_READ32 0xc
2548
+#undef MC_CMD_0xc_PRIVILEGE_CTG
21492549 
21502550 #define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_INSECURE
21512551 
....@@ -2162,12 +2562,15 @@
21622562 /* MC_CMD_CSR_READ32_OUT msgresponse */
21632563 #define    MC_CMD_CSR_READ32_OUT_LENMIN 4
21642564 #define    MC_CMD_CSR_READ32_OUT_LENMAX 252
2565
+#define    MC_CMD_CSR_READ32_OUT_LENMAX_MCDI2 1020
21652566 #define    MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num))
2567
+#define    MC_CMD_CSR_READ32_OUT_BUFFER_NUM(len) (((len)-0)/4)
21662568 /* The last dword is the status, not a value read */
21672569 #define       MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0
21682570 #define       MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4
21692571 #define       MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1
21702572 #define       MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63
2573
+#define       MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM_MCDI2 255
21712574 
21722575 
21732576 /***********************************/
....@@ -2175,13 +2578,16 @@
21752578  * Write 32bit dwords to the indirect memory map.
21762579  */
21772580 #define MC_CMD_CSR_WRITE32 0xd
2581
+#undef MC_CMD_0xd_PRIVILEGE_CTG
21782582 
21792583 #define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_INSECURE
21802584 
21812585 /* MC_CMD_CSR_WRITE32_IN msgrequest */
21822586 #define    MC_CMD_CSR_WRITE32_IN_LENMIN 12
21832587 #define    MC_CMD_CSR_WRITE32_IN_LENMAX 252
2588
+#define    MC_CMD_CSR_WRITE32_IN_LENMAX_MCDI2 1020
21842589 #define    MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num))
2590
+#define    MC_CMD_CSR_WRITE32_IN_BUFFER_NUM(len) (((len)-8)/4)
21852591 /* Address */
21862592 #define       MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0
21872593 #define       MC_CMD_CSR_WRITE32_IN_ADDR_LEN 4
....@@ -2191,6 +2597,7 @@
21912597 #define       MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4
21922598 #define       MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1
21932599 #define       MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61
2600
+#define       MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM_MCDI2 253
21942601 
21952602 /* MC_CMD_CSR_WRITE32_OUT msgresponse */
21962603 #define    MC_CMD_CSR_WRITE32_OUT_LEN 4
....@@ -2204,6 +2611,7 @@
22042611  * MCDI command to avoid creating too many MCDI commands.
22052612  */
22062613 #define MC_CMD_HP 0x54
2614
+#undef MC_CMD_0x54_PRIVILEGE_CTG
22072615 
22082616 #define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN
22092617 
....@@ -2250,6 +2658,7 @@
22502658  * Get stack information.
22512659  */
22522660 #define MC_CMD_STACKINFO 0xf
2661
+#undef MC_CMD_0xf_PRIVILEGE_CTG
22532662 
22542663 #define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN
22552664 
....@@ -2259,12 +2668,15 @@
22592668 /* MC_CMD_STACKINFO_OUT msgresponse */
22602669 #define    MC_CMD_STACKINFO_OUT_LENMIN 12
22612670 #define    MC_CMD_STACKINFO_OUT_LENMAX 252
2671
+#define    MC_CMD_STACKINFO_OUT_LENMAX_MCDI2 1020
22622672 #define    MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num))
2673
+#define    MC_CMD_STACKINFO_OUT_THREAD_INFO_NUM(len) (((len)-0)/12)
22632674 /* (thread ptr, stack size, free space) for each thread in system */
22642675 #define       MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0
22652676 #define       MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12
22662677 #define       MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1
22672678 #define       MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21
2679
+#define       MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM_MCDI2 85
22682680 
22692681 
22702682 /***********************************/
....@@ -2272,6 +2684,7 @@
22722684  * MDIO register read.
22732685  */
22742686 #define MC_CMD_MDIO_READ 0x10
2687
+#undef MC_CMD_0x10_PRIVILEGE_CTG
22752688 
22762689 #define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL
22772690 
....@@ -2319,6 +2732,7 @@
23192732  * MDIO register write.
23202733  */
23212734 #define MC_CMD_MDIO_WRITE 0x11
2735
+#undef MC_CMD_0x11_PRIVILEGE_CTG
23222736 
23232737 #define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN
23242738 
....@@ -2366,13 +2780,16 @@
23662780  * Write DBI register(s).
23672781  */
23682782 #define MC_CMD_DBI_WRITE 0x12
2783
+#undef MC_CMD_0x12_PRIVILEGE_CTG
23692784 
23702785 #define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_INSECURE
23712786 
23722787 /* MC_CMD_DBI_WRITE_IN msgrequest */
23732788 #define    MC_CMD_DBI_WRITE_IN_LENMIN 12
23742789 #define    MC_CMD_DBI_WRITE_IN_LENMAX 252
2790
+#define    MC_CMD_DBI_WRITE_IN_LENMAX_MCDI2 1020
23752791 #define    MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num))
2792
+#define    MC_CMD_DBI_WRITE_IN_DBIWROP_NUM(len) (((len)-0)/12)
23762793 /* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset
23772794  * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF.
23782795  */
....@@ -2380,6 +2797,7 @@
23802797 #define       MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12
23812798 #define       MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1
23822799 #define       MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21
2800
+#define       MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM_MCDI2 85
23832801 
23842802 /* MC_CMD_DBI_WRITE_OUT msgresponse */
23852803 #define    MC_CMD_DBI_WRITE_OUT_LEN 0
....@@ -2392,10 +2810,13 @@
23922810 #define       MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32
23932811 #define       MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4
23942812 #define       MC_CMD_DBIWROP_TYPEDEF_PARMS_LEN 4
2813
+#define        MC_CMD_DBIWROP_TYPEDEF_VF_NUM_OFST 4
23952814 #define        MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16
23962815 #define        MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16
2816
+#define        MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_OFST 4
23972817 #define        MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15
23982818 #define        MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1
2819
+#define        MC_CMD_DBIWROP_TYPEDEF_CS2_OFST 4
23992820 #define        MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14
24002821 #define        MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1
24012822 #define       MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32
....@@ -2529,6 +2950,7 @@
25292950  * Returns the MC firmware configuration structure.
25302951  */
25312952 #define MC_CMD_GET_BOARD_CFG 0x18
2953
+#undef MC_CMD_0x18_PRIVILEGE_CTG
25322954 
25332955 #define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL
25342956 
....@@ -2538,7 +2960,9 @@
25382960 /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */
25392961 #define    MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96
25402962 #define    MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136
2963
+#define    MC_CMD_GET_BOARD_CFG_OUT_LENMAX_MCDI2 136
25412964 #define    MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num))
2965
+#define    MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_NUM(len) (((len)-72)/2)
25422966 #define       MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0
25432967 #define       MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_LEN 4
25442968 #define       MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4
....@@ -2593,6 +3017,7 @@
25933017 #define       MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2
25943018 #define       MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12
25953019 #define       MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32
3020
+#define       MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM_MCDI2 32
25963021 
25973022 
25983023 /***********************************/
....@@ -2600,13 +3025,16 @@
26003025  * Read DBI register(s) -- extended functionality
26013026  */
26023027 #define MC_CMD_DBI_READX 0x19
3028
+#undef MC_CMD_0x19_PRIVILEGE_CTG
26033029 
26043030 #define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_INSECURE
26053031 
26063032 /* MC_CMD_DBI_READX_IN msgrequest */
26073033 #define    MC_CMD_DBI_READX_IN_LENMIN 8
26083034 #define    MC_CMD_DBI_READX_IN_LENMAX 248
3035
+#define    MC_CMD_DBI_READX_IN_LENMAX_MCDI2 1016
26093036 #define    MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num))
3037
+#define    MC_CMD_DBI_READX_IN_DBIRDOP_NUM(len) (((len)-0)/8)
26103038 /* Each Read op consists of an address (offset 0), VF/CS2) */
26113039 #define       MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0
26123040 #define       MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8
....@@ -2614,16 +3042,20 @@
26143042 #define       MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4
26153043 #define       MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1
26163044 #define       MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31
3045
+#define       MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM_MCDI2 127
26173046 
26183047 /* MC_CMD_DBI_READX_OUT msgresponse */
26193048 #define    MC_CMD_DBI_READX_OUT_LENMIN 4
26203049 #define    MC_CMD_DBI_READX_OUT_LENMAX 252
3050
+#define    MC_CMD_DBI_READX_OUT_LENMAX_MCDI2 1020
26213051 #define    MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num))
3052
+#define    MC_CMD_DBI_READX_OUT_VALUE_NUM(len) (((len)-0)/4)
26223053 /* Value */
26233054 #define       MC_CMD_DBI_READX_OUT_VALUE_OFST 0
26243055 #define       MC_CMD_DBI_READX_OUT_VALUE_LEN 4
26253056 #define       MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1
26263057 #define       MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63
3058
+#define       MC_CMD_DBI_READX_OUT_VALUE_MAXNUM_MCDI2 255
26273059 
26283060 /* MC_CMD_DBIRDOP_TYPEDEF structuredef */
26293061 #define    MC_CMD_DBIRDOP_TYPEDEF_LEN 8
....@@ -2633,10 +3065,13 @@
26333065 #define       MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32
26343066 #define       MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4
26353067 #define       MC_CMD_DBIRDOP_TYPEDEF_PARMS_LEN 4
3068
+#define        MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_OFST 4
26363069 #define        MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16
26373070 #define        MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16
3071
+#define        MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_OFST 4
26383072 #define        MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15
26393073 #define        MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1
3074
+#define        MC_CMD_DBIRDOP_TYPEDEF_CS2_OFST 4
26403075 #define        MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14
26413076 #define        MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1
26423077 #define       MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32
....@@ -2648,6 +3083,7 @@
26483083  * Set the 16byte seed for the MC pseudo-random generator.
26493084  */
26503085 #define MC_CMD_SET_RAND_SEED 0x1a
3086
+#undef MC_CMD_0x1a_PRIVILEGE_CTG
26513087 
26523088 #define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_INSECURE
26533089 
....@@ -2673,12 +3109,15 @@
26733109 /* MC_CMD_LTSSM_HIST_OUT msgresponse */
26743110 #define    MC_CMD_LTSSM_HIST_OUT_LENMIN 0
26753111 #define    MC_CMD_LTSSM_HIST_OUT_LENMAX 252
3112
+#define    MC_CMD_LTSSM_HIST_OUT_LENMAX_MCDI2 1020
26763113 #define    MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num))
3114
+#define    MC_CMD_LTSSM_HIST_OUT_DATA_NUM(len) (((len)-0)/4)
26773115 /* variable number of LTSSM values, as bytes. The history is read-to-clear. */
26783116 #define       MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0
26793117 #define       MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4
26803118 #define       MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0
26813119 #define       MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63
3120
+#define       MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM_MCDI2 255
26823121 
26833122 
26843123 /***********************************/
....@@ -2691,6 +3130,7 @@
26913130  * platforms.
26923131  */
26933132 #define MC_CMD_DRV_ATTACH 0x1c
3133
+#undef MC_CMD_0x1c_PRIVILEGE_CTG
26943134 
26953135 #define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
26963136 
....@@ -2699,18 +3139,33 @@
26993139 /* new state to set if UPDATE=1 */
27003140 #define       MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0
27013141 #define       MC_CMD_DRV_ATTACH_IN_NEW_STATE_LEN 4
3142
+#define        MC_CMD_DRV_ATTACH_OFST 0
27023143 #define        MC_CMD_DRV_ATTACH_LBN 0
27033144 #define        MC_CMD_DRV_ATTACH_WIDTH 1
3145
+#define        MC_CMD_DRV_ATTACH_IN_ATTACH_OFST 0
27043146 #define        MC_CMD_DRV_ATTACH_IN_ATTACH_LBN 0
27053147 #define        MC_CMD_DRV_ATTACH_IN_ATTACH_WIDTH 1
3148
+#define        MC_CMD_DRV_PREBOOT_OFST 0
27063149 #define        MC_CMD_DRV_PREBOOT_LBN 1
27073150 #define        MC_CMD_DRV_PREBOOT_WIDTH 1
3151
+#define        MC_CMD_DRV_ATTACH_IN_PREBOOT_OFST 0
27083152 #define        MC_CMD_DRV_ATTACH_IN_PREBOOT_LBN 1
27093153 #define        MC_CMD_DRV_ATTACH_IN_PREBOOT_WIDTH 1
3154
+#define        MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_OFST 0
27103155 #define        MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_LBN 2
27113156 #define        MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_WIDTH 1
3157
+#define        MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_OFST 0
27123158 #define        MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_LBN 3
27133159 #define        MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_WIDTH 1
3160
+#define        MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_OFST 0
3161
+#define        MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_LBN 4
3162
+#define        MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_WIDTH 1
3163
+#define        MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_OFST 0
3164
+#define        MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_LBN 5
3165
+#define        MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_WIDTH 1
3166
+#define        MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_OFST 0
3167
+#define        MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_LBN 5
3168
+#define        MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_WIDTH 1
27143169 /* 1 to set new state, or 0 to just report the existing state */
27153170 #define       MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4
27163171 #define       MC_CMD_DRV_ATTACH_IN_UPDATE_LEN 4
....@@ -2739,8 +3194,90 @@
27393194  * bug69716)
27403195  */
27413196 #define          MC_CMD_FW_L3XUDP 0x7
3197
+/* enum: Requests that the MC keep whatever datapath firmware is currently
3198
+ * running. It's used for test purposes, where we want to be able to shmboot
3199
+ * special test firmware variants. This option is only recognised in eftest
3200
+ * (i.e. non-production) builds.
3201
+ */
3202
+#define          MC_CMD_FW_KEEP_CURRENT_EFTEST_ONLY 0xfffffffe
27423203 /* enum: Only this option is allowed for non-admin functions */
27433204 #define          MC_CMD_FW_DONT_CARE 0xffffffff
3205
+
3206
+/* MC_CMD_DRV_ATTACH_IN_V2 msgrequest: Updated DRV_ATTACH to include driver
3207
+ * version
3208
+ */
3209
+#define    MC_CMD_DRV_ATTACH_IN_V2_LEN 32
3210
+/* new state to set if UPDATE=1 */
3211
+#define       MC_CMD_DRV_ATTACH_IN_V2_NEW_STATE_OFST 0
3212
+#define       MC_CMD_DRV_ATTACH_IN_V2_NEW_STATE_LEN 4
3213
+/*             MC_CMD_DRV_ATTACH_OFST 0 */
3214
+/*             MC_CMD_DRV_ATTACH_LBN 0 */
3215
+/*             MC_CMD_DRV_ATTACH_WIDTH 1 */
3216
+#define        MC_CMD_DRV_ATTACH_IN_V2_ATTACH_OFST 0
3217
+#define        MC_CMD_DRV_ATTACH_IN_V2_ATTACH_LBN 0
3218
+#define        MC_CMD_DRV_ATTACH_IN_V2_ATTACH_WIDTH 1
3219
+/*             MC_CMD_DRV_PREBOOT_OFST 0 */
3220
+/*             MC_CMD_DRV_PREBOOT_LBN 1 */
3221
+/*             MC_CMD_DRV_PREBOOT_WIDTH 1 */
3222
+#define        MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_OFST 0
3223
+#define        MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_LBN 1
3224
+#define        MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_WIDTH 1
3225
+#define        MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_OFST 0
3226
+#define        MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_LBN 2
3227
+#define        MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_WIDTH 1
3228
+#define        MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_OFST 0
3229
+#define        MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_LBN 3
3230
+#define        MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_WIDTH 1
3231
+#define        MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_OFST 0
3232
+#define        MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_LBN 4
3233
+#define        MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_WIDTH 1
3234
+#define        MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_OFST 0
3235
+#define        MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_LBN 5
3236
+#define        MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_WIDTH 1
3237
+#define        MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_OFST 0
3238
+#define        MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_LBN 5
3239
+#define        MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_WIDTH 1
3240
+/* 1 to set new state, or 0 to just report the existing state */
3241
+#define       MC_CMD_DRV_ATTACH_IN_V2_UPDATE_OFST 4
3242
+#define       MC_CMD_DRV_ATTACH_IN_V2_UPDATE_LEN 4
3243
+/* preferred datapath firmware (for Huntington; ignored for Siena) */
3244
+#define       MC_CMD_DRV_ATTACH_IN_V2_FIRMWARE_ID_OFST 8
3245
+#define       MC_CMD_DRV_ATTACH_IN_V2_FIRMWARE_ID_LEN 4
3246
+/* enum: Prefer to use full featured firmware */
3247
+/*               MC_CMD_FW_FULL_FEATURED 0x0 */
3248
+/* enum: Prefer to use firmware with fewer features but lower latency */
3249
+/*               MC_CMD_FW_LOW_LATENCY 0x1 */
3250
+/* enum: Prefer to use firmware for SolarCapture packed stream mode */
3251
+/*               MC_CMD_FW_PACKED_STREAM 0x2 */
3252
+/* enum: Prefer to use firmware with fewer features and simpler TX event
3253
+ * batching but higher TX packet rate
3254
+ */
3255
+/*               MC_CMD_FW_HIGH_TX_RATE 0x3 */
3256
+/* enum: Reserved value */
3257
+/*               MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4 */
3258
+/* enum: Prefer to use firmware with additional "rules engine" filtering
3259
+ * support
3260
+ */
3261
+/*               MC_CMD_FW_RULES_ENGINE 0x5 */
3262
+/* enum: Prefer to use firmware with additional DPDK support */
3263
+/*               MC_CMD_FW_DPDK 0x6 */
3264
+/* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and
3265
+ * bug69716)
3266
+ */
3267
+/*               MC_CMD_FW_L3XUDP 0x7 */
3268
+/* enum: Requests that the MC keep whatever datapath firmware is currently
3269
+ * running. It's used for test purposes, where we want to be able to shmboot
3270
+ * special test firmware variants. This option is only recognised in eftest
3271
+ * (i.e. non-production) builds.
3272
+ */
3273
+/*               MC_CMD_FW_KEEP_CURRENT_EFTEST_ONLY 0xfffffffe */
3274
+/* enum: Only this option is allowed for non-admin functions */
3275
+/*               MC_CMD_FW_DONT_CARE 0xffffffff */
3276
+/* Version of the driver to be reported by management protocols (e.g. NC-SI)
3277
+ * handled by the NIC. This is a zero-terminated ASCII string.
3278
+ */
3279
+#define       MC_CMD_DRV_ATTACH_IN_V2_DRIVER_VERSION_OFST 12
3280
+#define       MC_CMD_DRV_ATTACH_IN_V2_DRIVER_VERSION_LEN 20
27443281 
27453282 /* MC_CMD_DRV_ATTACH_OUT msgresponse */
27463283 #define    MC_CMD_DRV_ATTACH_OUT_LEN 4
....@@ -2773,6 +3310,13 @@
27733310  * input.
27743311  */
27753312 #define          MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_VI_SPREADING_ENABLED 0x4
3313
+/* enum: Used during development only. Should no longer be used. */
3314
+#define          MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_RX_VI_SPREADING_INHIBITED 0x5
3315
+/* enum: If set, indicates that TX only spreading is enabled. Even-numbered
3316
+ * TXQs will use one engine, and odd-numbered TXQs will use the other. This
3317
+ * also has the effect that only even-numbered RXQs will receive traffic.
3318
+ */
3319
+#define          MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TX_ONLY_VI_SPREADING_ENABLED 0x5
27763320 
27773321 
27783322 /***********************************/
....@@ -2798,6 +3342,7 @@
27983342  * use MC_CMD_ENTITY_RESET instead.
27993343  */
28003344 #define MC_CMD_PORT_RESET 0x20
3345
+#undef MC_CMD_0x20_PRIVILEGE_CTG
28013346 
28023347 #define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL
28033348 
....@@ -2824,6 +3369,7 @@
28243369  */
28253370 #define       MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0
28263371 #define       MC_CMD_ENTITY_RESET_IN_FLAG_LEN 4
3372
+#define        MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_OFST 0
28273373 #define        MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0
28283374 #define        MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1
28293375 
....@@ -2930,17 +3476,22 @@
29303476  * Copy the given ASCII string out onto UART and/or out of the network port.
29313477  */
29323478 #define MC_CMD_PUTS 0x23
3479
+#undef MC_CMD_0x23_PRIVILEGE_CTG
29333480 
29343481 #define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_INSECURE
29353482 
29363483 /* MC_CMD_PUTS_IN msgrequest */
29373484 #define    MC_CMD_PUTS_IN_LENMIN 13
29383485 #define    MC_CMD_PUTS_IN_LENMAX 252
3486
+#define    MC_CMD_PUTS_IN_LENMAX_MCDI2 1020
29393487 #define    MC_CMD_PUTS_IN_LEN(num) (12+1*(num))
3488
+#define    MC_CMD_PUTS_IN_STRING_NUM(len) (((len)-12)/1)
29403489 #define       MC_CMD_PUTS_IN_DEST_OFST 0
29413490 #define       MC_CMD_PUTS_IN_DEST_LEN 4
3491
+#define        MC_CMD_PUTS_IN_UART_OFST 0
29423492 #define        MC_CMD_PUTS_IN_UART_LBN 0
29433493 #define        MC_CMD_PUTS_IN_UART_WIDTH 1
3494
+#define        MC_CMD_PUTS_IN_PORT_OFST 0
29443495 #define        MC_CMD_PUTS_IN_PORT_LBN 1
29453496 #define        MC_CMD_PUTS_IN_PORT_WIDTH 1
29463497 #define       MC_CMD_PUTS_IN_DHOST_OFST 4
....@@ -2949,6 +3500,7 @@
29493500 #define       MC_CMD_PUTS_IN_STRING_LEN 1
29503501 #define       MC_CMD_PUTS_IN_STRING_MINNUM 1
29513502 #define       MC_CMD_PUTS_IN_STRING_MAXNUM 240
3503
+#define       MC_CMD_PUTS_IN_STRING_MAXNUM_MCDI2 1008
29523504 
29533505 /* MC_CMD_PUTS_OUT msgresponse */
29543506 #define    MC_CMD_PUTS_OUT_LEN 0
....@@ -2960,6 +3512,7 @@
29603512  * 'zombie' state. Locks required: None
29613513  */
29623514 #define MC_CMD_GET_PHY_CFG 0x24
3515
+#undef MC_CMD_0x24_PRIVILEGE_CTG
29633516 
29643517 #define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL
29653518 
....@@ -2971,18 +3524,25 @@
29713524 /* flags */
29723525 #define       MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0
29733526 #define       MC_CMD_GET_PHY_CFG_OUT_FLAGS_LEN 4
3527
+#define        MC_CMD_GET_PHY_CFG_OUT_PRESENT_OFST 0
29743528 #define        MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0
29753529 #define        MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1
3530
+#define        MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_OFST 0
29763531 #define        MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1
29773532 #define        MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1
3533
+#define        MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_OFST 0
29783534 #define        MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2
29793535 #define        MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1
3536
+#define        MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_OFST 0
29803537 #define        MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3
29813538 #define        MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1
3539
+#define        MC_CMD_GET_PHY_CFG_OUT_POWEROFF_OFST 0
29823540 #define        MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4
29833541 #define        MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1
3542
+#define        MC_CMD_GET_PHY_CFG_OUT_TXDIS_OFST 0
29843543 #define        MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5
29853544 #define        MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1
3545
+#define        MC_CMD_GET_PHY_CFG_OUT_BIST_OFST 0
29863546 #define        MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6
29873547 #define        MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1
29883548 /* ?? */
....@@ -2991,46 +3551,67 @@
29913551 /* Bitmask of supported capabilities */
29923552 #define       MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8
29933553 #define       MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_LEN 4
3554
+#define        MC_CMD_PHY_CAP_10HDX_OFST 8
29943555 #define        MC_CMD_PHY_CAP_10HDX_LBN 1
29953556 #define        MC_CMD_PHY_CAP_10HDX_WIDTH 1
3557
+#define        MC_CMD_PHY_CAP_10FDX_OFST 8
29963558 #define        MC_CMD_PHY_CAP_10FDX_LBN 2
29973559 #define        MC_CMD_PHY_CAP_10FDX_WIDTH 1
3560
+#define        MC_CMD_PHY_CAP_100HDX_OFST 8
29983561 #define        MC_CMD_PHY_CAP_100HDX_LBN 3
29993562 #define        MC_CMD_PHY_CAP_100HDX_WIDTH 1
3563
+#define        MC_CMD_PHY_CAP_100FDX_OFST 8
30003564 #define        MC_CMD_PHY_CAP_100FDX_LBN 4
30013565 #define        MC_CMD_PHY_CAP_100FDX_WIDTH 1
3566
+#define        MC_CMD_PHY_CAP_1000HDX_OFST 8
30023567 #define        MC_CMD_PHY_CAP_1000HDX_LBN 5
30033568 #define        MC_CMD_PHY_CAP_1000HDX_WIDTH 1
3569
+#define        MC_CMD_PHY_CAP_1000FDX_OFST 8
30043570 #define        MC_CMD_PHY_CAP_1000FDX_LBN 6
30053571 #define        MC_CMD_PHY_CAP_1000FDX_WIDTH 1
3572
+#define        MC_CMD_PHY_CAP_10000FDX_OFST 8
30063573 #define        MC_CMD_PHY_CAP_10000FDX_LBN 7
30073574 #define        MC_CMD_PHY_CAP_10000FDX_WIDTH 1
3575
+#define        MC_CMD_PHY_CAP_PAUSE_OFST 8
30083576 #define        MC_CMD_PHY_CAP_PAUSE_LBN 8
30093577 #define        MC_CMD_PHY_CAP_PAUSE_WIDTH 1
3578
+#define        MC_CMD_PHY_CAP_ASYM_OFST 8
30103579 #define        MC_CMD_PHY_CAP_ASYM_LBN 9
30113580 #define        MC_CMD_PHY_CAP_ASYM_WIDTH 1
3581
+#define        MC_CMD_PHY_CAP_AN_OFST 8
30123582 #define        MC_CMD_PHY_CAP_AN_LBN 10
30133583 #define        MC_CMD_PHY_CAP_AN_WIDTH 1
3584
+#define        MC_CMD_PHY_CAP_40000FDX_OFST 8
30143585 #define        MC_CMD_PHY_CAP_40000FDX_LBN 11
30153586 #define        MC_CMD_PHY_CAP_40000FDX_WIDTH 1
3587
+#define        MC_CMD_PHY_CAP_DDM_OFST 8
30163588 #define        MC_CMD_PHY_CAP_DDM_LBN 12
30173589 #define        MC_CMD_PHY_CAP_DDM_WIDTH 1
3590
+#define        MC_CMD_PHY_CAP_100000FDX_OFST 8
30183591 #define        MC_CMD_PHY_CAP_100000FDX_LBN 13
30193592 #define        MC_CMD_PHY_CAP_100000FDX_WIDTH 1
3593
+#define        MC_CMD_PHY_CAP_25000FDX_OFST 8
30203594 #define        MC_CMD_PHY_CAP_25000FDX_LBN 14
30213595 #define        MC_CMD_PHY_CAP_25000FDX_WIDTH 1
3596
+#define        MC_CMD_PHY_CAP_50000FDX_OFST 8
30223597 #define        MC_CMD_PHY_CAP_50000FDX_LBN 15
30233598 #define        MC_CMD_PHY_CAP_50000FDX_WIDTH 1
3599
+#define        MC_CMD_PHY_CAP_BASER_FEC_OFST 8
30243600 #define        MC_CMD_PHY_CAP_BASER_FEC_LBN 16
30253601 #define        MC_CMD_PHY_CAP_BASER_FEC_WIDTH 1
3602
+#define        MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_OFST 8
30263603 #define        MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_LBN 17
30273604 #define        MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_WIDTH 1
3605
+#define        MC_CMD_PHY_CAP_RS_FEC_OFST 8
30283606 #define        MC_CMD_PHY_CAP_RS_FEC_LBN 18
30293607 #define        MC_CMD_PHY_CAP_RS_FEC_WIDTH 1
3608
+#define        MC_CMD_PHY_CAP_RS_FEC_REQUESTED_OFST 8
30303609 #define        MC_CMD_PHY_CAP_RS_FEC_REQUESTED_LBN 19
30313610 #define        MC_CMD_PHY_CAP_RS_FEC_REQUESTED_WIDTH 1
3611
+#define        MC_CMD_PHY_CAP_25G_BASER_FEC_OFST 8
30323612 #define        MC_CMD_PHY_CAP_25G_BASER_FEC_LBN 20
30333613 #define        MC_CMD_PHY_CAP_25G_BASER_FEC_WIDTH 1
3614
+#define        MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_OFST 8
30343615 #define        MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_LBN 21
30353616 #define        MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_WIDTH 1
30363617 /* ?? */
....@@ -3087,6 +3668,7 @@
30873668  * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held)
30883669  */
30893670 #define MC_CMD_START_BIST 0x25
3671
+#undef MC_CMD_0x25_PRIVILEGE_CTG
30903672 
30913673 #define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN
30923674 
....@@ -3126,6 +3708,7 @@
31263708  * EACCES (if PHY_LOCK is not held).
31273709  */
31283710 #define MC_CMD_POLL_BIST 0x26
3711
+#undef MC_CMD_0x26_PRIVILEGE_CTG
31293712 
31303713 #define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN
31313714 
....@@ -3298,11 +3881,14 @@
32983881 /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */
32993882 #define    MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4
33003883 #define    MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252
3884
+#define    MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX_MCDI2 1020
33013885 #define    MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num))
3886
+#define    MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_NUM(len) (((len)-0)/4)
33023887 #define       MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0
33033888 #define       MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4
33043889 #define       MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1
33053890 #define       MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63
3891
+#define       MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM_MCDI2 255
33063892 
33073893 /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */
33083894 #define    MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0
....@@ -3313,6 +3899,7 @@
33133899  * Returns a bitmask of loopback modes available at each speed.
33143900  */
33153901 #define MC_CMD_GET_LOOPBACK_MODES 0x28
3902
+#undef MC_CMD_0x28_PRIVILEGE_CTG
33163903 
33173904 #define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL
33183905 
....@@ -3608,6 +4195,7 @@
36084195  * ETIME.
36094196  */
36104197 #define MC_CMD_GET_LINK 0x29
4198
+#undef MC_CMD_0x29_PRIVILEGE_CTG
36114199 
36124200 #define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL
36134201 
....@@ -3638,18 +4226,30 @@
36384226 /*               MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
36394227 #define       MC_CMD_GET_LINK_OUT_FLAGS_OFST 16
36404228 #define       MC_CMD_GET_LINK_OUT_FLAGS_LEN 4
4229
+#define        MC_CMD_GET_LINK_OUT_LINK_UP_OFST 16
36414230 #define        MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0
36424231 #define        MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1
4232
+#define        MC_CMD_GET_LINK_OUT_FULL_DUPLEX_OFST 16
36434233 #define        MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1
36444234 #define        MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1
4235
+#define        MC_CMD_GET_LINK_OUT_BPX_LINK_OFST 16
36454236 #define        MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2
36464237 #define        MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1
4238
+#define        MC_CMD_GET_LINK_OUT_PHY_LINK_OFST 16
36474239 #define        MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3
36484240 #define        MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1
4241
+#define        MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_OFST 16
36494242 #define        MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6
36504243 #define        MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1
4244
+#define        MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_OFST 16
36514245 #define        MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7
36524246 #define        MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1
4247
+#define        MC_CMD_GET_LINK_OUT_MODULE_UP_VALID_OFST 16
4248
+#define        MC_CMD_GET_LINK_OUT_MODULE_UP_VALID_LBN 8
4249
+#define        MC_CMD_GET_LINK_OUT_MODULE_UP_VALID_WIDTH 1
4250
+#define        MC_CMD_GET_LINK_OUT_MODULE_UP_OFST 16
4251
+#define        MC_CMD_GET_LINK_OUT_MODULE_UP_LBN 9
4252
+#define        MC_CMD_GET_LINK_OUT_MODULE_UP_WIDTH 1
36534253 /* This returns the negotiated flow control value. */
36544254 #define       MC_CMD_GET_LINK_OUT_FCNTL_OFST 20
36554255 #define       MC_CMD_GET_LINK_OUT_FCNTL_LEN 4
....@@ -3657,12 +4257,16 @@
36574257 /*               MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */
36584258 #define       MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24
36594259 #define       MC_CMD_GET_LINK_OUT_MAC_FAULT_LEN 4
4260
+#define        MC_CMD_MAC_FAULT_XGMII_LOCAL_OFST 24
36604261 #define        MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0
36614262 #define        MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1
4263
+#define        MC_CMD_MAC_FAULT_XGMII_REMOTE_OFST 24
36624264 #define        MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1
36634265 #define        MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1
4266
+#define        MC_CMD_MAC_FAULT_SGMII_REMOTE_OFST 24
36644267 #define        MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2
36654268 #define        MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1
4269
+#define        MC_CMD_MAC_FAULT_PENDING_RECONFIG_OFST 24
36664270 #define        MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3
36674271 #define        MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1
36684272 
....@@ -3690,18 +4294,30 @@
36904294 /*               MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
36914295 #define       MC_CMD_GET_LINK_OUT_V2_FLAGS_OFST 16
36924296 #define       MC_CMD_GET_LINK_OUT_V2_FLAGS_LEN 4
4297
+#define        MC_CMD_GET_LINK_OUT_V2_LINK_UP_OFST 16
36934298 #define        MC_CMD_GET_LINK_OUT_V2_LINK_UP_LBN 0
36944299 #define        MC_CMD_GET_LINK_OUT_V2_LINK_UP_WIDTH 1
4300
+#define        MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_OFST 16
36954301 #define        MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_LBN 1
36964302 #define        MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_WIDTH 1
4303
+#define        MC_CMD_GET_LINK_OUT_V2_BPX_LINK_OFST 16
36974304 #define        MC_CMD_GET_LINK_OUT_V2_BPX_LINK_LBN 2
36984305 #define        MC_CMD_GET_LINK_OUT_V2_BPX_LINK_WIDTH 1
4306
+#define        MC_CMD_GET_LINK_OUT_V2_PHY_LINK_OFST 16
36994307 #define        MC_CMD_GET_LINK_OUT_V2_PHY_LINK_LBN 3
37004308 #define        MC_CMD_GET_LINK_OUT_V2_PHY_LINK_WIDTH 1
4309
+#define        MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_OFST 16
37014310 #define        MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_LBN 6
37024311 #define        MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_WIDTH 1
4312
+#define        MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_OFST 16
37034313 #define        MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_LBN 7
37044314 #define        MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_WIDTH 1
4315
+#define        MC_CMD_GET_LINK_OUT_V2_MODULE_UP_VALID_OFST 16
4316
+#define        MC_CMD_GET_LINK_OUT_V2_MODULE_UP_VALID_LBN 8
4317
+#define        MC_CMD_GET_LINK_OUT_V2_MODULE_UP_VALID_WIDTH 1
4318
+#define        MC_CMD_GET_LINK_OUT_V2_MODULE_UP_OFST 16
4319
+#define        MC_CMD_GET_LINK_OUT_V2_MODULE_UP_LBN 9
4320
+#define        MC_CMD_GET_LINK_OUT_V2_MODULE_UP_WIDTH 1
37054321 /* This returns the negotiated flow control value. */
37064322 #define       MC_CMD_GET_LINK_OUT_V2_FCNTL_OFST 20
37074323 #define       MC_CMD_GET_LINK_OUT_V2_FCNTL_LEN 4
....@@ -3709,12 +4325,16 @@
37094325 /*               MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */
37104326 #define       MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_OFST 24
37114327 #define       MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_LEN 4
4328
+/*             MC_CMD_MAC_FAULT_XGMII_LOCAL_OFST 24 */
37124329 /*             MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 */
37134330 /*             MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 */
4331
+/*             MC_CMD_MAC_FAULT_XGMII_REMOTE_OFST 24 */
37144332 /*             MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 */
37154333 /*             MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 */
4334
+/*             MC_CMD_MAC_FAULT_SGMII_REMOTE_OFST 24 */
37164335 /*             MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 */
37174336 /*             MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 */
4337
+/*             MC_CMD_MAC_FAULT_PENDING_RECONFIG_OFST 24 */
37184338 /*             MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 */
37194339 /*             MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 */
37204340 /* True local device capabilities (taking into account currently used PMD/MDI,
....@@ -3738,32 +4358,45 @@
37384358 /*               FEC_TYPE/TYPE */
37394359 #define       MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_OFST 40
37404360 #define       MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_LEN 4
4361
+#define        MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_OFST 40
37414362 #define        MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_LBN 0
37424363 #define        MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_WIDTH 1
4364
+#define        MC_CMD_GET_LINK_OUT_V2_PMD_READY_OFST 40
37434365 #define        MC_CMD_GET_LINK_OUT_V2_PMD_READY_LBN 1
37444366 #define        MC_CMD_GET_LINK_OUT_V2_PMD_READY_WIDTH 1
4367
+#define        MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_OFST 40
37454368 #define        MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_LBN 2
37464369 #define        MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_WIDTH 1
4370
+#define        MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_OFST 40
37474371 #define        MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_LBN 3
37484372 #define        MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_WIDTH 1
4373
+#define        MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_OFST 40
37494374 #define        MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_LBN 4
37504375 #define        MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_WIDTH 1
4376
+#define        MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_OFST 40
37514377 #define        MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_LBN 5
37524378 #define        MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_WIDTH 1
4379
+#define        MC_CMD_GET_LINK_OUT_V2_HI_BER_OFST 40
37534380 #define        MC_CMD_GET_LINK_OUT_V2_HI_BER_LBN 6
37544381 #define        MC_CMD_GET_LINK_OUT_V2_HI_BER_WIDTH 1
4382
+#define        MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_OFST 40
37554383 #define        MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_LBN 7
37564384 #define        MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_WIDTH 1
4385
+#define        MC_CMD_GET_LINK_OUT_V2_AN_DONE_OFST 40
37574386 #define        MC_CMD_GET_LINK_OUT_V2_AN_DONE_LBN 8
37584387 #define        MC_CMD_GET_LINK_OUT_V2_AN_DONE_WIDTH 1
4388
+#define        MC_CMD_GET_LINK_OUT_V2_PORT_SHUTDOWN_OFST 40
4389
+#define        MC_CMD_GET_LINK_OUT_V2_PORT_SHUTDOWN_LBN 9
4390
+#define        MC_CMD_GET_LINK_OUT_V2_PORT_SHUTDOWN_WIDTH 1
37594391 
37604392 
37614393 /***********************************/
37624394 /* MC_CMD_SET_LINK
37634395  * Write the unified MAC/PHY link configuration. Locks required: None. Return
3764
- * code: 0, EINVAL, ETIME
4396
+ * code: 0, EINVAL, ETIME, EAGAIN
37654397  */
37664398 #define MC_CMD_SET_LINK 0x2a
4399
+#undef MC_CMD_0x2a_PRIVILEGE_CTG
37674400 
37684401 #define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK
37694402 
....@@ -3777,12 +4410,18 @@
37774410 /* Flags */
37784411 #define       MC_CMD_SET_LINK_IN_FLAGS_OFST 4
37794412 #define       MC_CMD_SET_LINK_IN_FLAGS_LEN 4
4413
+#define        MC_CMD_SET_LINK_IN_LOWPOWER_OFST 4
37804414 #define        MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0
37814415 #define        MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1
4416
+#define        MC_CMD_SET_LINK_IN_POWEROFF_OFST 4
37824417 #define        MC_CMD_SET_LINK_IN_POWEROFF_LBN 1
37834418 #define        MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1
4419
+#define        MC_CMD_SET_LINK_IN_TXDIS_OFST 4
37844420 #define        MC_CMD_SET_LINK_IN_TXDIS_LBN 2
37854421 #define        MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1
4422
+#define        MC_CMD_SET_LINK_IN_LINKDOWN_OFST 4
4423
+#define        MC_CMD_SET_LINK_IN_LINKDOWN_LBN 3
4424
+#define        MC_CMD_SET_LINK_IN_LINKDOWN_WIDTH 1
37864425 /* Loopback mode. */
37874426 #define       MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8
37884427 #define       MC_CMD_SET_LINK_IN_LOOPBACK_MODE_LEN 4
....@@ -3794,6 +4433,50 @@
37944433 #define       MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12
37954434 #define       MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_LEN 4
37964435 
4436
+/* MC_CMD_SET_LINK_IN_V2 msgrequest: Updated SET_LINK to include sequence
4437
+ * number to ensure this SET_LINK command corresponds to the latest
4438
+ * MODULECHANGE event.
4439
+ */
4440
+#define    MC_CMD_SET_LINK_IN_V2_LEN 17
4441
+/* Near-side advertised capabilities. Refer to
4442
+ * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
4443
+ */
4444
+#define       MC_CMD_SET_LINK_IN_V2_CAP_OFST 0
4445
+#define       MC_CMD_SET_LINK_IN_V2_CAP_LEN 4
4446
+/* Flags */
4447
+#define       MC_CMD_SET_LINK_IN_V2_FLAGS_OFST 4
4448
+#define       MC_CMD_SET_LINK_IN_V2_FLAGS_LEN 4
4449
+#define        MC_CMD_SET_LINK_IN_V2_LOWPOWER_OFST 4
4450
+#define        MC_CMD_SET_LINK_IN_V2_LOWPOWER_LBN 0
4451
+#define        MC_CMD_SET_LINK_IN_V2_LOWPOWER_WIDTH 1
4452
+#define        MC_CMD_SET_LINK_IN_V2_POWEROFF_OFST 4
4453
+#define        MC_CMD_SET_LINK_IN_V2_POWEROFF_LBN 1
4454
+#define        MC_CMD_SET_LINK_IN_V2_POWEROFF_WIDTH 1
4455
+#define        MC_CMD_SET_LINK_IN_V2_TXDIS_OFST 4
4456
+#define        MC_CMD_SET_LINK_IN_V2_TXDIS_LBN 2
4457
+#define        MC_CMD_SET_LINK_IN_V2_TXDIS_WIDTH 1
4458
+#define        MC_CMD_SET_LINK_IN_V2_LINKDOWN_OFST 4
4459
+#define        MC_CMD_SET_LINK_IN_V2_LINKDOWN_LBN 3
4460
+#define        MC_CMD_SET_LINK_IN_V2_LINKDOWN_WIDTH 1
4461
+/* Loopback mode. */
4462
+#define       MC_CMD_SET_LINK_IN_V2_LOOPBACK_MODE_OFST 8
4463
+#define       MC_CMD_SET_LINK_IN_V2_LOOPBACK_MODE_LEN 4
4464
+/*            Enum values, see field(s): */
4465
+/*               MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
4466
+/* A loopback speed of "0" is supported, and means (choose any available
4467
+ * speed).
4468
+ */
4469
+#define       MC_CMD_SET_LINK_IN_V2_LOOPBACK_SPEED_OFST 12
4470
+#define       MC_CMD_SET_LINK_IN_V2_LOOPBACK_SPEED_LEN 4
4471
+#define       MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_OFST 16
4472
+#define       MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_LEN 1
4473
+#define        MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_OFST 16
4474
+#define        MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_LBN 0
4475
+#define        MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_WIDTH 7
4476
+#define        MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_OFST 16
4477
+#define        MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_LBN 7
4478
+#define        MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_WIDTH 1
4479
+
37974480 /* MC_CMD_SET_LINK_OUT msgresponse */
37984481 #define    MC_CMD_SET_LINK_OUT_LEN 0
37994482 
....@@ -3803,6 +4486,7 @@
38034486  * Set identification LED state. Locks required: None. Return code: 0, EINVAL
38044487  */
38054488 #define MC_CMD_SET_ID_LED 0x2b
4489
+#undef MC_CMD_0x2b_PRIVILEGE_CTG
38064490 
38074491 #define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK
38084492 
....@@ -3824,6 +4508,7 @@
38244508  * Set MAC configuration. Locks required: None. Return code: 0, EINVAL
38254509  */
38264510 #define MC_CMD_SET_MAC 0x2c
4511
+#undef MC_CMD_0x2c_PRIVILEGE_CTG
38274512 
38284513 #define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
38294514 
....@@ -3842,8 +4527,10 @@
38424527 #define       MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12
38434528 #define       MC_CMD_SET_MAC_IN_REJECT_OFST 16
38444529 #define       MC_CMD_SET_MAC_IN_REJECT_LEN 4
4530
+#define        MC_CMD_SET_MAC_IN_REJECT_UNCST_OFST 16
38454531 #define        MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0
38464532 #define        MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1
4533
+#define        MC_CMD_SET_MAC_IN_REJECT_BRDCST_OFST 16
38474534 #define        MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1
38484535 #define        MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1
38494536 #define       MC_CMD_SET_MAC_IN_FCNTL_OFST 20
....@@ -3862,6 +4549,7 @@
38624549 #define          MC_CMD_FCNTL_GENERATE 0x5
38634550 #define       MC_CMD_SET_MAC_IN_FLAGS_OFST 24
38644551 #define       MC_CMD_SET_MAC_IN_FLAGS_LEN 4
4552
+#define        MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_OFST 24
38654553 #define        MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0
38664554 #define        MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1
38674555 
....@@ -3880,8 +4568,10 @@
38804568 #define       MC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12
38814569 #define       MC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16
38824570 #define       MC_CMD_SET_MAC_EXT_IN_REJECT_LEN 4
4571
+#define        MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_OFST 16
38834572 #define        MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0
38844573 #define        MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 1
4574
+#define        MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_OFST 16
38854575 #define        MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 1
38864576 #define        MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 1
38874577 #define       MC_CMD_SET_MAC_EXT_IN_FCNTL_OFST 20
....@@ -3900,6 +4590,7 @@
39004590 /*               MC_CMD_FCNTL_GENERATE 0x5 */
39014591 #define       MC_CMD_SET_MAC_EXT_IN_FLAGS_OFST 24
39024592 #define       MC_CMD_SET_MAC_EXT_IN_FLAGS_LEN 4
4593
+#define        MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_OFST 24
39034594 #define        MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0
39044595 #define        MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 1
39054596 /* Select which parameters to configure. A parameter will only be modified if
....@@ -3909,14 +4600,19 @@
39094600  */
39104601 #define       MC_CMD_SET_MAC_EXT_IN_CONTROL_OFST 28
39114602 #define       MC_CMD_SET_MAC_EXT_IN_CONTROL_LEN 4
4603
+#define        MC_CMD_SET_MAC_EXT_IN_CFG_MTU_OFST 28
39124604 #define        MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0
39134605 #define        MC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 1
4606
+#define        MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_OFST 28
39144607 #define        MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 1
39154608 #define        MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_WIDTH 1
4609
+#define        MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_OFST 28
39164610 #define        MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_LBN 2
39174611 #define        MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_WIDTH 1
4612
+#define        MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_OFST 28
39184613 #define        MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_LBN 3
39194614 #define        MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_WIDTH 1
4615
+#define        MC_CMD_SET_MAC_EXT_IN_CFG_FCS_OFST 28
39204616 #define        MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4
39214617 #define        MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1
39224618 
....@@ -3943,6 +4639,7 @@
39434639  * Returns: 0, ETIME
39444640  */
39454641 #define MC_CMD_PHY_STATS 0x2d
4642
+#undef MC_CMD_0x2d_PRIVILEGE_CTG
39464643 
39474644 #define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK
39484645 
....@@ -4024,6 +4721,7 @@
40244721  * effect. Returns: 0, ETIME
40254722  */
40264723 #define MC_CMD_MAC_STATS 0x2e
4724
+#undef MC_CMD_0x2e_PRIVILEGE_CTG
40274725 
40284726 #define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
40294727 
....@@ -4036,18 +4734,25 @@
40364734 #define       MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4
40374735 #define       MC_CMD_MAC_STATS_IN_CMD_OFST 8
40384736 #define       MC_CMD_MAC_STATS_IN_CMD_LEN 4
4737
+#define        MC_CMD_MAC_STATS_IN_DMA_OFST 8
40394738 #define        MC_CMD_MAC_STATS_IN_DMA_LBN 0
40404739 #define        MC_CMD_MAC_STATS_IN_DMA_WIDTH 1
4740
+#define        MC_CMD_MAC_STATS_IN_CLEAR_OFST 8
40414741 #define        MC_CMD_MAC_STATS_IN_CLEAR_LBN 1
40424742 #define        MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1
4743
+#define        MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_OFST 8
40434744 #define        MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2
40444745 #define        MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1
4746
+#define        MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_OFST 8
40454747 #define        MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3
40464748 #define        MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1
4749
+#define        MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_OFST 8
40474750 #define        MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4
40484751 #define        MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1
4752
+#define        MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_OFST 8
40494753 #define        MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5
40504754 #define        MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1
4755
+#define        MC_CMD_MAC_STATS_IN_PERIOD_MS_OFST 8
40514756 #define        MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16
40524757 #define        MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16
40534758 /* DMA length. Should be set to MAC_STATS_NUM_STATS * sizeof(uint64_t), as
....@@ -4324,6 +5029,37 @@
43245029 /*            Other enum values, see field(s): */
43255030 /*               MC_CMD_MAC_STATS_V2_OUT_NO_DMA/STATISTICS */
43265031 
5032
+/* MC_CMD_MAC_STATS_V4_OUT_DMA msgresponse */
5033
+#define    MC_CMD_MAC_STATS_V4_OUT_DMA_LEN 0
5034
+
5035
+/* MC_CMD_MAC_STATS_V4_OUT_NO_DMA msgresponse */
5036
+#define    MC_CMD_MAC_STATS_V4_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V4*64))>>3)
5037
+#define       MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_OFST 0
5038
+#define       MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LEN 8
5039
+#define       MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_OFST 0
5040
+#define       MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_OFST 4
5041
+#define       MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V4
5042
+/* enum: Start of V4 stats buffer space */
5043
+#define          MC_CMD_MAC_V4_DMABUF_START 0x79
5044
+/* enum: RXDP counter: Number of packets truncated because scattering was
5045
+ * disabled.
5046
+ */
5047
+#define          MC_CMD_MAC_RXDP_SCATTER_DISABLED_TRUNC 0x79
5048
+/* enum: RXDP counter: Number of times the RXDP head of line blocked waiting
5049
+ * for descriptors. Will be zero unless RXDP_HLB_IDLE capability is set.
5050
+ */
5051
+#define          MC_CMD_MAC_RXDP_HLB_IDLE 0x7a
5052
+/* enum: RXDP counter: Number of times the RXDP timed out while head of line
5053
+ * blocking. Will be zero unless RXDP_HLB_IDLE capability is set.
5054
+ */
5055
+#define          MC_CMD_MAC_RXDP_HLB_TIMEOUT 0x7b
5056
+/* enum: This includes the space at offset 124 which is the final
5057
+ * GENERATION_END in a MAC_STATS_V4 response and otherwise unused.
5058
+ */
5059
+#define          MC_CMD_MAC_NSTATS_V4 0x7d
5060
+/*            Other enum values, see field(s): */
5061
+/*               MC_CMD_MAC_STATS_V3_OUT_NO_DMA/STATISTICS */
5062
+
43275063 
43285064 /***********************************/
43295065 /* MC_CMD_SRIOV
....@@ -4406,12 +5142,15 @@
44065142 /* MC_CMD_MEMCPY_IN msgrequest */
44075143 #define    MC_CMD_MEMCPY_IN_LENMIN 32
44085144 #define    MC_CMD_MEMCPY_IN_LENMAX 224
5145
+#define    MC_CMD_MEMCPY_IN_LENMAX_MCDI2 992
44095146 #define    MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num))
5147
+#define    MC_CMD_MEMCPY_IN_RECORD_NUM(len) (((len)-0)/32)
44105148 /* see MC_CMD_MEMCPY_RECORD_TYPEDEF */
44115149 #define       MC_CMD_MEMCPY_IN_RECORD_OFST 0
44125150 #define       MC_CMD_MEMCPY_IN_RECORD_LEN 32
44135151 #define       MC_CMD_MEMCPY_IN_RECORD_MINNUM 1
44145152 #define       MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7
5153
+#define       MC_CMD_MEMCPY_IN_RECORD_MAXNUM_MCDI2 31
44155154 
44165155 /* MC_CMD_MEMCPY_OUT msgresponse */
44175156 #define    MC_CMD_MEMCPY_OUT_LEN 0
....@@ -4422,6 +5161,7 @@
44225161  * Set a WoL filter.
44235162  */
44245163 #define MC_CMD_WOL_FILTER_SET 0x32
5164
+#undef MC_CMD_0x32_PRIVILEGE_CTG
44255165 
44265166 #define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK
44275167 
....@@ -4518,8 +5258,10 @@
45185258 /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
45195259 #define       MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8
45205260 #define       MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_LEN 4
5261
+#define        MC_CMD_WOL_FILTER_SET_IN_LINK_UP_OFST 8
45215262 #define        MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0
45225263 #define        MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1
5264
+#define        MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_OFST 8
45235265 #define        MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1
45245266 #define        MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1
45255267 
....@@ -4534,6 +5276,7 @@
45345276  * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS
45355277  */
45365278 #define MC_CMD_WOL_FILTER_REMOVE 0x33
5279
+#undef MC_CMD_0x33_PRIVILEGE_CTG
45375280 
45385281 #define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK
45395282 
....@@ -4552,6 +5295,7 @@
45525295  * ENOSYS
45535296  */
45545297 #define MC_CMD_WOL_FILTER_RESET 0x34
5298
+#undef MC_CMD_0x34_PRIVILEGE_CTG
45555299 
45565300 #define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK
45575301 
....@@ -4589,6 +5333,7 @@
45895333  * Locks required: none. Returns: 0
45905334  */
45915335 #define MC_CMD_NVRAM_TYPES 0x36
5336
+#undef MC_CMD_0x36_PRIVILEGE_CTG
45925337 
45935338 #define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN
45945339 
....@@ -4650,6 +5395,7 @@
46505395  * EINVAL (bad type).
46515396  */
46525397 #define MC_CMD_NVRAM_INFO 0x37
5398
+#undef MC_CMD_0x37_PRIVILEGE_CTG
46535399 
46545400 #define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN
46555401 
....@@ -4672,16 +5418,25 @@
46725418 #define       MC_CMD_NVRAM_INFO_OUT_ERASESIZE_LEN 4
46735419 #define       MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12
46745420 #define       MC_CMD_NVRAM_INFO_OUT_FLAGS_LEN 4
5421
+#define        MC_CMD_NVRAM_INFO_OUT_PROTECTED_OFST 12
46755422 #define        MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0
46765423 #define        MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1
5424
+#define        MC_CMD_NVRAM_INFO_OUT_TLV_OFST 12
46775425 #define        MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1
46785426 #define        MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1
5427
+#define        MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_OFST 12
46795428 #define        MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_LBN 2
46805429 #define        MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1
5430
+#define        MC_CMD_NVRAM_INFO_OUT_CRC_OFST 12
5431
+#define        MC_CMD_NVRAM_INFO_OUT_CRC_LBN 3
5432
+#define        MC_CMD_NVRAM_INFO_OUT_CRC_WIDTH 1
5433
+#define        MC_CMD_NVRAM_INFO_OUT_READ_ONLY_OFST 12
46815434 #define        MC_CMD_NVRAM_INFO_OUT_READ_ONLY_LBN 5
46825435 #define        MC_CMD_NVRAM_INFO_OUT_READ_ONLY_WIDTH 1
5436
+#define        MC_CMD_NVRAM_INFO_OUT_CMAC_OFST 12
46835437 #define        MC_CMD_NVRAM_INFO_OUT_CMAC_LBN 6
46845438 #define        MC_CMD_NVRAM_INFO_OUT_CMAC_WIDTH 1
5439
+#define        MC_CMD_NVRAM_INFO_OUT_A_B_OFST 12
46855440 #define        MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7
46865441 #define        MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1
46875442 #define       MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16
....@@ -4701,14 +5456,19 @@
47015456 #define       MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_LEN 4
47025457 #define       MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_OFST 12
47035458 #define       MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_LEN 4
5459
+#define        MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_OFST 12
47045460 #define        MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0
47055461 #define        MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 1
5462
+#define        MC_CMD_NVRAM_INFO_V2_OUT_TLV_OFST 12
47065463 #define        MC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 1
47075464 #define        MC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 1
5465
+#define        MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_OFST 12
47085466 #define        MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_LBN 2
47095467 #define        MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1
5468
+#define        MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_OFST 12
47105469 #define        MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_LBN 5
47115470 #define        MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_WIDTH 1
5471
+#define        MC_CMD_NVRAM_INFO_V2_OUT_A_B_OFST 12
47125472 #define        MC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 7
47135473 #define        MC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 1
47145474 #define       MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_OFST 16
....@@ -4732,6 +5492,7 @@
47325492  * EPERM.
47335493  */
47345494 #define MC_CMD_NVRAM_UPDATE_START 0x38
5495
+#undef MC_CMD_0x38_PRIVILEGE_CTG
47355496 
47365497 #define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN
47375498 
....@@ -4756,6 +5517,7 @@
47565517 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
47575518 #define       MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_OFST 4
47585519 #define       MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_LEN 4
5520
+#define        MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_OFST 4
47595521 #define        MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0
47605522 #define        MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1
47615523 
....@@ -4770,6 +5532,7 @@
47705532  * PHY_LOCK required and not held)
47715533  */
47725534 #define MC_CMD_NVRAM_READ 0x39
5535
+#undef MC_CMD_0x39_PRIVILEGE_CTG
47735536 
47745537 #define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN
47755538 
....@@ -4823,11 +5586,14 @@
48235586 /* MC_CMD_NVRAM_READ_OUT msgresponse */
48245587 #define    MC_CMD_NVRAM_READ_OUT_LENMIN 1
48255588 #define    MC_CMD_NVRAM_READ_OUT_LENMAX 252
5589
+#define    MC_CMD_NVRAM_READ_OUT_LENMAX_MCDI2 1020
48265590 #define    MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num))
5591
+#define    MC_CMD_NVRAM_READ_OUT_READ_BUFFER_NUM(len) (((len)-0)/1)
48275592 #define       MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0
48285593 #define       MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1
48295594 #define       MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1
48305595 #define       MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252
5596
+#define       MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM_MCDI2 1020
48315597 
48325598 
48335599 /***********************************/
....@@ -4837,13 +5603,16 @@
48375603  * PHY_LOCK required and not held)
48385604  */
48395605 #define MC_CMD_NVRAM_WRITE 0x3a
5606
+#undef MC_CMD_0x3a_PRIVILEGE_CTG
48405607 
48415608 #define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
48425609 
48435610 /* MC_CMD_NVRAM_WRITE_IN msgrequest */
48445611 #define    MC_CMD_NVRAM_WRITE_IN_LENMIN 13
48455612 #define    MC_CMD_NVRAM_WRITE_IN_LENMAX 252
5613
+#define    MC_CMD_NVRAM_WRITE_IN_LENMAX_MCDI2 1020
48465614 #define    MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num))
5615
+#define    MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_NUM(len) (((len)-12)/1)
48475616 #define       MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0
48485617 #define       MC_CMD_NVRAM_WRITE_IN_TYPE_LEN 4
48495618 /*            Enum values, see field(s): */
....@@ -4856,6 +5625,7 @@
48565625 #define       MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1
48575626 #define       MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1
48585627 #define       MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240
5628
+#define       MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM_MCDI2 1008
48595629 
48605630 /* MC_CMD_NVRAM_WRITE_OUT msgresponse */
48615631 #define    MC_CMD_NVRAM_WRITE_OUT_LEN 0
....@@ -4868,6 +5638,7 @@
48685638  * PHY_LOCK required and not held)
48695639  */
48705640 #define MC_CMD_NVRAM_ERASE 0x3b
5641
+#undef MC_CMD_0x3b_PRIVILEGE_CTG
48715642 
48725643 #define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
48735644 
....@@ -4897,6 +5668,7 @@
48975668  * the error EPERM.
48985669  */
48995670 #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c
5671
+#undef MC_CMD_0x3c_PRIVILEGE_CTG
49005672 
49015673 #define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
49025674 
....@@ -4925,8 +5697,15 @@
49255697 #define       MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_LEN 4
49265698 #define       MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_OFST 8
49275699 #define       MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_LEN 4
5700
+#define        MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_OFST 8
49285701 #define        MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0
49295702 #define        MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1
5703
+#define        MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_OFST 8
5704
+#define        MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_LBN 1
5705
+#define        MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_WIDTH 1
5706
+#define        MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_OFST 8
5707
+#define        MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_LBN 2
5708
+#define        MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_WIDTH 1
49305709 
49315710 /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse: Legacy NVRAM_UPDATE_FINISH
49325711  * response. Use NVRAM_UPDATE_FINISH_V2_OUT in new code
....@@ -4949,7 +5728,10 @@
49495728  * has completed.
49505729  */
49515730 #define    MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_LEN 4
4952
-/* Result of nvram update completion processing */
5731
+/* Result of nvram update completion processing. Result codes that indicate an
5732
+ * internal build failure and therefore not expected to be seen by customers in
5733
+ * the field are marked with a prefix 'Internal-error'.
5734
+ */
49535735 #define       MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_OFST 0
49545736 #define       MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_LEN 4
49555737 /* enum: Invalid return code; only non-zero values are defined. Defined as
....@@ -4988,6 +5770,51 @@
49885770 #define          MC_CMD_NVRAM_VERIFY_RC_REJECT_TEST_SIGNED 0xc
49895771 /* enum: The image has a lower security level than the current firmware. */
49905772 #define          MC_CMD_NVRAM_VERIFY_RC_SECURITY_LEVEL_DOWNGRADE 0xd
5773
+/* enum: Internal-error. The signed image is missing the 'contents' section,
5774
+ * where the 'contents' section holds the actual image payload to be applied.
5775
+ */
5776
+#define          MC_CMD_NVRAM_VERIFY_RC_CONTENT_NOT_FOUND 0xe
5777
+/* enum: Internal-error. The bundle header is invalid. */
5778
+#define          MC_CMD_NVRAM_VERIFY_RC_BUNDLE_CONTENT_HEADER_INVALID 0xf
5779
+/* enum: Internal-error. The bundle does not have a valid reflash image layout.
5780
+ */
5781
+#define          MC_CMD_NVRAM_VERIFY_RC_BUNDLE_REFLASH_IMAGE_INVALID 0x10
5782
+/* enum: Internal-error. The bundle has an inconsistent layout of components or
5783
+ * incorrect checksum.
5784
+ */
5785
+#define          MC_CMD_NVRAM_VERIFY_RC_BUNDLE_IMAGE_LAYOUT_INVALID 0x11
5786
+/* enum: Internal-error. The bundle manifest is inconsistent with components in
5787
+ * the bundle.
5788
+ */
5789
+#define          MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_INVALID 0x12
5790
+/* enum: Internal-error. The number of components in a bundle do not match the
5791
+ * number of components advertised by the bundle manifest.
5792
+ */
5793
+#define          MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_NUM_COMPONENTS_MISMATCH 0x13
5794
+/* enum: Internal-error. The bundle contains too many components for the MC
5795
+ * firmware to process
5796
+ */
5797
+#define          MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_TOO_MANY_COMPONENTS 0x14
5798
+/* enum: Internal-error. The bundle manifest has an invalid/inconsistent
5799
+ * component.
5800
+ */
5801
+#define          MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_INVALID 0x15
5802
+/* enum: Internal-error. The hash of a component does not match the hash stored
5803
+ * in the bundle manifest.
5804
+ */
5805
+#define          MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_MISMATCH 0x16
5806
+/* enum: Internal-error. Component hash calculation failed. */
5807
+#define          MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_FAILED 0x17
5808
+/* enum: Internal-error. The component does not have a valid reflash image
5809
+ * layout.
5810
+ */
5811
+#define          MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_REFLASH_IMAGE_INVALID 0x18
5812
+/* enum: The bundle processing code failed to copy a component to its target
5813
+ * partition.
5814
+ */
5815
+#define          MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_COPY_FAILED 0x19
5816
+/* enum: The update operation is in-progress. */
5817
+#define          MC_CMD_NVRAM_VERIFY_RC_PENDING 0x1a
49915818 
49925819 
49935820 /***********************************/
....@@ -5009,6 +5836,7 @@
50095836  * DATALEN=0
50105837  */
50115838 #define MC_CMD_REBOOT 0x3d
5839
+#undef MC_CMD_0x3d_PRIVILEGE_CTG
50125840 
50135841 #define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN
50145842 
....@@ -5029,6 +5857,7 @@
50295857  * thread address.
50305858  */
50315859 #define MC_CMD_SCHEDINFO 0x3e
5860
+#undef MC_CMD_0x3e_PRIVILEGE_CTG
50325861 
50335862 #define MC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN
50345863 
....@@ -5038,11 +5867,14 @@
50385867 /* MC_CMD_SCHEDINFO_OUT msgresponse */
50395868 #define    MC_CMD_SCHEDINFO_OUT_LENMIN 4
50405869 #define    MC_CMD_SCHEDINFO_OUT_LENMAX 252
5870
+#define    MC_CMD_SCHEDINFO_OUT_LENMAX_MCDI2 1020
50415871 #define    MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num))
5872
+#define    MC_CMD_SCHEDINFO_OUT_DATA_NUM(len) (((len)-0)/4)
50425873 #define       MC_CMD_SCHEDINFO_OUT_DATA_OFST 0
50435874 #define       MC_CMD_SCHEDINFO_OUT_DATA_LEN 4
50445875 #define       MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1
50455876 #define       MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63
5877
+#define       MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM_MCDI2 255
50465878 
50475879 
50485880 /***********************************/
....@@ -5051,6 +5883,7 @@
50515883  * mode to the specified value. Returns the old mode.
50525884  */
50535885 #define MC_CMD_REBOOT_MODE 0x3f
5886
+#undef MC_CMD_0x3f_PRIVILEGE_CTG
50545887 
50555888 #define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_INSECURE
50565889 
....@@ -5066,6 +5899,7 @@
50665899 #define          MC_CMD_REBOOT_MODE_SNAPPER 0x3
50675900 /* enum: snapper fake POR */
50685901 #define          MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4
5902
+#define        MC_CMD_REBOOT_MODE_IN_FAKE_OFST 0
50695903 #define        MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7
50705904 #define        MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1
50715905 
....@@ -5107,6 +5941,7 @@
51075941  * Locks required: None Returns: 0
51085942  */
51095943 #define MC_CMD_SENSOR_INFO 0x41
5944
+#undef MC_CMD_0x41_PRIVILEGE_CTG
51105945 
51115946 #define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_GENERAL
51125947 
....@@ -5124,10 +5959,29 @@
51245959 #define       MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0
51255960 #define       MC_CMD_SENSOR_INFO_EXT_IN_PAGE_LEN 4
51265961 
5962
+/* MC_CMD_SENSOR_INFO_EXT_IN_V2 msgrequest */
5963
+#define    MC_CMD_SENSOR_INFO_EXT_IN_V2_LEN 8
5964
+/* Which page of sensors to report.
5965
+ *
5966
+ * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit).
5967
+ *
5968
+ * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc.
5969
+ */
5970
+#define       MC_CMD_SENSOR_INFO_EXT_IN_V2_PAGE_OFST 0
5971
+#define       MC_CMD_SENSOR_INFO_EXT_IN_V2_PAGE_LEN 4
5972
+/* Flags controlling information retrieved */
5973
+#define       MC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_OFST 4
5974
+#define       MC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_LEN 4
5975
+#define        MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_OFST 4
5976
+#define        MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_LBN 0
5977
+#define        MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_WIDTH 1
5978
+
51275979 /* MC_CMD_SENSOR_INFO_OUT msgresponse */
51285980 #define    MC_CMD_SENSOR_INFO_OUT_LENMIN 4
51295981 #define    MC_CMD_SENSOR_INFO_OUT_LENMAX 252
5982
+#define    MC_CMD_SENSOR_INFO_OUT_LENMAX_MCDI2 1020
51305983 #define    MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num))
5984
+#define    MC_CMD_SENSOR_INFO_OUT_MC_CMD_SENSOR_ENTRY_NUM(len) (((len)-4)/8)
51315985 #define       MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0
51325986 #define       MC_CMD_SENSOR_INFO_OUT_MASK_LEN 4
51335987 /* enum: Controller temperature: degC */
....@@ -5304,6 +6158,22 @@
53046158 #define          MC_CMD_SENSOR_IN_1V3 0x55
53056159 /* enum: 1.3v power current: mA */
53066160 #define          MC_CMD_SENSOR_IN_I1V3 0x56
6161
+/* enum: Engineering sensor 1 */
6162
+#define          MC_CMD_SENSOR_ENGINEERING_1 0x57
6163
+/* enum: Engineering sensor 2 */
6164
+#define          MC_CMD_SENSOR_ENGINEERING_2 0x58
6165
+/* enum: Engineering sensor 3 */
6166
+#define          MC_CMD_SENSOR_ENGINEERING_3 0x59
6167
+/* enum: Engineering sensor 4 */
6168
+#define          MC_CMD_SENSOR_ENGINEERING_4 0x5a
6169
+/* enum: Engineering sensor 5 */
6170
+#define          MC_CMD_SENSOR_ENGINEERING_5 0x5b
6171
+/* enum: Engineering sensor 6 */
6172
+#define          MC_CMD_SENSOR_ENGINEERING_6 0x5c
6173
+/* enum: Engineering sensor 7 */
6174
+#define          MC_CMD_SENSOR_ENGINEERING_7 0x5d
6175
+/* enum: Engineering sensor 8 */
6176
+#define          MC_CMD_SENSOR_ENGINEERING_8 0x5e
53076177 /* enum: Not a sensor: reserved for the next page flag */
53086178 #define          MC_CMD_SENSOR_PAGE2_NEXT 0x5f
53096179 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */
....@@ -5313,15 +6183,19 @@
53136183 #define       MC_CMD_SENSOR_ENTRY_HI_OFST 8
53146184 #define       MC_CMD_SENSOR_ENTRY_MINNUM 0
53156185 #define       MC_CMD_SENSOR_ENTRY_MAXNUM 31
6186
+#define       MC_CMD_SENSOR_ENTRY_MAXNUM_MCDI2 127
53166187 
53176188 /* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */
53186189 #define    MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4
53196190 #define    MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252
6191
+#define    MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX_MCDI2 1020
53206192 #define    MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num))
6193
+#define    MC_CMD_SENSOR_INFO_EXT_OUT_MC_CMD_SENSOR_ENTRY_NUM(len) (((len)-4)/8)
53216194 #define       MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0
53226195 #define       MC_CMD_SENSOR_INFO_EXT_OUT_MASK_LEN 4
53236196 /*            Enum values, see field(s): */
53246197 /*               MC_CMD_SENSOR_INFO_OUT */
6198
+#define        MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_OFST 0
53256199 #define        MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31
53266200 #define        MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1
53276201 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */
....@@ -5331,6 +6205,7 @@
53316205 /*            MC_CMD_SENSOR_ENTRY_HI_OFST 8 */
53326206 /*            MC_CMD_SENSOR_ENTRY_MINNUM 0 */
53336207 /*            MC_CMD_SENSOR_ENTRY_MAXNUM 31 */
6208
+/*            MC_CMD_SENSOR_ENTRY_MAXNUM_MCDI2 127 */
53346209 
53356210 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */
53366211 #define    MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8
....@@ -5370,12 +6245,17 @@
53706245  * STATE_WARNING. Otherwise the board should not be expected to function.
53716246  */
53726247 #define MC_CMD_READ_SENSORS 0x42
6248
+#undef MC_CMD_0x42_PRIVILEGE_CTG
53736249 
53746250 #define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_GENERAL
53756251 
53766252 /* MC_CMD_READ_SENSORS_IN msgrequest */
53776253 #define    MC_CMD_READ_SENSORS_IN_LEN 8
5378
-/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */
6254
+/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
6255
+ *
6256
+ * If the address is 0xffffffffffffffff send the readings in the response (used
6257
+ * by cmdclient).
6258
+ */
53796259 #define       MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0
53806260 #define       MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8
53816261 #define       MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0
....@@ -5383,7 +6263,11 @@
53836263 
53846264 /* MC_CMD_READ_SENSORS_EXT_IN msgrequest */
53856265 #define    MC_CMD_READ_SENSORS_EXT_IN_LEN 12
5386
-/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */
6266
+/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
6267
+ *
6268
+ * If the address is 0xffffffffffffffff send the readings in the response (used
6269
+ * by cmdclient).
6270
+ */
53876271 #define       MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0
53886272 #define       MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8
53896273 #define       MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0
....@@ -5391,6 +6275,27 @@
53916275 /* Size in bytes of host buffer. */
53926276 #define       MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8
53936277 #define       MC_CMD_READ_SENSORS_EXT_IN_LENGTH_LEN 4
6278
+
6279
+/* MC_CMD_READ_SENSORS_EXT_IN_V2 msgrequest */
6280
+#define    MC_CMD_READ_SENSORS_EXT_IN_V2_LEN 16
6281
+/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
6282
+ *
6283
+ * If the address is 0xffffffffffffffff send the readings in the response (used
6284
+ * by cmdclient).
6285
+ */
6286
+#define       MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_OFST 0
6287
+#define       MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LEN 8
6288
+#define       MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_OFST 0
6289
+#define       MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_OFST 4
6290
+/* Size in bytes of host buffer. */
6291
+#define       MC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_OFST 8
6292
+#define       MC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_LEN 4
6293
+/* Flags controlling information retrieved */
6294
+#define       MC_CMD_READ_SENSORS_EXT_IN_V2_FLAGS_OFST 12
6295
+#define       MC_CMD_READ_SENSORS_EXT_IN_V2_FLAGS_LEN 4
6296
+#define        MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_OFST 12
6297
+#define        MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_LBN 0
6298
+#define        MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_WIDTH 1
53946299 
53956300 /* MC_CMD_READ_SENSORS_OUT msgresponse */
53966301 #define    MC_CMD_READ_SENSORS_OUT_LEN 0
....@@ -5435,6 +6340,7 @@
54356340  * code: 0
54366341  */
54376342 #define MC_CMD_GET_PHY_STATE 0x43
6343
+#undef MC_CMD_0x43_PRIVILEGE_CTG
54386344 
54396345 #define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL
54406346 
....@@ -5472,6 +6378,7 @@
54726378  * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS
54736379  */
54746380 #define MC_CMD_WOL_FILTER_GET 0x45
6381
+#undef MC_CMD_0x45_PRIVILEGE_CTG
54756382 
54766383 #define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK
54776384 
....@@ -5490,13 +6397,16 @@
54906397  * Returns: 0, ENOSYS
54916398  */
54926399 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46
6400
+#undef MC_CMD_0x46_PRIVILEGE_CTG
54936401 
54946402 #define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK
54956403 
54966404 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */
54976405 #define    MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8
54986406 #define    MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252
6407
+#define    MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX_MCDI2 1020
54996408 #define    MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num))
6409
+#define    MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_NUM(len) (((len)-4)/4)
55006410 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
55016411 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4
55026412 #define          MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */
....@@ -5505,6 +6415,7 @@
55056415 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4
55066416 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1
55076417 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62
6418
+#define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM_MCDI2 254
55086419 
55096420 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */
55106421 #define    MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14
....@@ -5538,6 +6449,7 @@
55386449  * None. Returns: 0, ENOSYS
55396450  */
55406451 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47
6452
+#undef MC_CMD_0x47_PRIVILEGE_CTG
55416453 
55426454 #define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK
55436455 
....@@ -5572,6 +6484,7 @@
55726484  * required: None Returns: 0
55736485  */
55746486 #define MC_CMD_TESTASSERT 0x49
6487
+#undef MC_CMD_0x49_PRIVILEGE_CTG
55756488 
55766489 #define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN
55776490 
....@@ -5614,6 +6527,7 @@
56146527  * basis. Locks required: None. Returns: 0, EINVAL .
56156528  */
56166529 #define MC_CMD_WORKAROUND 0x4a
6530
+#undef MC_CMD_0x4a_PRIVILEGE_CTG
56176531 
56186532 #define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
56196533 
....@@ -5661,6 +6575,7 @@
56616575 #define    MC_CMD_WORKAROUND_EXT_OUT_LEN 4
56626576 #define       MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0
56636577 #define       MC_CMD_WORKAROUND_EXT_OUT_FLAGS_LEN 4
6578
+#define        MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_OFST 0
56646579 #define        MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0
56656580 #define        MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1
56666581 
....@@ -5675,6 +6590,7 @@
56756590  * Anything else: currently undefined. Locks required: None. Return code: 0.
56766591  */
56776592 #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b
6593
+#undef MC_CMD_0x4b_PRIVILEGE_CTG
56786594 
56796595 #define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
56806596 
....@@ -5686,7 +6602,9 @@
56866602 /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */
56876603 #define    MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5
56886604 #define    MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252
6605
+#define    MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX_MCDI2 1020
56896606 #define    MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num))
6607
+#define    MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_NUM(len) (((len)-4)/1)
56906608 /* in bytes */
56916609 #define       MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0
56926610 #define       MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_LEN 4
....@@ -5694,6 +6612,7 @@
56946612 #define       MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1
56956613 #define       MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1
56966614 #define       MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248
6615
+#define       MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM_MCDI2 1016
56976616 
56986617 
56996618 /***********************************/
....@@ -5702,6 +6621,7 @@
57026621  * on the type of partition).
57036622  */
57046623 #define MC_CMD_NVRAM_TEST 0x4c
6624
+#undef MC_CMD_0x4c_PRIVILEGE_CTG
57056625 
57066626 #define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
57076627 
....@@ -5774,6 +6694,7 @@
57746694  * of range.
57756695  */
57766696 #define MC_CMD_SENSOR_SET_LIMS 0x4e
6697
+#undef MC_CMD_0x4e_PRIVILEGE_CTG
57776698 
57786699 #define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_INSECURE
57796700 
....@@ -5826,6 +6747,7 @@
58266747  * none. Returns: 0, EINVAL (bad type).
58276748  */
58286749 #define MC_CMD_NVRAM_PARTITIONS 0x51
6750
+#undef MC_CMD_0x51_PRIVILEGE_CTG
58296751 
58306752 #define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN
58316753 
....@@ -5835,7 +6757,9 @@
58356757 /* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */
58366758 #define    MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4
58376759 #define    MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252
6760
+#define    MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX_MCDI2 1020
58386761 #define    MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num))
6762
+#define    MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_NUM(len) (((len)-4)/4)
58396763 /* total number of partitions */
58406764 #define       MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0
58416765 #define       MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_LEN 4
....@@ -5844,6 +6768,7 @@
58446768 #define       MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4
58456769 #define       MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0
58466770 #define       MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62
6771
+#define       MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM_MCDI2 254
58476772 
58486773 
58496774 /***********************************/
....@@ -5852,6 +6777,7 @@
58526777  * none. Returns: 0, EINVAL (bad type).
58536778  */
58546779 #define MC_CMD_NVRAM_METADATA 0x52
6780
+#undef MC_CMD_0x52_PRIVILEGE_CTG
58556781 
58566782 #define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN
58576783 
....@@ -5864,16 +6790,21 @@
58646790 /* MC_CMD_NVRAM_METADATA_OUT msgresponse */
58656791 #define    MC_CMD_NVRAM_METADATA_OUT_LENMIN 20
58666792 #define    MC_CMD_NVRAM_METADATA_OUT_LENMAX 252
6793
+#define    MC_CMD_NVRAM_METADATA_OUT_LENMAX_MCDI2 1020
58676794 #define    MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num))
6795
+#define    MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_NUM(len) (((len)-20)/1)
58686796 /* Partition type ID code */
58696797 #define       MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0
58706798 #define       MC_CMD_NVRAM_METADATA_OUT_TYPE_LEN 4
58716799 #define       MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4
58726800 #define       MC_CMD_NVRAM_METADATA_OUT_FLAGS_LEN 4
6801
+#define        MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_OFST 4
58736802 #define        MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0
58746803 #define        MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1
6804
+#define        MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_OFST 4
58756805 #define        MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1
58766806 #define        MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1
6807
+#define        MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_OFST 4
58776808 #define        MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2
58786809 #define        MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1
58796810 /* Subtype ID code for content of this partition */
....@@ -5896,6 +6827,7 @@
58966827 #define       MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1
58976828 #define       MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0
58986829 #define       MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232
6830
+#define       MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM_MCDI2 1000
58996831 
59006832 
59016833 /***********************************/
....@@ -5903,6 +6835,7 @@
59036835  * Returns the base MAC, count and stride for the requesting function
59046836  */
59056837 #define MC_CMD_GET_MAC_ADDRESSES 0x55
6838
+#undef MC_CMD_0x55_PRIVILEGE_CTG
59066839 
59076840 #define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL
59086841 
....@@ -5927,9 +6860,13 @@
59276860 
59286861 /***********************************/
59296862 /* MC_CMD_CLP
5930
- * Perform a CLP related operation
6863
+ * Perform a CLP related operation, see SF-110495-PS for details of CLP
6864
+ * processing. This command has been extended to accomodate the requirements of
6865
+ * different manufacturers which are to be found in SF-119187-TC, SF-119186-TC,
6866
+ * SF-120509-TC and SF-117282-PS.
59316867  */
59326868 #define MC_CMD_CLP 0x56
6869
+#undef MC_CMD_0x56_PRIVILEGE_CTG
59336870 
59346871 #define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN
59356872 
....@@ -5964,7 +6901,10 @@
59646901 #define    MC_CMD_CLP_IN_SET_MAC_LEN 12
59656902 /*            MC_CMD_CLP_IN_OP_OFST 0 */
59666903 /*            MC_CMD_CLP_IN_OP_LEN 4 */
5967
-/* MAC address assigned to port */
6904
+/* The MAC address assigned to port. A zero MAC address of 00:00:00:00:00:00
6905
+ * restores the permanent (factory-programmed) MAC address associated with the
6906
+ * port. A non-zero MAC address persists until a PCIe reset or a power cycle.
6907
+ */
59686908 #define       MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4
59696909 #define       MC_CMD_CLP_IN_SET_MAC_ADDR_LEN 6
59706910 /* Padding */
....@@ -5974,10 +6914,39 @@
59746914 /* MC_CMD_CLP_OUT_SET_MAC msgresponse */
59756915 #define    MC_CMD_CLP_OUT_SET_MAC_LEN 0
59766916 
6917
+/* MC_CMD_CLP_IN_SET_MAC_V2 msgrequest */
6918
+#define    MC_CMD_CLP_IN_SET_MAC_V2_LEN 16
6919
+/*            MC_CMD_CLP_IN_OP_OFST 0 */
6920
+/*            MC_CMD_CLP_IN_OP_LEN 4 */
6921
+/* The MAC address assigned to port. A zero MAC address of 00:00:00:00:00:00
6922
+ * restores the permanent (factory-programmed) MAC address associated with the
6923
+ * port. A non-zero MAC address persists until a PCIe reset or a power cycle.
6924
+ */
6925
+#define       MC_CMD_CLP_IN_SET_MAC_V2_ADDR_OFST 4
6926
+#define       MC_CMD_CLP_IN_SET_MAC_V2_ADDR_LEN 6
6927
+/* Padding */
6928
+#define       MC_CMD_CLP_IN_SET_MAC_V2_RESERVED_OFST 10
6929
+#define       MC_CMD_CLP_IN_SET_MAC_V2_RESERVED_LEN 2
6930
+#define       MC_CMD_CLP_IN_SET_MAC_V2_FLAGS_OFST 12
6931
+#define       MC_CMD_CLP_IN_SET_MAC_V2_FLAGS_LEN 4
6932
+#define        MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_OFST 12
6933
+#define        MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_LBN 0
6934
+#define        MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_WIDTH 1
6935
+
59776936 /* MC_CMD_CLP_IN_GET_MAC msgrequest */
59786937 #define    MC_CMD_CLP_IN_GET_MAC_LEN 4
59796938 /*            MC_CMD_CLP_IN_OP_OFST 0 */
59806939 /*            MC_CMD_CLP_IN_OP_LEN 4 */
6940
+
6941
+/* MC_CMD_CLP_IN_GET_MAC_V2 msgrequest */
6942
+#define    MC_CMD_CLP_IN_GET_MAC_V2_LEN 8
6943
+/*            MC_CMD_CLP_IN_OP_OFST 0 */
6944
+/*            MC_CMD_CLP_IN_OP_LEN 4 */
6945
+#define       MC_CMD_CLP_IN_GET_MAC_V2_FLAGS_OFST 4
6946
+#define       MC_CMD_CLP_IN_GET_MAC_V2_FLAGS_LEN 4
6947
+#define        MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_OFST 4
6948
+#define        MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_LBN 0
6949
+#define        MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_WIDTH 1
59816950 
59826951 /* MC_CMD_CLP_OUT_GET_MAC msgresponse */
59836952 #define    MC_CMD_CLP_OUT_GET_MAC_LEN 8
....@@ -6019,6 +6988,7 @@
60196988  * Perform a MUM operation
60206989  */
60216990 #define MC_CMD_MUM 0x57
6991
+#undef MC_CMD_0x57_PRIVILEGE_CTG
60226992 
60236993 #define MC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_INSECURE
60246994 
....@@ -6026,6 +6996,7 @@
60266996 #define    MC_CMD_MUM_IN_LEN 4
60276997 #define       MC_CMD_MUM_IN_OP_HDR_OFST 0
60286998 #define       MC_CMD_MUM_IN_OP_HDR_LEN 4
6999
+#define        MC_CMD_MUM_IN_OP_OFST 0
60297000 #define        MC_CMD_MUM_IN_OP_LBN 0
60307001 #define        MC_CMD_MUM_IN_OP_WIDTH 8
60317002 /* enum: NULL MCDI command to MUM */
....@@ -6095,7 +7066,9 @@
60957066 /* MC_CMD_MUM_IN_WRITE msgrequest */
60967067 #define    MC_CMD_MUM_IN_WRITE_LENMIN 16
60977068 #define    MC_CMD_MUM_IN_WRITE_LENMAX 252
7069
+#define    MC_CMD_MUM_IN_WRITE_LENMAX_MCDI2 1020
60987070 #define    MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num))
7071
+#define    MC_CMD_MUM_IN_WRITE_BUFFER_NUM(len) (((len)-12)/4)
60997072 /* MUM cmd header */
61007073 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
61017074 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
....@@ -6112,11 +7085,14 @@
61127085 #define       MC_CMD_MUM_IN_WRITE_BUFFER_LEN 4
61137086 #define       MC_CMD_MUM_IN_WRITE_BUFFER_MINNUM 1
61147087 #define       MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM 60
7088
+#define       MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM_MCDI2 252
61157089 
61167090 /* MC_CMD_MUM_IN_RAW_CMD msgrequest */
61177091 #define    MC_CMD_MUM_IN_RAW_CMD_LENMIN 17
61187092 #define    MC_CMD_MUM_IN_RAW_CMD_LENMAX 252
7093
+#define    MC_CMD_MUM_IN_RAW_CMD_LENMAX_MCDI2 1020
61197094 #define    MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num))
7095
+#define    MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_NUM(len) (((len)-16)/1)
61207096 /* MUM cmd header */
61217097 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
61227098 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
....@@ -6134,6 +7110,7 @@
61347110 #define       MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 1
61357111 #define       MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MINNUM 1
61367112 #define       MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM 236
7113
+#define       MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM_MCDI2 1004
61377114 
61387115 /* MC_CMD_MUM_IN_LOG msgrequest */
61397116 #define    MC_CMD_MUM_IN_LOG_LEN 8
....@@ -6161,6 +7138,7 @@
61617138 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
61627139 #define       MC_CMD_MUM_IN_GPIO_HDR_OFST 4
61637140 #define       MC_CMD_MUM_IN_GPIO_HDR_LEN 4
7141
+#define        MC_CMD_MUM_IN_GPIO_OPCODE_OFST 4
61647142 #define        MC_CMD_MUM_IN_GPIO_OPCODE_LBN 0
61657143 #define        MC_CMD_MUM_IN_GPIO_OPCODE_WIDTH 8
61667144 #define          MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */
....@@ -6223,12 +7201,14 @@
62237201 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
62247202 #define       MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4
62257203 #define       MC_CMD_MUM_IN_GPIO_OP_HDR_LEN 4
7204
+#define        MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_OFST 4
62267205 #define        MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_LBN 8
62277206 #define        MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_WIDTH 8
62287207 #define          MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */
62297208 #define          MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */
62307209 #define          MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */
62317210 #define          MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */
7211
+#define        MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_OFST 4
62327212 #define        MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_LBN 16
62337213 #define        MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_WIDTH 8
62347214 
....@@ -6245,6 +7225,7 @@
62457225 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
62467226 #define       MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4
62477227 #define       MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_LEN 4
7228
+#define        MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_OFST 4
62487229 #define        MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_LBN 24
62497230 #define        MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_WIDTH 8
62507231 
....@@ -6254,6 +7235,7 @@
62547235 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
62557236 #define       MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4
62567237 #define       MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_LEN 4
7238
+#define        MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_OFST 4
62577239 #define        MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_LBN 24
62587240 #define        MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_WIDTH 8
62597241 
....@@ -6263,6 +7245,7 @@
62637245 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
62647246 #define       MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4
62657247 #define       MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_LEN 4
7248
+#define        MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_OFST 4
62667249 #define        MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_LBN 24
62677250 #define        MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_WIDTH 8
62687251 
....@@ -6273,8 +7256,10 @@
62737256 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
62747257 #define       MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4
62757258 #define       MC_CMD_MUM_IN_READ_SENSORS_PARAMS_LEN 4
7259
+#define        MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_OFST 4
62767260 #define        MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0
62777261 #define        MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_WIDTH 8
7262
+#define        MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_OFST 4
62787263 #define        MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_LBN 8
62797264 #define        MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_WIDTH 8
62807265 
....@@ -6292,10 +7277,13 @@
62927277 /* Control flags for clock programming */
62937278 #define       MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 8
62947279 #define       MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_LEN 4
7280
+#define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_OFST 8
62957281 #define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0
62967282 #define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1
7283
+#define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_OFST 8
62977284 #define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_LBN 1
62987285 #define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_WIDTH 1
7286
+#define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_OFST 8
62997287 #define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_LBN 2
63007288 #define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_WIDTH 1
63017289 
....@@ -6321,6 +7309,7 @@
63217309 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
63227310 #define       MC_CMD_MUM_IN_QSFP_HDR_OFST 4
63237311 #define       MC_CMD_MUM_IN_QSFP_HDR_LEN 4
7312
+#define        MC_CMD_MUM_IN_QSFP_OPCODE_OFST 4
63247313 #define        MC_CMD_MUM_IN_QSFP_OPCODE_LBN 0
63257314 #define        MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4
63267315 #define          MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */
....@@ -6420,21 +7409,27 @@
64207409 /* MC_CMD_MUM_OUT_RAW_CMD msgresponse */
64217410 #define    MC_CMD_MUM_OUT_RAW_CMD_LENMIN 1
64227411 #define    MC_CMD_MUM_OUT_RAW_CMD_LENMAX 252
7412
+#define    MC_CMD_MUM_OUT_RAW_CMD_LENMAX_MCDI2 1020
64237413 #define    MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num))
7414
+#define    MC_CMD_MUM_OUT_RAW_CMD_DATA_NUM(len) (((len)-0)/1)
64247415 /* returned data */
64257416 #define       MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0
64267417 #define       MC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 1
64277418 #define       MC_CMD_MUM_OUT_RAW_CMD_DATA_MINNUM 1
64287419 #define       MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM 252
7420
+#define       MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM_MCDI2 1020
64297421 
64307422 /* MC_CMD_MUM_OUT_READ msgresponse */
64317423 #define    MC_CMD_MUM_OUT_READ_LENMIN 4
64327424 #define    MC_CMD_MUM_OUT_READ_LENMAX 252
7425
+#define    MC_CMD_MUM_OUT_READ_LENMAX_MCDI2 1020
64337426 #define    MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num))
7427
+#define    MC_CMD_MUM_OUT_READ_BUFFER_NUM(len) (((len)-0)/4)
64347428 #define       MC_CMD_MUM_OUT_READ_BUFFER_OFST 0
64357429 #define       MC_CMD_MUM_OUT_READ_BUFFER_LEN 4
64367430 #define       MC_CMD_MUM_OUT_READ_BUFFER_MINNUM 1
64377431 #define       MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM 63
7432
+#define       MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM_MCDI2 255
64387433 
64397434 /* MC_CMD_MUM_OUT_WRITE msgresponse */
64407435 #define    MC_CMD_MUM_OUT_WRITE_LEN 0
....@@ -6493,15 +7488,21 @@
64937488 /* MC_CMD_MUM_OUT_READ_SENSORS msgresponse */
64947489 #define    MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 4
64957490 #define    MC_CMD_MUM_OUT_READ_SENSORS_LENMAX 252
7491
+#define    MC_CMD_MUM_OUT_READ_SENSORS_LENMAX_MCDI2 1020
64967492 #define    MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num))
7493
+#define    MC_CMD_MUM_OUT_READ_SENSORS_DATA_NUM(len) (((len)-0)/4)
64977494 #define       MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0
64987495 #define       MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4
64997496 #define       MC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 1
65007497 #define       MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM 63
7498
+#define       MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM_MCDI2 255
7499
+#define        MC_CMD_MUM_OUT_READ_SENSORS_READING_OFST 0
65017500 #define        MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0
65027501 #define        MC_CMD_MUM_OUT_READ_SENSORS_READING_WIDTH 16
7502
+#define        MC_CMD_MUM_OUT_READ_SENSORS_STATE_OFST 0
65037503 #define        MC_CMD_MUM_OUT_READ_SENSORS_STATE_LBN 16
65047504 #define        MC_CMD_MUM_OUT_READ_SENSORS_STATE_WIDTH 8
7505
+#define        MC_CMD_MUM_OUT_READ_SENSORS_TYPE_OFST 0
65057506 #define        MC_CMD_MUM_OUT_READ_SENSORS_TYPE_LBN 24
65067507 #define        MC_CMD_MUM_OUT_READ_SENSORS_TYPE_WIDTH 8
65077508 
....@@ -6527,8 +7528,10 @@
65277528 #define       MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_LEN 4
65287529 #define       MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4
65297530 #define       MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_LEN 4
7531
+#define        MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_OFST 4
65307532 #define        MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0
65317533 #define        MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 1
7534
+#define        MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_OFST 4
65327535 #define        MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 1
65337536 #define        MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 1
65347537 
....@@ -6540,7 +7543,9 @@
65407543 /* MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO msgresponse */
65417544 #define    MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMIN 5
65427545 #define    MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX 252
7546
+#define    MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX_MCDI2 1020
65437547 #define    MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num))
7548
+#define    MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_NUM(len) (((len)-4)/1)
65447549 /* in bytes */
65457550 #define       MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0
65467551 #define       MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_LEN 4
....@@ -6548,6 +7553,7 @@
65487553 #define       MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 1
65497554 #define       MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 1
65507555 #define       MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM 248
7556
+#define       MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM_MCDI2 1016
65517557 
65527558 /* MC_CMD_MUM_OUT_QSFP_FILL_STATS msgresponse */
65537559 #define    MC_CMD_MUM_OUT_QSFP_FILL_STATS_LEN 8
....@@ -6564,12 +7570,16 @@
65647570 /* MC_CMD_MUM_OUT_READ_DDR_INFO msgresponse */
65657571 #define    MC_CMD_MUM_OUT_READ_DDR_INFO_LENMIN 24
65667572 #define    MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX 248
7573
+#define    MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX_MCDI2 1016
65677574 #define    MC_CMD_MUM_OUT_READ_DDR_INFO_LEN(num) (8+8*(num))
7575
+#define    MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_NUM(len) (((len)-8)/8)
65687576 /* Discrete (soldered) DDR resistor strap info */
65697577 #define       MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0
65707578 #define       MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_LEN 4
7579
+#define        MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_OFST 0
65717580 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0
65727581 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_WIDTH 16
7582
+#define        MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_OFST 0
65737583 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_LBN 16
65747584 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_WIDTH 16
65757585 /* Number of SODIMM info records */
....@@ -6582,6 +7592,8 @@
65827592 #define       MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 12
65837593 #define       MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 2
65847594 #define       MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 30
7595
+#define       MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM_MCDI2 126
7596
+#define        MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_OFST 8
65857597 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 0
65867598 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_WIDTH 8
65877599 /* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */
....@@ -6590,10 +7602,13 @@
65907602 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x1
65917603 /* enum: Total number of SODIMM banks */
65927604 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x2
7605
+#define        MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_OFST 8
65937606 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_LBN 8
65947607 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_WIDTH 8
7608
+#define        MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_OFST 8
65957609 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_LBN 16
65967610 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 4
7611
+#define        MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_OFST 8
65977612 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_LBN 20
65987613 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 4
65997614 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */
....@@ -6602,10 +7617,13 @@
66027617 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */
66037618 /* enum: Values 5-15 are reserved for future usage */
66047619 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x4
7620
+#define        MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_OFST 8
66057621 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_LBN 24
66067622 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_WIDTH 8
7623
+#define        MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_OFST 8
66077624 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_LBN 32
66087625 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_WIDTH 16
7626
+#define        MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_OFST 8
66097627 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_LBN 48
66107628 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 4
66117629 /* enum: No module present */
....@@ -6623,14 +7641,314 @@
66237641 /* enum: Modules may or may not be present, but cannot establish contact by I2C
66247642  */
66257643 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x6
7644
+#define        MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_OFST 8
66267645 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_LBN 52
66277646 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_WIDTH 12
66287647 
6629
-/* MC_CMD_RESOURCE_SPECIFIER enum */
6630
-/* enum: Any */
6631
-#define          MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff
6632
-/* enum: None */
6633
-#define          MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe
7648
+/* MC_CMD_DYNAMIC_SENSORS_LIMITS structuredef: Set of sensor limits. This
7649
+ * should match the equivalent structure in the sensor_query SPHINX service.
7650
+ */
7651
+#define    MC_CMD_DYNAMIC_SENSORS_LIMITS_LEN 24
7652
+/* A value below this will trigger a warning event. */
7653
+#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_OFST 0
7654
+#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_LEN 4
7655
+#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_LBN 0
7656
+#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_WIDTH 32
7657
+/* A value below this will trigger a critical event. */
7658
+#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_OFST 4
7659
+#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_LEN 4
7660
+#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_LBN 32
7661
+#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_WIDTH 32
7662
+/* A value below this will shut down the card. */
7663
+#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_OFST 8
7664
+#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_LEN 4
7665
+#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_LBN 64
7666
+#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_WIDTH 32
7667
+/* A value above this will trigger a warning event. */
7668
+#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_OFST 12
7669
+#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_LEN 4
7670
+#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_LBN 96
7671
+#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_WIDTH 32
7672
+/* A value above this will trigger a critical event. */
7673
+#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_OFST 16
7674
+#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_LEN 4
7675
+#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_LBN 128
7676
+#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_WIDTH 32
7677
+/* A value above this will shut down the card. */
7678
+#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_OFST 20
7679
+#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_LEN 4
7680
+#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_LBN 160
7681
+#define       MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_WIDTH 32
7682
+
7683
+/* MC_CMD_DYNAMIC_SENSORS_DESCRIPTION structuredef: Description of a sensor.
7684
+ * This should match the equivalent structure in the sensor_query SPHINX
7685
+ * service.
7686
+ */
7687
+#define    MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LEN 64
7688
+/* The handle used to identify the sensor in calls to
7689
+ * MC_CMD_DYNAMIC_SENSORS_GET_VALUES
7690
+ */
7691
+#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_OFST 0
7692
+#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_LEN 4
7693
+#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_LBN 0
7694
+#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_WIDTH 32
7695
+/* A human-readable name for the sensor (zero terminated string, max 32 bytes)
7696
+ */
7697
+#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_OFST 4
7698
+#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_LEN 32
7699
+#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_LBN 32
7700
+#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_WIDTH 256
7701
+/* The type of the sensor device, and by implication the unit of that the
7702
+ * values will be reported in
7703
+ */
7704
+#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_OFST 36
7705
+#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_LEN 4
7706
+/* enum: A voltage sensor. Unit is mV */
7707
+#define          MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_VOLTAGE 0x0
7708
+/* enum: A current sensor. Unit is mA */
7709
+#define          MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_CURRENT 0x1
7710
+/* enum: A power sensor. Unit is mW */
7711
+#define          MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_POWER 0x2
7712
+/* enum: A temperature sensor. Unit is Celsius */
7713
+#define          MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TEMPERATURE 0x3
7714
+/* enum: A cooling fan sensor. Unit is RPM */
7715
+#define          MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_FAN 0x4
7716
+#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_LBN 288
7717
+#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_WIDTH 32
7718
+/* A single MC_CMD_DYNAMIC_SENSORS_LIMITS structure */
7719
+#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_OFST 40
7720
+#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_LEN 24
7721
+#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_LBN 320
7722
+#define       MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_WIDTH 192
7723
+
7724
+/* MC_CMD_DYNAMIC_SENSORS_READING structuredef: State and value of a sensor.
7725
+ * This should match the equivalent structure in the sensor_query SPHINX
7726
+ * service.
7727
+ */
7728
+#define    MC_CMD_DYNAMIC_SENSORS_READING_LEN 12
7729
+/* The handle used to identify the sensor */
7730
+#define       MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_OFST 0
7731
+#define       MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_LEN 4
7732
+#define       MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_LBN 0
7733
+#define       MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_WIDTH 32
7734
+/* The current value of the sensor */
7735
+#define       MC_CMD_DYNAMIC_SENSORS_READING_VALUE_OFST 4
7736
+#define       MC_CMD_DYNAMIC_SENSORS_READING_VALUE_LEN 4
7737
+#define       MC_CMD_DYNAMIC_SENSORS_READING_VALUE_LBN 32
7738
+#define       MC_CMD_DYNAMIC_SENSORS_READING_VALUE_WIDTH 32
7739
+/* The sensor's condition, e.g. good, broken or removed */
7740
+#define       MC_CMD_DYNAMIC_SENSORS_READING_STATE_OFST 8
7741
+#define       MC_CMD_DYNAMIC_SENSORS_READING_STATE_LEN 4
7742
+/* enum: Sensor working normally within limits */
7743
+#define          MC_CMD_DYNAMIC_SENSORS_READING_OK 0x0
7744
+/* enum: Warning threshold breached */
7745
+#define          MC_CMD_DYNAMIC_SENSORS_READING_WARNING 0x1
7746
+/* enum: Critical threshold breached */
7747
+#define          MC_CMD_DYNAMIC_SENSORS_READING_CRITICAL 0x2
7748
+/* enum: Fatal threshold breached */
7749
+#define          MC_CMD_DYNAMIC_SENSORS_READING_FATAL 0x3
7750
+/* enum: Sensor not working */
7751
+#define          MC_CMD_DYNAMIC_SENSORS_READING_BROKEN 0x4
7752
+/* enum: Sensor working but no reading available */
7753
+#define          MC_CMD_DYNAMIC_SENSORS_READING_NO_READING 0x5
7754
+/* enum: Sensor initialization failed */
7755
+#define          MC_CMD_DYNAMIC_SENSORS_READING_INIT_FAILED 0x6
7756
+#define       MC_CMD_DYNAMIC_SENSORS_READING_STATE_LBN 64
7757
+#define       MC_CMD_DYNAMIC_SENSORS_READING_STATE_WIDTH 32
7758
+
7759
+
7760
+/***********************************/
7761
+/* MC_CMD_DYNAMIC_SENSORS_LIST
7762
+ * Return a complete list of handles for sensors currently managed by the MC,
7763
+ * and a generation count for this version of the sensor table. On systems
7764
+ * advertising the DYNAMIC_SENSORS capability bit, this replaces the
7765
+ * MC_CMD_READ_SENSORS command. On multi-MC systems this may include sensors
7766
+ * added by the NMC.
7767
+ *
7768
+ * Sensor handles are persistent for the lifetime of the sensor and are used to
7769
+ * identify sensors in MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS and
7770
+ * MC_CMD_DYNAMIC_SENSORS_GET_VALUES.
7771
+ *
7772
+ * The generation count is maintained by the MC, is persistent across reboots
7773
+ * and will be incremented each time the sensor table is modified. When the
7774
+ * table is modified, a CODE_DYNAMIC_SENSORS_CHANGE event will be generated
7775
+ * containing the new generation count. The driver should compare this against
7776
+ * the current generation count, and if it is different, call
7777
+ * MC_CMD_DYNAMIC_SENSORS_LIST again to update it's copy of the sensor table.
7778
+ *
7779
+ * The sensor count is provided to allow a future path to supporting more than
7780
+ * MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MAXNUM_MCDI2 sensors, i.e.
7781
+ * the maximum number that will fit in a single response. As this is a fairly
7782
+ * large number (253) it is not anticipated that this will be needed in the
7783
+ * near future, so can currently be ignored.
7784
+ *
7785
+ * On Riverhead this command is implemented as a a wrapper for `list` in the
7786
+ * sensor_query SPHINX service.
7787
+ */
7788
+#define MC_CMD_DYNAMIC_SENSORS_LIST 0x66
7789
+#undef MC_CMD_0x66_PRIVILEGE_CTG
7790
+
7791
+#define MC_CMD_0x66_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7792
+
7793
+/* MC_CMD_DYNAMIC_SENSORS_LIST_IN msgrequest */
7794
+#define    MC_CMD_DYNAMIC_SENSORS_LIST_IN_LEN 0
7795
+
7796
+/* MC_CMD_DYNAMIC_SENSORS_LIST_OUT msgresponse */
7797
+#define    MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMIN 8
7798
+#define    MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMAX 252
7799
+#define    MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMAX_MCDI2 1020
7800
+#define    MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LEN(num) (8+4*(num))
7801
+#define    MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_NUM(len) (((len)-8)/4)
7802
+/* Generation count, which will be updated each time a sensor is added to or
7803
+ * removed from the MC sensor table.
7804
+ */
7805
+#define       MC_CMD_DYNAMIC_SENSORS_LIST_OUT_GENERATION_OFST 0
7806
+#define       MC_CMD_DYNAMIC_SENSORS_LIST_OUT_GENERATION_LEN 4
7807
+/* Number of sensors managed by the MC. Note that in principle, this can be
7808
+ * larger than the size of the HANDLES array.
7809
+ */
7810
+#define       MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_OFST 4
7811
+#define       MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_LEN 4
7812
+/* Array of sensor handles */
7813
+#define       MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_OFST 8
7814
+#define       MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_LEN 4
7815
+#define       MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MINNUM 0
7816
+#define       MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MAXNUM 61
7817
+#define       MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MAXNUM_MCDI2 253
7818
+
7819
+
7820
+/***********************************/
7821
+/* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS
7822
+ * Get descriptions for a set of sensors, specified as an array of sensor
7823
+ * handles as returned by MC_CMD_DYNAMIC_SENSORS_LIST
7824
+ *
7825
+ * Any handles which do not correspond to a sensor currently managed by the MC
7826
+ * will be dropped from from the response. This may happen when a sensor table
7827
+ * update is in progress, and effectively means the set of usable sensors is
7828
+ * the intersection between the sets of sensors known to the driver and the MC.
7829
+ *
7830
+ * On Riverhead this command is implemented as a a wrapper for
7831
+ * `get_descriptions` in the sensor_query SPHINX service.
7832
+ */
7833
+#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS 0x67
7834
+#undef MC_CMD_0x67_PRIVILEGE_CTG
7835
+
7836
+#define MC_CMD_0x67_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7837
+
7838
+/* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN msgrequest */
7839
+#define    MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMIN 0
7840
+#define    MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMAX 252
7841
+#define    MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMAX_MCDI2 1020
7842
+#define    MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LEN(num) (0+4*(num))
7843
+#define    MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_NUM(len) (((len)-0)/4)
7844
+/* Array of sensor handles */
7845
+#define       MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_OFST 0
7846
+#define       MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_LEN 4
7847
+#define       MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MINNUM 0
7848
+#define       MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MAXNUM 63
7849
+#define       MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MAXNUM_MCDI2 255
7850
+
7851
+/* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT msgresponse */
7852
+#define    MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMIN 0
7853
+#define    MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMAX 192
7854
+#define    MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMAX_MCDI2 960
7855
+#define    MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LEN(num) (0+64*(num))
7856
+#define    MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_NUM(len) (((len)-0)/64)
7857
+/* Array of MC_CMD_DYNAMIC_SENSORS_DESCRIPTION structures */
7858
+#define       MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_OFST 0
7859
+#define       MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_LEN 64
7860
+#define       MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MINNUM 0
7861
+#define       MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MAXNUM 3
7862
+#define       MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MAXNUM_MCDI2 15
7863
+
7864
+
7865
+/***********************************/
7866
+/* MC_CMD_DYNAMIC_SENSORS_GET_READINGS
7867
+ * Read the state and value for a set of sensors, specified as an array of
7868
+ * sensor handles as returned by MC_CMD_DYNAMIC_SENSORS_LIST.
7869
+ *
7870
+ * In the case of a broken sensor, then the state of the response's
7871
+ * MC_CMD_DYNAMIC_SENSORS_VALUE entry will be set to BROKEN, and any value
7872
+ * provided should be treated as erroneous.
7873
+ *
7874
+ * Any handles which do not correspond to a sensor currently managed by the MC
7875
+ * will be dropped from from the response. This may happen when a sensor table
7876
+ * update is in progress, and effectively means the set of usable sensors is
7877
+ * the intersection between the sets of sensors known to the driver and the MC.
7878
+ *
7879
+ * On Riverhead this command is implemented as a a wrapper for `get_readings`
7880
+ * in the sensor_query SPHINX service.
7881
+ */
7882
+#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS 0x68
7883
+#undef MC_CMD_0x68_PRIVILEGE_CTG
7884
+
7885
+#define MC_CMD_0x68_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7886
+
7887
+/* MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN msgrequest */
7888
+#define    MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMIN 0
7889
+#define    MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMAX 252
7890
+#define    MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMAX_MCDI2 1020
7891
+#define    MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LEN(num) (0+4*(num))
7892
+#define    MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_NUM(len) (((len)-0)/4)
7893
+/* Array of sensor handles */
7894
+#define       MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_OFST 0
7895
+#define       MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_LEN 4
7896
+#define       MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MINNUM 0
7897
+#define       MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MAXNUM 63
7898
+#define       MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MAXNUM_MCDI2 255
7899
+
7900
+/* MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT msgresponse */
7901
+#define    MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMIN 0
7902
+#define    MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMAX 252
7903
+#define    MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMAX_MCDI2 1020
7904
+#define    MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LEN(num) (0+12*(num))
7905
+#define    MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_NUM(len) (((len)-0)/12)
7906
+/* Array of MC_CMD_DYNAMIC_SENSORS_READING structures */
7907
+#define       MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_OFST 0
7908
+#define       MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_LEN 12
7909
+#define       MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MINNUM 0
7910
+#define       MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MAXNUM 21
7911
+#define       MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MAXNUM_MCDI2 85
7912
+
7913
+
7914
+/***********************************/
7915
+/* MC_CMD_EVENT_CTRL
7916
+ * Configure which categories of unsolicited events the driver expects to
7917
+ * receive (Riverhead).
7918
+ */
7919
+#define MC_CMD_EVENT_CTRL 0x69
7920
+#undef MC_CMD_0x69_PRIVILEGE_CTG
7921
+
7922
+#define MC_CMD_0x69_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7923
+
7924
+/* MC_CMD_EVENT_CTRL_IN msgrequest */
7925
+#define    MC_CMD_EVENT_CTRL_IN_LENMIN 0
7926
+#define    MC_CMD_EVENT_CTRL_IN_LENMAX 252
7927
+#define    MC_CMD_EVENT_CTRL_IN_LENMAX_MCDI2 1020
7928
+#define    MC_CMD_EVENT_CTRL_IN_LEN(num) (0+4*(num))
7929
+#define    MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_NUM(len) (((len)-0)/4)
7930
+/* Array of event categories for which the driver wishes to receive events. */
7931
+#define       MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_OFST 0
7932
+#define       MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_LEN 4
7933
+#define       MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MINNUM 0
7934
+#define       MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MAXNUM 63
7935
+#define       MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MAXNUM_MCDI2 255
7936
+/* enum: Driver wishes to receive LINKCHANGE events. */
7937
+#define          MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_LINKCHANGE 0x0
7938
+/* enum: Driver wishes to receive SENSOR_CHANGE and SENSOR_STATE_CHANGE events.
7939
+ */
7940
+#define          MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_SENSOREVT 0x1
7941
+/* enum: Driver wishes to receive receive errors. */
7942
+#define          MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_RX_ERR 0x2
7943
+/* enum: Driver wishes to receive transmit errors. */
7944
+#define          MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_TX_ERR 0x3
7945
+/* enum: Driver wishes to receive firmware alerts. */
7946
+#define          MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_FWALERT 0x4
7947
+/* enum: Driver wishes to receive reboot events. */
7948
+#define          MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_MC_REBOOT 0x5
7949
+
7950
+/* MC_CMD_EVENT_CTRL_OUT msgrequest */
7951
+#define    MC_CMD_EVENT_CTRL_OUT_LEN 0
66347952 
66357953 /* EVB_PORT_ID structuredef */
66367954 #define    EVB_PORT_ID_LEN 4
....@@ -6784,6 +8102,16 @@
67848102  * subset of the information stored in this partition.
67858103  */
67868104 #define          NVRAM_PARTITION_TYPE_FRU_INFORMATION 0x1d00
8105
+/* enum: Bundle image partition */
8106
+#define          NVRAM_PARTITION_TYPE_BUNDLE 0x1e00
8107
+/* enum: Bundle metadata partition that holds additional information related to
8108
+ * a bundle update in TLV format
8109
+ */
8110
+#define          NVRAM_PARTITION_TYPE_BUNDLE_METADATA 0x1e01
8111
+/* enum: Bundle update non-volatile log output partition */
8112
+#define          NVRAM_PARTITION_TYPE_BUNDLE_LOG 0x1e02
8113
+/* enum: Partition for Solarflare gPXE bootrom installed via Bundle update. */
8114
+#define          NVRAM_PARTITION_TYPE_EXPANSION_ROM_INTERNAL 0x1e03
67878115 /* enum: Start of reserved value range (firmware may use for any purpose) */
67888116 #define          NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00
67898117 /* enum: End of reserved value range (firmware may use for any purpose) */
....@@ -6841,24 +8169,34 @@
68418169 #define       LICENSED_FEATURES_MASK_LEN 8
68428170 #define       LICENSED_FEATURES_MASK_LO_OFST 0
68438171 #define       LICENSED_FEATURES_MASK_HI_OFST 4
8172
+#define        LICENSED_FEATURES_RX_CUT_THROUGH_OFST 0
68448173 #define        LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0
68458174 #define        LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1
8175
+#define        LICENSED_FEATURES_PIO_OFST 0
68468176 #define        LICENSED_FEATURES_PIO_LBN 1
68478177 #define        LICENSED_FEATURES_PIO_WIDTH 1
8178
+#define        LICENSED_FEATURES_EVQ_TIMER_OFST 0
68488179 #define        LICENSED_FEATURES_EVQ_TIMER_LBN 2
68498180 #define        LICENSED_FEATURES_EVQ_TIMER_WIDTH 1
8181
+#define        LICENSED_FEATURES_CLOCK_OFST 0
68508182 #define        LICENSED_FEATURES_CLOCK_LBN 3
68518183 #define        LICENSED_FEATURES_CLOCK_WIDTH 1
8184
+#define        LICENSED_FEATURES_RX_TIMESTAMPS_OFST 0
68528185 #define        LICENSED_FEATURES_RX_TIMESTAMPS_LBN 4
68538186 #define        LICENSED_FEATURES_RX_TIMESTAMPS_WIDTH 1
8187
+#define        LICENSED_FEATURES_TX_TIMESTAMPS_OFST 0
68548188 #define        LICENSED_FEATURES_TX_TIMESTAMPS_LBN 5
68558189 #define        LICENSED_FEATURES_TX_TIMESTAMPS_WIDTH 1
8190
+#define        LICENSED_FEATURES_RX_SNIFF_OFST 0
68568191 #define        LICENSED_FEATURES_RX_SNIFF_LBN 6
68578192 #define        LICENSED_FEATURES_RX_SNIFF_WIDTH 1
8193
+#define        LICENSED_FEATURES_TX_SNIFF_OFST 0
68588194 #define        LICENSED_FEATURES_TX_SNIFF_LBN 7
68598195 #define        LICENSED_FEATURES_TX_SNIFF_WIDTH 1
8196
+#define        LICENSED_FEATURES_PROXY_FILTER_OPS_OFST 0
68608197 #define        LICENSED_FEATURES_PROXY_FILTER_OPS_LBN 8
68618198 #define        LICENSED_FEATURES_PROXY_FILTER_OPS_WIDTH 1
8199
+#define        LICENSED_FEATURES_EVENT_CUT_THROUGH_OFST 0
68628200 #define        LICENSED_FEATURES_EVENT_CUT_THROUGH_LBN 9
68638201 #define        LICENSED_FEATURES_EVENT_CUT_THROUGH_WIDTH 1
68648202 #define       LICENSED_FEATURES_MASK_LBN 0
....@@ -6871,36 +8209,52 @@
68718209 #define       LICENSED_V3_APPS_MASK_LEN 8
68728210 #define       LICENSED_V3_APPS_MASK_LO_OFST 0
68738211 #define       LICENSED_V3_APPS_MASK_HI_OFST 4
8212
+#define        LICENSED_V3_APPS_ONLOAD_OFST 0
68748213 #define        LICENSED_V3_APPS_ONLOAD_LBN 0
68758214 #define        LICENSED_V3_APPS_ONLOAD_WIDTH 1
8215
+#define        LICENSED_V3_APPS_PTP_OFST 0
68768216 #define        LICENSED_V3_APPS_PTP_LBN 1
68778217 #define        LICENSED_V3_APPS_PTP_WIDTH 1
8218
+#define        LICENSED_V3_APPS_SOLARCAPTURE_PRO_OFST 0
68788219 #define        LICENSED_V3_APPS_SOLARCAPTURE_PRO_LBN 2
68798220 #define        LICENSED_V3_APPS_SOLARCAPTURE_PRO_WIDTH 1
8221
+#define        LICENSED_V3_APPS_SOLARSECURE_OFST 0
68808222 #define        LICENSED_V3_APPS_SOLARSECURE_LBN 3
68818223 #define        LICENSED_V3_APPS_SOLARSECURE_WIDTH 1
8224
+#define        LICENSED_V3_APPS_PERF_MONITOR_OFST 0
68828225 #define        LICENSED_V3_APPS_PERF_MONITOR_LBN 4
68838226 #define        LICENSED_V3_APPS_PERF_MONITOR_WIDTH 1
8227
+#define        LICENSED_V3_APPS_SOLARCAPTURE_LIVE_OFST 0
68848228 #define        LICENSED_V3_APPS_SOLARCAPTURE_LIVE_LBN 5
68858229 #define        LICENSED_V3_APPS_SOLARCAPTURE_LIVE_WIDTH 1
8230
+#define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_OFST 0
68868231 #define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_LBN 6
68878232 #define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_WIDTH 1
8233
+#define        LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_OFST 0
68888234 #define        LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_LBN 7
68898235 #define        LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_WIDTH 1
8236
+#define        LICENSED_V3_APPS_TCP_DIRECT_OFST 0
68908237 #define        LICENSED_V3_APPS_TCP_DIRECT_LBN 8
68918238 #define        LICENSED_V3_APPS_TCP_DIRECT_WIDTH 1
8239
+#define        LICENSED_V3_APPS_LOW_LATENCY_OFST 0
68928240 #define        LICENSED_V3_APPS_LOW_LATENCY_LBN 9
68938241 #define        LICENSED_V3_APPS_LOW_LATENCY_WIDTH 1
8242
+#define        LICENSED_V3_APPS_SOLARCAPTURE_TAP_OFST 0
68948243 #define        LICENSED_V3_APPS_SOLARCAPTURE_TAP_LBN 10
68958244 #define        LICENSED_V3_APPS_SOLARCAPTURE_TAP_WIDTH 1
8245
+#define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_OFST 0
68968246 #define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_LBN 11
68978247 #define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_WIDTH 1
8248
+#define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_OFST 0
68988249 #define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_LBN 12
68998250 #define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_WIDTH 1
8251
+#define        LICENSED_V3_APPS_SCALEOUT_ONLOAD_OFST 0
69008252 #define        LICENSED_V3_APPS_SCALEOUT_ONLOAD_LBN 13
69018253 #define        LICENSED_V3_APPS_SCALEOUT_ONLOAD_WIDTH 1
8254
+#define        LICENSED_V3_APPS_DSHBRD_OFST 0
69028255 #define        LICENSED_V3_APPS_DSHBRD_LBN 14
69038256 #define        LICENSED_V3_APPS_DSHBRD_WIDTH 1
8257
+#define        LICENSED_V3_APPS_SCATRD_OFST 0
69048258 #define        LICENSED_V3_APPS_SCATRD_LBN 15
69058259 #define        LICENSED_V3_APPS_SCATRD_WIDTH 1
69068260 #define       LICENSED_V3_APPS_MASK_LBN 0
....@@ -6913,24 +8267,34 @@
69138267 #define       LICENSED_V3_FEATURES_MASK_LEN 8
69148268 #define       LICENSED_V3_FEATURES_MASK_LO_OFST 0
69158269 #define       LICENSED_V3_FEATURES_MASK_HI_OFST 4
8270
+#define        LICENSED_V3_FEATURES_RX_CUT_THROUGH_OFST 0
69168271 #define        LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0
69178272 #define        LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1
8273
+#define        LICENSED_V3_FEATURES_PIO_OFST 0
69188274 #define        LICENSED_V3_FEATURES_PIO_LBN 1
69198275 #define        LICENSED_V3_FEATURES_PIO_WIDTH 1
8276
+#define        LICENSED_V3_FEATURES_EVQ_TIMER_OFST 0
69208277 #define        LICENSED_V3_FEATURES_EVQ_TIMER_LBN 2
69218278 #define        LICENSED_V3_FEATURES_EVQ_TIMER_WIDTH 1
8279
+#define        LICENSED_V3_FEATURES_CLOCK_OFST 0
69228280 #define        LICENSED_V3_FEATURES_CLOCK_LBN 3
69238281 #define        LICENSED_V3_FEATURES_CLOCK_WIDTH 1
8282
+#define        LICENSED_V3_FEATURES_RX_TIMESTAMPS_OFST 0
69248283 #define        LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4
69258284 #define        LICENSED_V3_FEATURES_RX_TIMESTAMPS_WIDTH 1
8285
+#define        LICENSED_V3_FEATURES_TX_TIMESTAMPS_OFST 0
69268286 #define        LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN 5
69278287 #define        LICENSED_V3_FEATURES_TX_TIMESTAMPS_WIDTH 1
8288
+#define        LICENSED_V3_FEATURES_RX_SNIFF_OFST 0
69288289 #define        LICENSED_V3_FEATURES_RX_SNIFF_LBN 6
69298290 #define        LICENSED_V3_FEATURES_RX_SNIFF_WIDTH 1
8291
+#define        LICENSED_V3_FEATURES_TX_SNIFF_OFST 0
69308292 #define        LICENSED_V3_FEATURES_TX_SNIFF_LBN 7
69318293 #define        LICENSED_V3_FEATURES_TX_SNIFF_WIDTH 1
8294
+#define        LICENSED_V3_FEATURES_PROXY_FILTER_OPS_OFST 0
69328295 #define        LICENSED_V3_FEATURES_PROXY_FILTER_OPS_LBN 8
69338296 #define        LICENSED_V3_FEATURES_PROXY_FILTER_OPS_WIDTH 1
8297
+#define        LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_OFST 0
69348298 #define        LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_LBN 9
69358299 #define        LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_WIDTH 1
69368300 #define       LICENSED_V3_FEATURES_MASK_LBN 0
....@@ -6983,12 +8347,16 @@
69838347  */
69848348 #define       RSS_MODE_HASH_SELECTOR_OFST 0
69858349 #define       RSS_MODE_HASH_SELECTOR_LEN 1
8350
+#define        RSS_MODE_HASH_SRC_ADDR_OFST 0
69868351 #define        RSS_MODE_HASH_SRC_ADDR_LBN 0
69878352 #define        RSS_MODE_HASH_SRC_ADDR_WIDTH 1
8353
+#define        RSS_MODE_HASH_DST_ADDR_OFST 0
69888354 #define        RSS_MODE_HASH_DST_ADDR_LBN 1
69898355 #define        RSS_MODE_HASH_DST_ADDR_WIDTH 1
8356
+#define        RSS_MODE_HASH_SRC_PORT_OFST 0
69908357 #define        RSS_MODE_HASH_SRC_PORT_LBN 2
69918358 #define        RSS_MODE_HASH_SRC_PORT_WIDTH 1
8359
+#define        RSS_MODE_HASH_DST_PORT_OFST 0
69928360 #define        RSS_MODE_HASH_DST_PORT_LBN 3
69938361 #define        RSS_MODE_HASH_DST_PORT_WIDTH 1
69948362 #define       RSS_MODE_HASH_SELECTOR_LBN 0
....@@ -7013,6 +8381,7 @@
70138381  * Get a dump of the MCPU registers
70148382  */
70158383 #define MC_CMD_READ_REGS 0x50
8384
+#undef MC_CMD_0x50_PRIVILEGE_CTG
70168385 
70178386 #define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_INSECURE
70188387 
....@@ -7038,13 +8407,16 @@
70388407  * end with an address for each 4k of host memory required to back the EVQ.
70398408  */
70408409 #define MC_CMD_INIT_EVQ 0x80
8410
+#undef MC_CMD_0x80_PRIVILEGE_CTG
70418411 
70428412 #define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL
70438413 
70448414 /* MC_CMD_INIT_EVQ_IN msgrequest */
70458415 #define    MC_CMD_INIT_EVQ_IN_LENMIN 44
70468416 #define    MC_CMD_INIT_EVQ_IN_LENMAX 548
8417
+#define    MC_CMD_INIT_EVQ_IN_LENMAX_MCDI2 548
70478418 #define    MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num))
8419
+#define    MC_CMD_INIT_EVQ_IN_DMA_ADDR_NUM(len) (((len)-36)/8)
70488420 /* Size, in entries */
70498421 #define       MC_CMD_INIT_EVQ_IN_SIZE_OFST 0
70508422 #define       MC_CMD_INIT_EVQ_IN_SIZE_LEN 4
....@@ -7063,18 +8435,25 @@
70638435 /* tbd */
70648436 #define       MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16
70658437 #define       MC_CMD_INIT_EVQ_IN_FLAGS_LEN 4
8438
+#define        MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_OFST 16
70668439 #define        MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0
70678440 #define        MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1
8441
+#define        MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_OFST 16
70688442 #define        MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1
70698443 #define        MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1
8444
+#define        MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_OFST 16
70708445 #define        MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2
70718446 #define        MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1
8447
+#define        MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_OFST 16
70728448 #define        MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3
70738449 #define        MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1
8450
+#define        MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_OFST 16
70748451 #define        MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4
70758452 #define        MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1
8453
+#define        MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_OFST 16
70768454 #define        MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5
70778455 #define        MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1
8456
+#define        MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_OFST 16
70788457 #define        MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_LBN 6
70798458 #define        MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_WIDTH 1
70808459 #define       MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20
....@@ -7117,6 +8496,7 @@
71178496 #define       MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40
71188497 #define       MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1
71198498 #define       MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64
8499
+#define       MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM_MCDI2 64
71208500 
71218501 /* MC_CMD_INIT_EVQ_OUT msgresponse */
71228502 #define    MC_CMD_INIT_EVQ_OUT_LEN 4
....@@ -7127,7 +8507,9 @@
71278507 /* MC_CMD_INIT_EVQ_V2_IN msgrequest */
71288508 #define    MC_CMD_INIT_EVQ_V2_IN_LENMIN 44
71298509 #define    MC_CMD_INIT_EVQ_V2_IN_LENMAX 548
8510
+#define    MC_CMD_INIT_EVQ_V2_IN_LENMAX_MCDI2 548
71308511 #define    MC_CMD_INIT_EVQ_V2_IN_LEN(num) (36+8*(num))
8512
+#define    MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_NUM(len) (((len)-36)/8)
71318513 /* Size, in entries */
71328514 #define       MC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0
71338515 #define       MC_CMD_INIT_EVQ_V2_IN_SIZE_LEN 4
....@@ -7146,20 +8528,28 @@
71468528 /* tbd */
71478529 #define       MC_CMD_INIT_EVQ_V2_IN_FLAGS_OFST 16
71488530 #define       MC_CMD_INIT_EVQ_V2_IN_FLAGS_LEN 4
8531
+#define        MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_OFST 16
71498532 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_LBN 0
71508533 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_WIDTH 1
8534
+#define        MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_OFST 16
71518535 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_LBN 1
71528536 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_WIDTH 1
8537
+#define        MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_OFST 16
71538538 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_LBN 2
71548539 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_WIDTH 1
8540
+#define        MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_OFST 16
71558541 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_LBN 3
71568542 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_WIDTH 1
8543
+#define        MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_OFST 16
71578544 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_LBN 4
71588545 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_WIDTH 1
8546
+#define        MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_OFST 16
71598547 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_LBN 5
71608548 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_WIDTH 1
8549
+#define        MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_OFST 16
71618550 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_LBN 6
71628551 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_WIDTH 1
8552
+#define        MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_OFST 16
71638553 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LBN 7
71648554 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_WIDTH 4
71658555 /* enum: All initialisation flags specified by host. */
....@@ -7181,6 +8571,9 @@
71818571  * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
71828572  */
71838573 #define          MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO 0x3
8574
+#define        MC_CMD_INIT_EVQ_V2_IN_FLAG_EXT_WIDTH_OFST 16
8575
+#define        MC_CMD_INIT_EVQ_V2_IN_FLAG_EXT_WIDTH_LBN 11
8576
+#define        MC_CMD_INIT_EVQ_V2_IN_FLAG_EXT_WIDTH_WIDTH 1
71848577 #define       MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_OFST 20
71858578 #define       MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_LEN 4
71868579 /* enum: Disabled */
....@@ -7221,6 +8614,7 @@
72218614 #define       MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_OFST 40
72228615 #define       MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MINNUM 1
72238616 #define       MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM 64
8617
+#define       MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM_MCDI2 64
72248618 
72258619 /* MC_CMD_INIT_EVQ_V2_OUT msgresponse */
72268620 #define    MC_CMD_INIT_EVQ_V2_OUT_LEN 8
....@@ -7230,12 +8624,16 @@
72308624 /* Actual configuration applied on the card */
72318625 #define       MC_CMD_INIT_EVQ_V2_OUT_FLAGS_OFST 4
72328626 #define       MC_CMD_INIT_EVQ_V2_OUT_FLAGS_LEN 4
8627
+#define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_OFST 4
72338628 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_LBN 0
72348629 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_WIDTH 1
8630
+#define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_OFST 4
72358631 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_LBN 1
72368632 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_WIDTH 1
8633
+#define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_OFST 4
72378634 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_LBN 2
72388635 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_WIDTH 1
8636
+#define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_OFST 4
72398637 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_LBN 3
72408638 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_WIDTH 1
72418639 
....@@ -7266,6 +8664,7 @@
72668664  * the RXQ.
72678665  */
72688666 #define MC_CMD_INIT_RXQ 0x81
8667
+#undef MC_CMD_0x81_PRIVILEGE_CTG
72698668 
72708669 #define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL
72718670 
....@@ -7274,7 +8673,9 @@
72748673  */
72758674 #define    MC_CMD_INIT_RXQ_IN_LENMIN 36
72768675 #define    MC_CMD_INIT_RXQ_IN_LENMAX 252
8676
+#define    MC_CMD_INIT_RXQ_IN_LENMAX_MCDI2 1020
72778677 #define    MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num))
8678
+#define    MC_CMD_INIT_RXQ_IN_DMA_ADDR_NUM(len) (((len)-28)/8)
72788679 /* Size, in entries */
72798680 #define       MC_CMD_INIT_RXQ_IN_SIZE_OFST 0
72808681 #define       MC_CMD_INIT_RXQ_IN_SIZE_LEN 4
....@@ -7293,20 +8694,28 @@
72938694 /* There will be more flags here. */
72948695 #define       MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16
72958696 #define       MC_CMD_INIT_RXQ_IN_FLAGS_LEN 4
8697
+#define        MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_OFST 16
72968698 #define        MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0
72978699 #define        MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1
8700
+#define        MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_OFST 16
72988701 #define        MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1
72998702 #define        MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1
8703
+#define        MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_OFST 16
73008704 #define        MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2
73018705 #define        MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1
8706
+#define        MC_CMD_INIT_RXQ_IN_CRC_MODE_OFST 16
73028707 #define        MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3
73038708 #define        MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4
8709
+#define        MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_OFST 16
73048710 #define        MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7
73058711 #define        MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1
8712
+#define        MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_OFST 16
73068713 #define        MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8
73078714 #define        MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1
8715
+#define        MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_OFST 16
73088716 #define        MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9
73098717 #define        MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1
8718
+#define        MC_CMD_INIT_RXQ_IN_UNUSED_OFST 16
73108719 #define        MC_CMD_INIT_RXQ_IN_UNUSED_LBN 10
73118720 #define        MC_CMD_INIT_RXQ_IN_UNUSED_WIDTH 1
73128721 /* Owner ID to use if in buffer mode (zero if physical) */
....@@ -7322,6 +8731,7 @@
73228731 #define       MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32
73238732 #define       MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1
73248733 #define       MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28
8734
+#define       MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM_MCDI2 124
73258735 
73268736 /* MC_CMD_INIT_RXQ_EXT_IN msgrequest: Extended RXQ_INIT with additional mode
73278737  * flags
....@@ -7336,7 +8746,7 @@
73368746 #define       MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4
73378747 #define       MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_LEN 4
73388748 /* The value to put in the event data. Check hardware spec. for valid range.
7339
- * This field is ignored if DMA_MODE == EQUAL_STRIDE_PACKED_STREAM or DMA_MODE
8749
+ * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE
73408750  * == PACKED_STREAM.
73418751  */
73428752 #define       MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8
....@@ -7349,20 +8759,28 @@
73498759 /* There will be more flags here. */
73508760 #define       MC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 16
73518761 #define       MC_CMD_INIT_RXQ_EXT_IN_FLAGS_LEN 4
8762
+#define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_OFST 16
73528763 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0
73538764 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1
8765
+#define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_OFST 16
73548766 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1
73558767 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 1
8768
+#define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_OFST 16
73568769 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_LBN 2
73578770 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1
8771
+#define        MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_OFST 16
73588772 #define        MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_LBN 3
73598773 #define        MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4
8774
+#define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_OFST 16
73608775 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_LBN 7
73618776 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 1
8777
+#define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_OFST 16
73628778 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_LBN 8
73638779 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 1
8780
+#define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_OFST 16
73648781 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_LBN 9
73658782 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 1
8783
+#define        MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_OFST 16
73668784 #define        MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 10
73678785 #define        MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4
73688786 /* enum: One packet per descriptor (for normal networking) */
....@@ -7375,9 +8793,13 @@
73758793  * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
73768794  * firmware.
73778795  */
8796
+#define          MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
8797
+/* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */
73788798 #define          MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
8799
+#define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_OFST 16
73798800 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14
73808801 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
8802
+#define        MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_OFST 16
73818803 #define        MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15
73828804 #define        MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3
73838805 #define          MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */
....@@ -7385,10 +8807,15 @@
73858807 #define          MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */
73868808 #define          MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */
73878809 #define          MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */
8810
+#define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_OFST 16
73888811 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 18
73898812 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
8813
+#define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_OFST 16
73908814 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_LBN 19
73918815 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
8816
+#define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_OFST 16
8817
+#define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_LBN 20
8818
+#define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_WIDTH 1
73928819 /* Owner ID to use if in buffer mode (zero if physical) */
73938820 #define       MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20
73948821 #define       MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_LEN 4
....@@ -7416,7 +8843,7 @@
74168843 #define       MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_OFST 4
74178844 #define       MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_LEN 4
74188845 /* The value to put in the event data. Check hardware spec. for valid range.
7419
- * This field is ignored if DMA_MODE == EQUAL_STRIDE_PACKED_STREAM or DMA_MODE
8846
+ * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE
74208847  * == PACKED_STREAM.
74218848  */
74228849 #define       MC_CMD_INIT_RXQ_V3_IN_LABEL_OFST 8
....@@ -7429,20 +8856,28 @@
74298856 /* There will be more flags here. */
74308857 #define       MC_CMD_INIT_RXQ_V3_IN_FLAGS_OFST 16
74318858 #define       MC_CMD_INIT_RXQ_V3_IN_FLAGS_LEN 4
8859
+#define        MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_OFST 16
74328860 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_LBN 0
74338861 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_WIDTH 1
8862
+#define        MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_OFST 16
74348863 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_LBN 1
74358864 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_WIDTH 1
8865
+#define        MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_OFST 16
74368866 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_LBN 2
74378867 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_WIDTH 1
8868
+#define        MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_OFST 16
74388869 #define        MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_LBN 3
74398870 #define        MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_WIDTH 4
8871
+#define        MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_OFST 16
74408872 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_LBN 7
74418873 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_WIDTH 1
8874
+#define        MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_OFST 16
74428875 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_LBN 8
74438876 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_WIDTH 1
8877
+#define        MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_OFST 16
74448878 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_LBN 9
74458879 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_WIDTH 1
8880
+#define        MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_OFST 16
74468881 #define        MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_LBN 10
74478882 #define        MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_WIDTH 4
74488883 /* enum: One packet per descriptor (for normal networking) */
....@@ -7455,9 +8890,13 @@
74558890  * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
74568891  * firmware.
74578892  */
8893
+#define          MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
8894
+/* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */
74588895 #define          MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
8896
+#define        MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_OFST 16
74598897 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_LBN 14
74608898 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
8899
+#define        MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_OFST 16
74618900 #define        MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_LBN 15
74628901 #define        MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3
74638902 #define          MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_1M 0x0 /* enum */
....@@ -7465,10 +8904,15 @@
74658904 #define          MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_256K 0x2 /* enum */
74668905 #define          MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_128K 0x3 /* enum */
74678906 #define          MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_64K 0x4 /* enum */
8907
+#define        MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_OFST 16
74688908 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_LBN 18
74698909 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
8910
+#define        MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_OFST 16
74708911 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_LBN 19
74718912 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
8913
+#define        MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_OFST 16
8914
+#define        MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_LBN 20
8915
+#define        MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_WIDTH 1
74728916 /* Owner ID to use if in buffer mode (zero if physical) */
74738917 #define       MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_OFST 20
74748918 #define       MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_LEN 4
....@@ -7485,21 +8929,21 @@
74858929 #define       MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_OFST 540
74868930 #define       MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_LEN 4
74878931 /* The number of packet buffers that will be contained within each
7488
- * EQUAL_STRIDE_PACKED_STREAM format bucket supplied by the driver. This field
7489
- * is ignored unless DMA_MODE == EQUAL_STRIDE_PACKED_STREAM.
8932
+ * EQUAL_STRIDE_SUPER_BUFFER format bucket supplied by the driver. This field
8933
+ * is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
74908934  */
74918935 #define       MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 544
74928936 #define       MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
74938937 /* The length in bytes of the area in each packet buffer that can be written to
74948938  * by the adapter. This is used to store the packet prefix and the packet
74958939  * payload. This length does not include any end padding added by the driver.
7496
- * This field is ignored unless DMA_MODE == EQUAL_STRIDE_PACKED_STREAM.
8940
+ * This field is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
74978941  */
74988942 #define       MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_OFST 548
74998943 #define       MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_LEN 4
75008944 /* The length in bytes of a single packet buffer within a
7501
- * EQUAL_STRIDE_PACKED_STREAM format bucket. This field is ignored unless
7502
- * DMA_MODE == EQUAL_STRIDE_PACKED_STREAM.
8945
+ * EQUAL_STRIDE_SUPER_BUFFER format bucket. This field is ignored unless
8946
+ * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
75038947  */
75048948 #define       MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_OFST 552
75058949 #define       MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_LEN 4
....@@ -7507,10 +8951,295 @@
75078951  * there are no RX descriptors available. If the timeout is reached and there
75088952  * are still no descriptors then the packet will be dropped. A timeout of 0
75098953  * means the datapath will never be blocked. This field is ignored unless
7510
- * DMA_MODE == EQUAL_STRIDE_PACKED_STREAM.
8954
+ * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
75118955  */
75128956 #define       MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 556
75138957 #define       MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
8958
+
8959
+/* MC_CMD_INIT_RXQ_V4_IN msgrequest: INIT_RXQ request with new field required
8960
+ * for systems with a QDMA (currently, Riverhead)
8961
+ */
8962
+#define    MC_CMD_INIT_RXQ_V4_IN_LEN 564
8963
+/* Size, in entries */
8964
+#define       MC_CMD_INIT_RXQ_V4_IN_SIZE_OFST 0
8965
+#define       MC_CMD_INIT_RXQ_V4_IN_SIZE_LEN 4
8966
+/* The EVQ to send events to. This is an index originally specified to
8967
+ * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.
8968
+ */
8969
+#define       MC_CMD_INIT_RXQ_V4_IN_TARGET_EVQ_OFST 4
8970
+#define       MC_CMD_INIT_RXQ_V4_IN_TARGET_EVQ_LEN 4
8971
+/* The value to put in the event data. Check hardware spec. for valid range.
8972
+ * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE
8973
+ * == PACKED_STREAM.
8974
+ */
8975
+#define       MC_CMD_INIT_RXQ_V4_IN_LABEL_OFST 8
8976
+#define       MC_CMD_INIT_RXQ_V4_IN_LABEL_LEN 4
8977
+/* Desired instance. Must be set to a specific instance, which is a function
8978
+ * local queue index.
8979
+ */
8980
+#define       MC_CMD_INIT_RXQ_V4_IN_INSTANCE_OFST 12
8981
+#define       MC_CMD_INIT_RXQ_V4_IN_INSTANCE_LEN 4
8982
+/* There will be more flags here. */
8983
+#define       MC_CMD_INIT_RXQ_V4_IN_FLAGS_OFST 16
8984
+#define       MC_CMD_INIT_RXQ_V4_IN_FLAGS_LEN 4
8985
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_OFST 16
8986
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_LBN 0
8987
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_WIDTH 1
8988
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_OFST 16
8989
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_LBN 1
8990
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_WIDTH 1
8991
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_TIMESTAMP_OFST 16
8992
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_TIMESTAMP_LBN 2
8993
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_TIMESTAMP_WIDTH 1
8994
+#define        MC_CMD_INIT_RXQ_V4_IN_CRC_MODE_OFST 16
8995
+#define        MC_CMD_INIT_RXQ_V4_IN_CRC_MODE_LBN 3
8996
+#define        MC_CMD_INIT_RXQ_V4_IN_CRC_MODE_WIDTH 4
8997
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_CHAIN_OFST 16
8998
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_CHAIN_LBN 7
8999
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_CHAIN_WIDTH 1
9000
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_PREFIX_OFST 16
9001
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_PREFIX_LBN 8
9002
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_PREFIX_WIDTH 1
9003
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_DISABLE_SCATTER_OFST 16
9004
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_DISABLE_SCATTER_LBN 9
9005
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_DISABLE_SCATTER_WIDTH 1
9006
+#define        MC_CMD_INIT_RXQ_V4_IN_DMA_MODE_OFST 16
9007
+#define        MC_CMD_INIT_RXQ_V4_IN_DMA_MODE_LBN 10
9008
+#define        MC_CMD_INIT_RXQ_V4_IN_DMA_MODE_WIDTH 4
9009
+/* enum: One packet per descriptor (for normal networking) */
9010
+#define          MC_CMD_INIT_RXQ_V4_IN_SINGLE_PACKET 0x0
9011
+/* enum: Pack multiple packets into large descriptors (for SolarCapture) */
9012
+#define          MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM 0x1
9013
+/* enum: Pack multiple packets into large descriptors using the format designed
9014
+ * to maximise packet rate. This mode uses 1 "bucket" per descriptor with
9015
+ * multiple fixed-size packet buffers within each bucket. For a full
9016
+ * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
9017
+ * firmware.
9018
+ */
9019
+#define          MC_CMD_INIT_RXQ_V4_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
9020
+/* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */
9021
+#define          MC_CMD_INIT_RXQ_V4_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
9022
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_SNAPSHOT_MODE_OFST 16
9023
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_SNAPSHOT_MODE_LBN 14
9024
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
9025
+#define        MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM_BUFF_SIZE_OFST 16
9026
+#define        MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM_BUFF_SIZE_LBN 15
9027
+#define        MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3
9028
+#define          MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_1M 0x0 /* enum */
9029
+#define          MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_512K 0x1 /* enum */
9030
+#define          MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_256K 0x2 /* enum */
9031
+#define          MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_128K 0x3 /* enum */
9032
+#define          MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_64K 0x4 /* enum */
9033
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_WANT_OUTER_CLASSES_OFST 16
9034
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_WANT_OUTER_CLASSES_LBN 18
9035
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
9036
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_FORCE_EV_MERGING_OFST 16
9037
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_FORCE_EV_MERGING_LBN 19
9038
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
9039
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_OFST 16
9040
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_LBN 20
9041
+#define        MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_WIDTH 1
9042
+/* Owner ID to use if in buffer mode (zero if physical) */
9043
+#define       MC_CMD_INIT_RXQ_V4_IN_OWNER_ID_OFST 20
9044
+#define       MC_CMD_INIT_RXQ_V4_IN_OWNER_ID_LEN 4
9045
+/* The port ID associated with the v-adaptor which should contain this DMAQ. */
9046
+#define       MC_CMD_INIT_RXQ_V4_IN_PORT_ID_OFST 24
9047
+#define       MC_CMD_INIT_RXQ_V4_IN_PORT_ID_LEN 4
9048
+/* 64-bit address of 4k of 4k-aligned host memory buffer */
9049
+#define       MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_OFST 28
9050
+#define       MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LEN 8
9051
+#define       MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_OFST 28
9052
+#define       MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_OFST 32
9053
+#define       MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_NUM 64
9054
+/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
9055
+#define       MC_CMD_INIT_RXQ_V4_IN_SNAPSHOT_LENGTH_OFST 540
9056
+#define       MC_CMD_INIT_RXQ_V4_IN_SNAPSHOT_LENGTH_LEN 4
9057
+/* The number of packet buffers that will be contained within each
9058
+ * EQUAL_STRIDE_SUPER_BUFFER format bucket supplied by the driver. This field
9059
+ * is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
9060
+ */
9061
+#define       MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 544
9062
+#define       MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
9063
+/* The length in bytes of the area in each packet buffer that can be written to
9064
+ * by the adapter. This is used to store the packet prefix and the packet
9065
+ * payload. This length does not include any end padding added by the driver.
9066
+ * This field is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
9067
+ */
9068
+#define       MC_CMD_INIT_RXQ_V4_IN_ES_MAX_DMA_LEN_OFST 548
9069
+#define       MC_CMD_INIT_RXQ_V4_IN_ES_MAX_DMA_LEN_LEN 4
9070
+/* The length in bytes of a single packet buffer within a
9071
+ * EQUAL_STRIDE_SUPER_BUFFER format bucket. This field is ignored unless
9072
+ * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
9073
+ */
9074
+#define       MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_STRIDE_OFST 552
9075
+#define       MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_STRIDE_LEN 4
9076
+/* The maximum time in nanoseconds that the datapath will be backpressured if
9077
+ * there are no RX descriptors available. If the timeout is reached and there
9078
+ * are still no descriptors then the packet will be dropped. A timeout of 0
9079
+ * means the datapath will never be blocked. This field is ignored unless
9080
+ * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
9081
+ */
9082
+#define       MC_CMD_INIT_RXQ_V4_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 556
9083
+#define       MC_CMD_INIT_RXQ_V4_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
9084
+/* V4 message data */
9085
+#define       MC_CMD_INIT_RXQ_V4_IN_V4_DATA_OFST 560
9086
+#define       MC_CMD_INIT_RXQ_V4_IN_V4_DATA_LEN 4
9087
+/* Size in bytes of buffers attached to descriptors posted to this queue. Set
9088
+ * to zero if using this message on non-QDMA based platforms. Currently in
9089
+ * Riverhead there is a global limit of eight different buffer sizes across all
9090
+ * active queues. A 2KB and 4KB buffer is guaranteed to be available, but a
9091
+ * request for a different buffer size will fail if there are already eight
9092
+ * other buffer sizes in use. In future Riverhead this limit will go away and
9093
+ * any size will be accepted.
9094
+ */
9095
+#define       MC_CMD_INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES_OFST 560
9096
+#define       MC_CMD_INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES_LEN 4
9097
+
9098
+/* MC_CMD_INIT_RXQ_V5_IN msgrequest: INIT_RXQ request with ability to request a
9099
+ * different RX packet prefix
9100
+ */
9101
+#define    MC_CMD_INIT_RXQ_V5_IN_LEN 568
9102
+/* Size, in entries */
9103
+#define       MC_CMD_INIT_RXQ_V5_IN_SIZE_OFST 0
9104
+#define       MC_CMD_INIT_RXQ_V5_IN_SIZE_LEN 4
9105
+/* The EVQ to send events to. This is an index originally specified to
9106
+ * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.
9107
+ */
9108
+#define       MC_CMD_INIT_RXQ_V5_IN_TARGET_EVQ_OFST 4
9109
+#define       MC_CMD_INIT_RXQ_V5_IN_TARGET_EVQ_LEN 4
9110
+/* The value to put in the event data. Check hardware spec. for valid range.
9111
+ * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE
9112
+ * == PACKED_STREAM.
9113
+ */
9114
+#define       MC_CMD_INIT_RXQ_V5_IN_LABEL_OFST 8
9115
+#define       MC_CMD_INIT_RXQ_V5_IN_LABEL_LEN 4
9116
+/* Desired instance. Must be set to a specific instance, which is a function
9117
+ * local queue index.
9118
+ */
9119
+#define       MC_CMD_INIT_RXQ_V5_IN_INSTANCE_OFST 12
9120
+#define       MC_CMD_INIT_RXQ_V5_IN_INSTANCE_LEN 4
9121
+/* There will be more flags here. */
9122
+#define       MC_CMD_INIT_RXQ_V5_IN_FLAGS_OFST 16
9123
+#define       MC_CMD_INIT_RXQ_V5_IN_FLAGS_LEN 4
9124
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_OFST 16
9125
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_LBN 0
9126
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_WIDTH 1
9127
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_OFST 16
9128
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_LBN 1
9129
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_WIDTH 1
9130
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_OFST 16
9131
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_LBN 2
9132
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_WIDTH 1
9133
+#define        MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_OFST 16
9134
+#define        MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_LBN 3
9135
+#define        MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_WIDTH 4
9136
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_OFST 16
9137
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_LBN 7
9138
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_WIDTH 1
9139
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_OFST 16
9140
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_LBN 8
9141
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_WIDTH 1
9142
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_OFST 16
9143
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_LBN 9
9144
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_WIDTH 1
9145
+#define        MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_OFST 16
9146
+#define        MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_LBN 10
9147
+#define        MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_WIDTH 4
9148
+/* enum: One packet per descriptor (for normal networking) */
9149
+#define          MC_CMD_INIT_RXQ_V5_IN_SINGLE_PACKET 0x0
9150
+/* enum: Pack multiple packets into large descriptors (for SolarCapture) */
9151
+#define          MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM 0x1
9152
+/* enum: Pack multiple packets into large descriptors using the format designed
9153
+ * to maximise packet rate. This mode uses 1 "bucket" per descriptor with
9154
+ * multiple fixed-size packet buffers within each bucket. For a full
9155
+ * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
9156
+ * firmware.
9157
+ */
9158
+#define          MC_CMD_INIT_RXQ_V5_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
9159
+/* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */
9160
+#define          MC_CMD_INIT_RXQ_V5_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
9161
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_OFST 16
9162
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_LBN 14
9163
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
9164
+#define        MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM_BUFF_SIZE_OFST 16
9165
+#define        MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM_BUFF_SIZE_LBN 15
9166
+#define        MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3
9167
+#define          MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_1M 0x0 /* enum */
9168
+#define          MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_512K 0x1 /* enum */
9169
+#define          MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_256K 0x2 /* enum */
9170
+#define          MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_128K 0x3 /* enum */
9171
+#define          MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_64K 0x4 /* enum */
9172
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_OFST 16
9173
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_LBN 18
9174
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
9175
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_OFST 16
9176
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_LBN 19
9177
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
9178
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_OFST 16
9179
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_LBN 20
9180
+#define        MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_WIDTH 1
9181
+/* Owner ID to use if in buffer mode (zero if physical) */
9182
+#define       MC_CMD_INIT_RXQ_V5_IN_OWNER_ID_OFST 20
9183
+#define       MC_CMD_INIT_RXQ_V5_IN_OWNER_ID_LEN 4
9184
+/* The port ID associated with the v-adaptor which should contain this DMAQ. */
9185
+#define       MC_CMD_INIT_RXQ_V5_IN_PORT_ID_OFST 24
9186
+#define       MC_CMD_INIT_RXQ_V5_IN_PORT_ID_LEN 4
9187
+/* 64-bit address of 4k of 4k-aligned host memory buffer */
9188
+#define       MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_OFST 28
9189
+#define       MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LEN 8
9190
+#define       MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_OFST 28
9191
+#define       MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_OFST 32
9192
+#define       MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_NUM 64
9193
+/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
9194
+#define       MC_CMD_INIT_RXQ_V5_IN_SNAPSHOT_LENGTH_OFST 540
9195
+#define       MC_CMD_INIT_RXQ_V5_IN_SNAPSHOT_LENGTH_LEN 4
9196
+/* The number of packet buffers that will be contained within each
9197
+ * EQUAL_STRIDE_SUPER_BUFFER format bucket supplied by the driver. This field
9198
+ * is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
9199
+ */
9200
+#define       MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 544
9201
+#define       MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
9202
+/* The length in bytes of the area in each packet buffer that can be written to
9203
+ * by the adapter. This is used to store the packet prefix and the packet
9204
+ * payload. This length does not include any end padding added by the driver.
9205
+ * This field is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
9206
+ */
9207
+#define       MC_CMD_INIT_RXQ_V5_IN_ES_MAX_DMA_LEN_OFST 548
9208
+#define       MC_CMD_INIT_RXQ_V5_IN_ES_MAX_DMA_LEN_LEN 4
9209
+/* The length in bytes of a single packet buffer within a
9210
+ * EQUAL_STRIDE_SUPER_BUFFER format bucket. This field is ignored unless
9211
+ * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
9212
+ */
9213
+#define       MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_STRIDE_OFST 552
9214
+#define       MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_STRIDE_LEN 4
9215
+/* The maximum time in nanoseconds that the datapath will be backpressured if
9216
+ * there are no RX descriptors available. If the timeout is reached and there
9217
+ * are still no descriptors then the packet will be dropped. A timeout of 0
9218
+ * means the datapath will never be blocked. This field is ignored unless
9219
+ * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
9220
+ */
9221
+#define       MC_CMD_INIT_RXQ_V5_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 556
9222
+#define       MC_CMD_INIT_RXQ_V5_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
9223
+/* V4 message data */
9224
+#define       MC_CMD_INIT_RXQ_V5_IN_V4_DATA_OFST 560
9225
+#define       MC_CMD_INIT_RXQ_V5_IN_V4_DATA_LEN 4
9226
+/* Size in bytes of buffers attached to descriptors posted to this queue. Set
9227
+ * to zero if using this message on non-QDMA based platforms. Currently in
9228
+ * Riverhead there is a global limit of eight different buffer sizes across all
9229
+ * active queues. A 2KB and 4KB buffer is guaranteed to be available, but a
9230
+ * request for a different buffer size will fail if there are already eight
9231
+ * other buffer sizes in use. In future Riverhead this limit will go away and
9232
+ * any size will be accepted.
9233
+ */
9234
+#define       MC_CMD_INIT_RXQ_V5_IN_BUFFER_SIZE_BYTES_OFST 560
9235
+#define       MC_CMD_INIT_RXQ_V5_IN_BUFFER_SIZE_BYTES_LEN 4
9236
+/* Prefix id for the RX prefix format to use on packets delivered this queue.
9237
+ * Zero is always a valid prefix id and means the default prefix format
9238
+ * documented for the platform. Other prefix ids can be obtained by calling
9239
+ * MC_CMD_GET_RX_PREFIX_ID with a requested set of prefix fields.
9240
+ */
9241
+#define       MC_CMD_INIT_RXQ_V5_IN_RX_PREFIX_ID_OFST 564
9242
+#define       MC_CMD_INIT_RXQ_V5_IN_RX_PREFIX_ID_LEN 4
75149243 
75159244 /* MC_CMD_INIT_RXQ_OUT msgresponse */
75169245 #define    MC_CMD_INIT_RXQ_OUT_LEN 0
....@@ -7521,11 +9250,18 @@
75219250 /* MC_CMD_INIT_RXQ_V3_OUT msgresponse */
75229251 #define    MC_CMD_INIT_RXQ_V3_OUT_LEN 0
75239252 
9253
+/* MC_CMD_INIT_RXQ_V4_OUT msgresponse */
9254
+#define    MC_CMD_INIT_RXQ_V4_OUT_LEN 0
9255
+
9256
+/* MC_CMD_INIT_RXQ_V5_OUT msgresponse */
9257
+#define    MC_CMD_INIT_RXQ_V5_OUT_LEN 0
9258
+
75249259 
75259260 /***********************************/
75269261 /* MC_CMD_INIT_TXQ
75279262  */
75289263 #define MC_CMD_INIT_TXQ 0x82
9264
+#undef MC_CMD_0x82_PRIVILEGE_CTG
75299265 
75309266 #define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL
75319267 
....@@ -7534,7 +9270,9 @@
75349270  */
75359271 #define    MC_CMD_INIT_TXQ_IN_LENMIN 36
75369272 #define    MC_CMD_INIT_TXQ_IN_LENMAX 252
9273
+#define    MC_CMD_INIT_TXQ_IN_LENMAX_MCDI2 1020
75379274 #define    MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num))
9275
+#define    MC_CMD_INIT_TXQ_IN_DMA_ADDR_NUM(len) (((len)-28)/8)
75389276 /* Size, in entries */
75399277 #define       MC_CMD_INIT_TXQ_IN_SIZE_OFST 0
75409278 #define       MC_CMD_INIT_TXQ_IN_SIZE_LEN 4
....@@ -7554,22 +9292,31 @@
75549292 /* There will be more flags here. */
75559293 #define       MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16
75569294 #define       MC_CMD_INIT_TXQ_IN_FLAGS_LEN 4
9295
+#define        MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_OFST 16
75579296 #define        MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0
75589297 #define        MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1
9298
+#define        MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_OFST 16
75599299 #define        MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1
75609300 #define        MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1
9301
+#define        MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_OFST 16
75619302 #define        MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2
75629303 #define        MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1
9304
+#define        MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_OFST 16
75639305 #define        MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3
75649306 #define        MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1
9307
+#define        MC_CMD_INIT_TXQ_IN_CRC_MODE_OFST 16
75659308 #define        MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4
75669309 #define        MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4
9310
+#define        MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_OFST 16
75679311 #define        MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8
75689312 #define        MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1
9313
+#define        MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_OFST 16
75699314 #define        MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9
75709315 #define        MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1
9316
+#define        MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_OFST 16
75719317 #define        MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_LBN 10
75729318 #define        MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1
9319
+#define        MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_OFST 16
75739320 #define        MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11
75749321 #define        MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1
75759322 /* Owner ID to use if in buffer mode (zero if physical) */
....@@ -7585,6 +9332,7 @@
75859332 #define       MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32
75869333 #define       MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1
75879334 #define       MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28
9335
+#define       MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM_MCDI2 124
75889336 
75899337 /* MC_CMD_INIT_TXQ_EXT_IN msgrequest: Extended INIT_TXQ with additional mode
75909338  * flags
....@@ -7609,30 +9357,48 @@
76099357 /* There will be more flags here. */
76109358 #define       MC_CMD_INIT_TXQ_EXT_IN_FLAGS_OFST 16
76119359 #define       MC_CMD_INIT_TXQ_EXT_IN_FLAGS_LEN 4
9360
+#define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_OFST 16
76129361 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0
76139362 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1
9363
+#define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_OFST 16
76149364 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 1
76159365 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 1
9366
+#define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_OFST 16
76169367 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_LBN 2
76179368 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 1
9369
+#define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_OFST 16
76189370 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_LBN 3
76199371 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 1
9372
+#define        MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_OFST 16
76209373 #define        MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4
76219374 #define        MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4
9375
+#define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_OFST 16
76229376 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_LBN 8
76239377 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1
9378
+#define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_OFST 16
76249379 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_LBN 9
76259380 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 1
9381
+#define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_OFST 16
76269382 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_LBN 10
76279383 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1
9384
+#define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_OFST 16
76289385 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11
76299386 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1
9387
+#define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_OFST 16
76309388 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_LBN 12
76319389 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_WIDTH 1
9390
+#define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_OFST 16
76329391 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_LBN 13
76339392 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_WIDTH 1
9393
+#define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_OFST 16
76349394 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_LBN 14
76359395 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_WIDTH 1
9396
+#define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_M2M_D2C_OFST 16
9397
+#define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_M2M_D2C_LBN 15
9398
+#define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_M2M_D2C_WIDTH 1
9399
+#define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_DESC_PROXY_OFST 16
9400
+#define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_DESC_PROXY_LBN 16
9401
+#define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_DESC_PROXY_WIDTH 1
76369402 /* Owner ID to use if in buffer mode (zero if physical) */
76379403 #define       MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 20
76389404 #define       MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_LEN 4
....@@ -7646,11 +9412,14 @@
76469412 #define       MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 32
76479413 #define       MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 1
76489414 #define       MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64
9415
+#define       MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM_MCDI2 64
76499416 /* Flags related to Qbb flow control mode. */
76509417 #define       MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_OFST 540
76519418 #define       MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_LEN 4
9419
+#define        MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_OFST 540
76529420 #define        MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0
76539421 #define        MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 1
9422
+#define        MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_OFST 540
76549423 #define        MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 1
76559424 #define        MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_WIDTH 3
76569425 
....@@ -7666,6 +9435,7 @@
76669435  * or the operation will fail with EBUSY
76679436  */
76689437 #define MC_CMD_FINI_EVQ 0x83
9438
+#undef MC_CMD_0x83_PRIVILEGE_CTG
76699439 
76709440 #define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL
76719441 
....@@ -7686,6 +9456,7 @@
76869456  * Teardown a RXQ.
76879457  */
76889458 #define MC_CMD_FINI_RXQ 0x84
9459
+#undef MC_CMD_0x84_PRIVILEGE_CTG
76899460 
76909461 #define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL
76919462 
....@@ -7704,6 +9475,7 @@
77049475  * Teardown a TXQ.
77059476  */
77069477 #define MC_CMD_FINI_TXQ 0x85
9478
+#undef MC_CMD_0x85_PRIVILEGE_CTG
77079479 
77089480 #define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL
77099481 
....@@ -7722,6 +9494,7 @@
77229494  * Generate an event on an EVQ belonging to the function issuing the command.
77239495  */
77249496 #define MC_CMD_DRIVER_EVENT 0x86
9497
+#undef MC_CMD_0x86_PRIVILEGE_CTG
77259498 
77269499 #define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL
77279500 
....@@ -7748,6 +9521,7 @@
77489521  * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated.
77499522  */
77509523 #define MC_CMD_PROXY_CMD 0x5b
9524
+#undef MC_CMD_0x5b_PRIVILEGE_CTG
77519525 
77529526 #define MC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
77539527 
....@@ -7756,8 +9530,10 @@
77569530 /* The handle of the target function. */
77579531 #define       MC_CMD_PROXY_CMD_IN_TARGET_OFST 0
77589532 #define       MC_CMD_PROXY_CMD_IN_TARGET_LEN 4
9533
+#define        MC_CMD_PROXY_CMD_IN_TARGET_PF_OFST 0
77599534 #define        MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0
77609535 #define        MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16
9536
+#define        MC_CMD_PROXY_CMD_IN_TARGET_VF_OFST 0
77619537 #define        MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16
77629538 #define        MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16
77639539 #define          MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */
....@@ -7813,6 +9589,7 @@
78139589  * a designated admin function
78149590  */
78159591 #define MC_CMD_PROXY_CONFIGURE 0x58
9592
+#undef MC_CMD_0x58_PRIVILEGE_CTG
78169593 
78179594 #define MC_CMD_0x58_PRIVILEGE_CTG SRIOV_CTG_ADMIN
78189595 
....@@ -7820,6 +9597,7 @@
78209597 #define    MC_CMD_PROXY_CONFIGURE_IN_LEN 108
78219598 #define       MC_CMD_PROXY_CONFIGURE_IN_FLAGS_OFST 0
78229599 #define       MC_CMD_PROXY_CONFIGURE_IN_FLAGS_LEN 4
9600
+#define        MC_CMD_PROXY_CONFIGURE_IN_ENABLE_OFST 0
78239601 #define        MC_CMD_PROXY_CONFIGURE_IN_ENABLE_LBN 0
78249602 #define        MC_CMD_PROXY_CONFIGURE_IN_ENABLE_WIDTH 1
78259603 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
....@@ -7864,6 +9642,7 @@
78649642 #define    MC_CMD_PROXY_CONFIGURE_EXT_IN_LEN 112
78659643 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_OFST 0
78669644 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_LEN 4
9645
+#define        MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_OFST 0
78679646 #define        MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_LBN 0
78689647 #define        MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_WIDTH 1
78699648 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
....@@ -7918,6 +9697,7 @@
79189697  * MC_CMD_PROXY_CONFIGURE).
79199698  */
79209699 #define MC_CMD_PROXY_COMPLETE 0x5f
9700
+#undef MC_CMD_0x5f_PRIVILEGE_CTG
79219701 
79229702 #define MC_CMD_0x5f_PRIVILEGE_CTG SRIOV_CTG_ADMIN
79239703 
....@@ -7955,6 +9735,7 @@
79559735  * cannot do so). The buffer table entries will initially be zeroed.
79569736  */
79579737 #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87
9738
+#undef MC_CMD_0x87_PRIVILEGE_CTG
79589739 
79599740 #define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
79609741 
....@@ -7985,13 +9766,16 @@
79859766  * Reprogram a set of buffer table entries in the specified chunk.
79869767  */
79879768 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88
9769
+#undef MC_CMD_0x88_PRIVILEGE_CTG
79889770 
79899771 #define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
79909772 
79919773 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */
79929774 #define    MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20
79939775 #define    MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 268
9776
+#define    MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX_MCDI2 268
79949777 #define    MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num))
9778
+#define    MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_NUM(len) (((len)-12)/8)
79959779 #define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0
79969780 #define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_LEN 4
79979781 /* ID */
....@@ -8007,6 +9791,7 @@
80079791 #define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16
80089792 #define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1
80099793 #define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32
9794
+#define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM_MCDI2 32
80109795 
80119796 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */
80129797 #define    MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0
....@@ -8016,6 +9801,7 @@
80169801 /* MC_CMD_FREE_BUFTBL_CHUNK
80179802  */
80189803 #define MC_CMD_FREE_BUFTBL_CHUNK 0x89
9804
+#undef MC_CMD_0x89_PRIVILEGE_CTG
80199805 
80209806 #define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
80219807 
....@@ -8033,6 +9819,7 @@
80339819  * Multiplexed MCDI call for filter operations
80349820  */
80359821 #define MC_CMD_FILTER_OP 0x8a
9822
+#undef MC_CMD_0x8a_PRIVILEGE_CTG
80369823 
80379824 #define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
80389825 
....@@ -8065,32 +9852,46 @@
80659852 /* fields to include in match criteria */
80669853 #define       MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16
80679854 #define       MC_CMD_FILTER_OP_IN_MATCH_FIELDS_LEN 4
9855
+#define        MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_OFST 16
80689856 #define        MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0
80699857 #define        MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1
9858
+#define        MC_CMD_FILTER_OP_IN_MATCH_DST_IP_OFST 16
80709859 #define        MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1
80719860 #define        MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1
9861
+#define        MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_OFST 16
80729862 #define        MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2
80739863 #define        MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1
9864
+#define        MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_OFST 16
80749865 #define        MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3
80759866 #define        MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1
9867
+#define        MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_OFST 16
80769868 #define        MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4
80779869 #define        MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1
9870
+#define        MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_OFST 16
80789871 #define        MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5
80799872 #define        MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1
9873
+#define        MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_OFST 16
80809874 #define        MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6
80819875 #define        MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1
9876
+#define        MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_OFST 16
80829877 #define        MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7
80839878 #define        MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1
9879
+#define        MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_OFST 16
80849880 #define        MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8
80859881 #define        MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1
9882
+#define        MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_OFST 16
80869883 #define        MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9
80879884 #define        MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1
9885
+#define        MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_OFST 16
80889886 #define        MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10
80899887 #define        MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1
9888
+#define        MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_OFST 16
80909889 #define        MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11
80919890 #define        MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1
9891
+#define        MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_OFST 16
80929892 #define        MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30
80939893 #define        MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
9894
+#define        MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_OFST 16
80949895 #define        MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31
80959896 #define        MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
80969897 /* receive destination */
....@@ -8138,8 +9939,10 @@
81389939 #define       MC_CMD_FILTER_OP_IN_TX_DEST_LEN 4
81399940 /* enum: request default behaviour (based on filter type) */
81409941 #define          MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff
9942
+#define        MC_CMD_FILTER_OP_IN_TX_DEST_MAC_OFST 40
81419943 #define        MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0
81429944 #define        MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1
9945
+#define        MC_CMD_FILTER_OP_IN_TX_DEST_PM_OFST 40
81439946 #define        MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1
81449947 #define        MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1
81459948 /* source MAC address to match (as bytes in network order) */
....@@ -8205,60 +10008,88 @@
820510008 /* fields to include in match criteria */
820610009 #define       MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 16
820710010 #define       MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_LEN 4
10011
+#define        MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_OFST 16
820810012 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0
820910013 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1
10014
+#define        MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_OFST 16
821010015 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1
821110016 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 1
10017
+#define        MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_OFST 16
821210018 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_LBN 2
821310019 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 1
10020
+#define        MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_OFST 16
821410021 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_LBN 3
821510022 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 1
10023
+#define        MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_OFST 16
821610024 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4
821710025 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 1
10026
+#define        MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_OFST 16
821810027 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_LBN 5
821910028 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 1
10029
+#define        MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_OFST 16
822010030 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN 6
822110031 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 1
10032
+#define        MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_OFST 16
822210033 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_LBN 7
822310034 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 1
10035
+#define        MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_OFST 16
822410036 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_LBN 8
822510037 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 1
10038
+#define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_OFST 16
822610039 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN 9
822710040 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 1
10041
+#define        MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_OFST 16
822810042 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_LBN 10
822910043 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 1
10044
+#define        MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_OFST 16
823010045 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_LBN 11
823110046 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 1
10047
+#define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_OFST 16
823210048 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_LBN 12
823310049 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 1
10050
+#define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_OFST 16
823410051 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_LBN 13
823510052 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 1
10053
+#define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_OFST 16
823610054 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_LBN 14
823710055 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 1
10056
+#define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_OFST 16
823810057 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_LBN 15
823910058 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 1
10059
+#define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_OFST 16
824010060 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_LBN 16
824110061 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 1
10062
+#define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_OFST 16
824210063 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_LBN 17
824310064 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 1
10065
+#define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_OFST 16
824410066 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_LBN 18
824510067 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1
10068
+#define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_OFST 16
824610069 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_LBN 19
824710070 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1
10071
+#define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_OFST 16
824810072 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_LBN 20
824910073 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1
10074
+#define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_OFST 16
825010075 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_LBN 21
825110076 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 1
10077
+#define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_OFST 16
825210078 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_LBN 22
825310079 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 1
10080
+#define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_OFST 16
825410081 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_LBN 23
825510082 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 1
10083
+#define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_OFST 16
825610084 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24
825710085 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1
10086
+#define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_OFST 16
825810087 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25
825910088 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1
10089
+#define        MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_OFST 16
826010090 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30
826110091 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
10092
+#define        MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_OFST 16
826210093 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31
826310094 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
826410095 /* receive destination */
....@@ -8306,8 +10137,10 @@
830610137 #define       MC_CMD_FILTER_OP_EXT_IN_TX_DEST_LEN 4
830710138 /* enum: request default behaviour (based on filter type) */
830810139 #define          MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff
10140
+#define        MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_OFST 40
830910141 #define        MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0
831010142 #define        MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1
10143
+#define        MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_OFST 40
831110144 #define        MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1
831210145 #define        MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 1
831310146 /* source MAC address to match (as bytes in network order) */
....@@ -8343,8 +10176,10 @@
834310176  */
834410177 #define       MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 72
834510178 #define       MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_LEN 4
10179
+#define        MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_OFST 72
834610180 #define        MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0
834710181 #define        MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 24
10182
+#define        MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_OFST 72
834810183 #define        MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 24
834910184 #define        MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 8
835010185 /* enum: Match VXLAN traffic with this VNI */
....@@ -8353,8 +10188,10 @@
835310188 #define          MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1
835410189 /* enum: Reserved for experimental development use */
835510190 #define          MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe
10191
+#define        MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_OFST 72
835610192 #define        MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0
835710193 #define        MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 24
10194
+#define        MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_OFST 72
835810195 #define        MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 24
835910196 #define        MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 8
836010197 /* enum: Match NVGRE traffic with this VSID */
....@@ -8449,60 +10286,88 @@
844910286 /* fields to include in match criteria */
845010287 #define       MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_OFST 16
845110288 #define       MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_LEN 4
10289
+#define        MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_OFST 16
845210290 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_LBN 0
845310291 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_WIDTH 1
10292
+#define        MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_OFST 16
845410293 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_LBN 1
845510294 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_WIDTH 1
10295
+#define        MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_OFST 16
845610296 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_LBN 2
845710297 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_WIDTH 1
10298
+#define        MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_OFST 16
845810299 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_LBN 3
845910300 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_WIDTH 1
10301
+#define        MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_OFST 16
846010302 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_LBN 4
846110303 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_WIDTH 1
10304
+#define        MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_OFST 16
846210305 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_LBN 5
846310306 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_WIDTH 1
10307
+#define        MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_OFST 16
846410308 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_LBN 6
846510309 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_WIDTH 1
10310
+#define        MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_OFST 16
846610311 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_LBN 7
846710312 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_WIDTH 1
10313
+#define        MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_OFST 16
846810314 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_LBN 8
846910315 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_WIDTH 1
10316
+#define        MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_OFST 16
847010317 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_LBN 9
847110318 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_WIDTH 1
10319
+#define        MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_OFST 16
847210320 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_LBN 10
847310321 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_WIDTH 1
10322
+#define        MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_OFST 16
847410323 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_LBN 11
847510324 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_WIDTH 1
10325
+#define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_OFST 16
847610326 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_LBN 12
847710327 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_WIDTH 1
10328
+#define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_OFST 16
847810329 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_LBN 13
847910330 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_WIDTH 1
10331
+#define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_OFST 16
848010332 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_LBN 14
848110333 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_WIDTH 1
10334
+#define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_OFST 16
848210335 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_LBN 15
848310336 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_WIDTH 1
10337
+#define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_OFST 16
848410338 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_LBN 16
848510339 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_WIDTH 1
10340
+#define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_OFST 16
848610341 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_LBN 17
848710342 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_WIDTH 1
10343
+#define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_OFST 16
848810344 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_LBN 18
848910345 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1
10346
+#define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_OFST 16
849010347 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_LBN 19
849110348 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1
10349
+#define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_OFST 16
849210350 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_LBN 20
849310351 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1
10352
+#define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_OFST 16
849410353 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_LBN 21
849510354 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_WIDTH 1
10355
+#define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_OFST 16
849610356 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_LBN 22
849710357 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_WIDTH 1
10358
+#define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_OFST 16
849810359 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_LBN 23
849910360 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_WIDTH 1
10361
+#define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_OFST 16
850010362 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24
850110363 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1
10364
+#define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_OFST 16
850210365 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25
850310366 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1
10367
+#define        MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_OFST 16
850410368 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30
850510369 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
10370
+#define        MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_OFST 16
850610371 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31
850710372 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
850810373 /* receive destination */
....@@ -8550,8 +10415,10 @@
855010415 #define       MC_CMD_FILTER_OP_V3_IN_TX_DEST_LEN 4
855110416 /* enum: request default behaviour (based on filter type) */
855210417 #define          MC_CMD_FILTER_OP_V3_IN_TX_DEST_DEFAULT 0xffffffff
10418
+#define        MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_OFST 40
855310419 #define        MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_LBN 0
855410420 #define        MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_WIDTH 1
10421
+#define        MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_OFST 40
855510422 #define        MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_LBN 1
855610423 #define        MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_WIDTH 1
855710424 /* source MAC address to match (as bytes in network order) */
....@@ -8587,8 +10454,10 @@
858710454  */
858810455 #define       MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_OFST 72
858910456 #define       MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_LEN 4
10457
+#define        MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_OFST 72
859010458 #define        MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_LBN 0
859110459 #define        MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_WIDTH 24
10460
+#define        MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_OFST 72
859210461 #define        MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_LBN 24
859310462 #define        MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_WIDTH 8
859410463 /* enum: Match VXLAN traffic with this VNI */
....@@ -8597,8 +10466,10 @@
859710466 #define          MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_GENEVE 0x1
859810467 /* enum: Reserved for experimental development use */
859910468 #define          MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_EXPERIMENTAL 0xfe
10469
+#define        MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_OFST 72
860010470 #define        MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_LBN 0
860110471 #define        MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_WIDTH 24
10472
+#define        MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_OFST 72
860210473 #define        MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_LBN 24
860310474 #define        MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_WIDTH 8
860410475 /* enum: Match NVGRE traffic with this VSID */
....@@ -8688,7 +10559,10 @@
868810559  * support the DPDK rte_flow "MARK" action.
868910560  */
869010561 #define          MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_MARK 0x2
8691
-/* the mark value for MATCH_ACTION_MARK */
10562
+/* the mark value for MATCH_ACTION_MARK. Requesting a value larger than the
10563
+ * maximum (obtained from MC_CMD_GET_CAPABILITIES_V5/FILTER_ACTION_MARK_MAX)
10564
+ * will cause the filter insertion to fail with EINVAL.
10565
+ */
869210566 #define       MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_OFST 176
869310567 #define       MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_LEN 4
869410568 
....@@ -8736,6 +10610,7 @@
873610610  * Get information related to the parser-dispatcher subsystem
873710611  */
873810612 #define MC_CMD_GET_PARSER_DISP_INFO 0xe4
10613
+#undef MC_CMD_0xe4_PRIVILEGE_CTG
873910614 
874010615 #define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
874110616 
....@@ -8759,11 +10634,17 @@
875910634  * frames (Medford only)
876010635  */
876110636 #define          MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x4
10637
+/* enum: read the list of supported matches for the encapsulation detection
10638
+ * rules inserted by MC_CMD_VNIC_ENCAP_RULE_ADD. (ef100 and later)
10639
+ */
10640
+#define          MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES 0x5
876210641 
876310642 /* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */
876410643 #define    MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8
876510644 #define    MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252
10645
+#define    MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX_MCDI2 1020
876610646 #define    MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num))
10647
+#define    MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_NUM(len) (((len)-8)/4)
876710648 /* identifies the type of operation requested */
876810649 #define       MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0
876910650 #define       MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_LEN 4
....@@ -8779,6 +10660,7 @@
877910660 #define       MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4
878010661 #define       MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0
878110662 #define       MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61
10663
+#define       MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM_MCDI2 253
878210664 
878310665 /* MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT msgresponse */
878410666 #define    MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_LEN 8
....@@ -8790,8 +10672,37 @@
879010672 /* bitfield of filter insertion restrictions */
879110673 #define       MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4
879210674 #define       MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_LEN 4
10675
+#define        MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_OFST 4
879310676 #define        MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0
879410677 #define        MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 1
10678
+
10679
+/* MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT msgresponse: This response is
10680
+ * returned if a MC_CMD_GET_PARSER_DISP_INFO_IN request is sent with OP value
10681
+ * OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES. It contains information about the
10682
+ * supported match types that can be used in the encapsulation detection rules
10683
+ * inserted by MC_CMD_VNIC_ENCAP_RULE_ADD.
10684
+ */
10685
+#define    MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LENMIN 8
10686
+#define    MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LENMAX 252
10687
+#define    MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LENMAX_MCDI2 1020
10688
+#define    MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LEN(num) (8+4*(num))
10689
+#define    MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_NUM(len) (((len)-8)/4)
10690
+/* The op code OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES is returned. */
10691
+#define       MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_OP_OFST 0
10692
+#define       MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_OP_LEN 4
10693
+/*            Enum values, see field(s): */
10694
+/*               MC_CMD_GET_PARSER_DISP_INFO_IN/OP */
10695
+/* number of supported match types */
10696
+#define       MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_NUM_SUPPORTED_MATCHES_OFST 4
10697
+#define       MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_NUM_SUPPORTED_MATCHES_LEN 4
10698
+/* array of supported match types (valid MATCH_FLAGS values for
10699
+ * MC_CMD_VNIC_ENCAP_RULE_ADD) sorted in decreasing priority order
10700
+ */
10701
+#define       MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_OFST 8
10702
+#define       MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_LEN 4
10703
+#define       MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MINNUM 0
10704
+#define       MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MAXNUM 61
10705
+#define       MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MAXNUM_MCDI2 253
879510706 
879610707 
879710708 /***********************************/
....@@ -8804,6 +10715,7 @@
880410715  * permitted.
880510716  */
880610717 #define MC_CMD_PARSER_DISP_RW 0xe5
10718
+#undef MC_CMD_0xe5_PRIVILEGE_CTG
880710719 
880810720 #define MC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
880910721 
....@@ -8893,6 +10805,7 @@
889310805  * Get number of PFs on the device.
889410806  */
889510807 #define MC_CMD_GET_PF_COUNT 0xb6
10808
+#undef MC_CMD_0xb6_PRIVILEGE_CTG
889610809 
889710810 #define MC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
889810811 
....@@ -8927,6 +10840,7 @@
892710840  * Get port assignment for current PCI function.
892810841  */
892910842 #define MC_CMD_GET_PORT_ASSIGNMENT 0xb8
10843
+#undef MC_CMD_0xb8_PRIVILEGE_CTG
893010844 
893110845 #define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
893210846 
....@@ -8945,6 +10859,7 @@
894510859  * Set port assignment for current PCI function.
894610860  */
894710861 #define MC_CMD_SET_PORT_ASSIGNMENT 0xb9
10862
+#undef MC_CMD_0xb9_PRIVILEGE_CTG
894810863 
894910864 #define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN
895010865 
....@@ -8963,6 +10878,7 @@
896310878  * Allocate VIs for current PCI function.
896410879  */
896510880 #define MC_CMD_ALLOC_VIS 0x8b
10881
+#undef MC_CMD_0x8b_PRIVILEGE_CTG
896610882 
896710883 #define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL
896810884 
....@@ -9009,6 +10925,7 @@
900910925  * but not freed.
901010926  */
901110927 #define MC_CMD_FREE_VIS 0x8c
10928
+#undef MC_CMD_0x8c_PRIVILEGE_CTG
901210929 
901310930 #define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
901410931 
....@@ -9024,6 +10941,7 @@
902410941  * Get SRIOV config for this PF.
902510942  */
902610943 #define MC_CMD_GET_SRIOV_CFG 0xba
10944
+#undef MC_CMD_0xba_PRIVILEGE_CTG
902710945 
902810946 #define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL
902910947 
....@@ -9040,6 +10958,7 @@
904010958 #define       MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_LEN 4
904110959 #define       MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8
904210960 #define       MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_LEN 4
10961
+#define        MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_OFST 8
904310962 #define        MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0
904410963 #define        MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1
904510964 /* RID offset of first VF from PF. */
....@@ -9055,6 +10974,7 @@
905510974  * Set SRIOV config for this PF.
905610975  */
905710976 #define MC_CMD_SET_SRIOV_CFG 0xbb
10977
+#undef MC_CMD_0xbb_PRIVILEGE_CTG
905810978 
905910979 #define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN
906010980 
....@@ -9068,6 +10988,7 @@
906810988 #define       MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_LEN 4
906910989 #define       MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8
907010990 #define       MC_CMD_SET_SRIOV_CFG_IN_FLAGS_LEN 4
10991
+#define        MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_OFST 8
907110992 #define        MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0
907210993 #define        MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1
907310994 /* RID offset of first VF from PF, or 0 for no change, or
....@@ -9091,6 +11012,7 @@
909111012  * function.
909211013  */
909311014 #define MC_CMD_GET_VI_ALLOC_INFO 0x8d
11015
+#undef MC_CMD_0x8d_PRIVILEGE_CTG
909411016 
909511017 #define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
909611018 
....@@ -9117,6 +11039,7 @@
911711039  * For CmdClient use. Dump pertinent information on a specific absolute VI.
911811040  */
911911041 #define MC_CMD_DUMP_VI_STATE 0x8e
11042
+#undef MC_CMD_0x8e_PRIVILEGE_CTG
912011043 
912111044 #define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
912211045 
....@@ -9159,10 +11082,13 @@
915911082 /* Combined metadata field. */
916011083 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28
916111084 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_LEN 4
11085
+#define        MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_OFST 28
916211086 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0
916311087 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16
11088
+#define        MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_OFST 28
916411089 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16
916511090 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8
11091
+#define        MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_OFST 28
916611092 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24
916711093 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8
916811094 /* TXDPCPU raw table data for queue. */
....@@ -9185,14 +11111,19 @@
918511111 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8
918611112 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56
918711113 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60
11114
+#define        MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_OFST 56
918811115 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0
918911116 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16
11117
+#define        MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_OFST 56
919011118 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16
919111119 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8
11120
+#define        MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_OFST 56
919211121 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24
919311122 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8
11123
+#define        MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_OFST 56
919411124 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32
919511125 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8
11126
+#define        MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_OFST 56
919611127 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40
919711128 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24
919811129 /* RXDPCPU raw table data for queue. */
....@@ -9215,12 +11146,16 @@
921511146 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8
921611147 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88
921711148 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92
11149
+#define        MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_OFST 88
921811150 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0
921911151 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16
11152
+#define        MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_OFST 88
922011153 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16
922111154 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8
11155
+#define        MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_OFST 88
922211156 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24
922311157 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8
11158
+#define        MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_OFST 88
922411159 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32
922511160 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8
922611161 
....@@ -9230,6 +11165,7 @@
923011165  * Allocate a push I/O buffer for later use with a tx queue.
923111166  */
923211167 #define MC_CMD_ALLOC_PIOBUF 0x8f
11168
+#undef MC_CMD_0x8f_PRIVILEGE_CTG
923311169 
923411170 #define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
923511171 
....@@ -9248,6 +11184,7 @@
924811184  * Free a push I/O buffer.
924911185  */
925011186 #define MC_CMD_FREE_PIOBUF 0x90
11187
+#undef MC_CMD_0x90_PRIVILEGE_CTG
925111188 
925211189 #define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
925311190 
....@@ -9266,6 +11203,7 @@
926611203  * Get TLP steering and ordering information for a VI.
926711204  */
926811205 #define MC_CMD_GET_VI_TLP_PROCESSING 0xb0
11206
+#undef MC_CMD_0xb0_PRIVILEGE_CTG
926911207 
927011208 #define MC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
927111209 
....@@ -9304,6 +11242,7 @@
930411242  * Set TLP steering and ordering information for a VI.
930511243  */
930611244 #define MC_CMD_SET_VI_TLP_PROCESSING 0xb1
11245
+#undef MC_CMD_0xb1_PRIVILEGE_CTG
930711246 
930811247 #define MC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
930911248 
....@@ -9342,6 +11281,7 @@
934211281  * Get global PCIe steering and transaction processing configuration.
934311282  */
934411283 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc
11284
+#undef MC_CMD_0xbc_PRIVILEGE_CTG
934511285 
934611286 #define MC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN
934711287 
....@@ -9367,38 +11307,55 @@
936711307 /* Amalgamated TLP info word. */
936811308 #define       MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4
936911309 #define       MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_LEN 4
11310
+#define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_OFST 4
937011311 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0
937111312 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1
11313
+#define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_OFST 4
937211314 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1
937311315 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31
11316
+#define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_OFST 4
937411317 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0
937511318 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1
11319
+#define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_OFST 4
937611320 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1
937711321 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1
11322
+#define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_OFST 4
937811323 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2
937911324 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1
11325
+#define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_OFST 4
938011326 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3
938111327 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1
11328
+#define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_OFST 4
938211329 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4
938311330 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28
11331
+#define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_OFST 4
938411332 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0
938511333 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1
11334
+#define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_OFST 4
938611335 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1
938711336 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1
11337
+#define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_OFST 4
938811338 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2
938911339 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1
11340
+#define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_OFST 4
939011341 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3
939111342 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29
11343
+#define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_OFST 4
939211344 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0
939311345 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2
11346
+#define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_OFST 4
939411347 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2
939511348 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2
11349
+#define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_OFST 4
939611350 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4
939711351 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2
11352
+#define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_OFST 4
939811353 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6
939911354 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2
11355
+#define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_OFST 4
940011356 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8
940111357 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2
11358
+#define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_OFST 4
940211359 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9
940311360 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23
940411361 
....@@ -9408,6 +11365,7 @@
940811365  * Set global PCIe steering and transaction processing configuration.
940911366  */
941011367 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd
11368
+#undef MC_CMD_0xbd_PRIVILEGE_CTG
941111369 
941211370 #define MC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN
941311371 
....@@ -9420,32 +11378,46 @@
942011378 /* Amalgamated TLP info word. */
942111379 #define       MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4
942211380 #define       MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_LEN 4
11381
+#define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_OFST 4
942311382 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0
942411383 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1
11384
+#define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_OFST 4
942511385 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0
942611386 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1
11387
+#define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_OFST 4
942711388 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1
942811389 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1
11390
+#define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_OFST 4
942911391 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2
943011392 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1
11393
+#define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_OFST 4
943111394 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3
943211395 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1
11396
+#define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_OFST 4
943311397 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0
943411398 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1
11399
+#define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_OFST 4
943511400 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1
943611401 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1
11402
+#define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_OFST 4
943711403 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2
943811404 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1
11405
+#define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_OFST 4
943911406 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0
944011407 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2
11408
+#define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_OFST 4
944111409 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2
944211410 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2
11411
+#define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_OFST 4
944311412 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4
944411413 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2
11414
+#define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_OFST 4
944511415 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6
944611416 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2
11417
+#define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_OFST 4
944711418 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8
944811419 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2
11420
+#define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_OFST 4
944911421 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10
945011422 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22
945111423 
....@@ -9458,6 +11430,7 @@
945811430  * Download a new set of images to the satellite CPUs from the host.
945911431  */
946011432 #define MC_CMD_SATELLITE_DOWNLOAD 0x91
11433
+#undef MC_CMD_0x91_PRIVILEGE_CTG
946111434 
946211435 #define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN
946311436 
....@@ -9481,7 +11454,9 @@
948111454  */
948211455 #define    MC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 20
948311456 #define    MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252
11457
+#define    MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX_MCDI2 1020
948411458 #define    MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num))
11459
+#define    MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_NUM(len) (((len)-16)/4)
948511460 /* Download phase. (Note: the IDLE phase is used internally and is never valid
948611461  * in a command from the host.)
948711462  */
....@@ -9546,6 +11521,7 @@
954611521 #define       MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4
954711522 #define       MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1
954811523 #define       MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 59
11524
+#define       MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM_MCDI2 251
954911525 
955011526 /* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */
955111527 #define    MC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8
....@@ -9581,6 +11557,7 @@
958111557  * reference inherent device capabilities as opposed to current NVRAM config.
958211558  */
958311559 #define MC_CMD_GET_CAPABILITIES 0xbe
11560
+#undef MC_CMD_0xbe_PRIVILEGE_CTG
958411561 
958511562 #define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL
958611563 
....@@ -9592,62 +11569,91 @@
959211569 /* First word of flags. */
959311570 #define       MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0
959411571 #define       MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_LEN 4
11572
+#define        MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_OFST 0
959511573 #define        MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_LBN 3
959611574 #define        MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_WIDTH 1
11575
+#define        MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_OFST 0
959711576 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4
959811577 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_WIDTH 1
11578
+#define        MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_OFST 0
959911579 #define        MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN 5
960011580 #define        MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_WIDTH 1
11581
+#define        MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
960111582 #define        MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
960211583 #define        MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
11584
+#define        MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_OFST 0
960311585 #define        MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_LBN 7
960411586 #define        MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
11587
+#define        MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_OFST 0
960511588 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_LBN 8
960611589 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
11590
+#define        MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_OFST 0
960711591 #define        MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_LBN 9
960811592 #define        MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_WIDTH 1
11593
+#define        MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
960911594 #define        MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
961011595 #define        MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
11596
+#define        MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
961111597 #define        MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
961211598 #define        MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
11599
+#define        MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
961311600 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
961411601 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
11602
+#define        MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_OFST 0
961511603 #define        MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN 13
961611604 #define        MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
11605
+#define        MC_CMD_GET_CAPABILITIES_OUT_QBB_OFST 0
961711606 #define        MC_CMD_GET_CAPABILITIES_OUT_QBB_LBN 14
961811607 #define        MC_CMD_GET_CAPABILITIES_OUT_QBB_WIDTH 1
11608
+#define        MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
961911609 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
962011610 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
11611
+#define        MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_OFST 0
962111612 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN 16
962211613 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_WIDTH 1
11614
+#define        MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_OFST 0
962311615 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_LBN 17
962411616 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_WIDTH 1
11617
+#define        MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_OFST 0
962511618 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN 18
962611619 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_WIDTH 1
11620
+#define        MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_OFST 0
962711621 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19
962811622 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1
11623
+#define        MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_OFST 0
962911624 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20
963011625 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1
11626
+#define        MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_OFST 0
963111627 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21
963211628 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1
11629
+#define        MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_OFST 0
963311630 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22
963411631 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1
11632
+#define        MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_OFST 0
963511633 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23
963611634 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1
11635
+#define        MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_OFST 0
963711636 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24
963811637 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1
11638
+#define        MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_OFST 0
963911639 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25
964011640 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1
11641
+#define        MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_OFST 0
964111642 #define        MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26
964211643 #define        MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1
11644
+#define        MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_OFST 0
964311645 #define        MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27
964411646 #define        MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
11647
+#define        MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_OFST 0
964511648 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_LBN 28
964611649 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_WIDTH 1
11650
+#define        MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
964711651 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
964811652 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
11653
+#define        MC_CMD_GET_CAPABILITIES_OUT_EVB_OFST 0
964911654 #define        MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN 30
965011655 #define        MC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 1
11656
+#define        MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_OFST 0
965111657 #define        MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN 31
965211658 #define        MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_WIDTH 1
965311659 /* RxDPCPU firmware id. */
....@@ -9708,8 +11714,10 @@
970811714 #define          MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR 0x103
970911715 #define       MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8
971011716 #define       MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2
11717
+#define        MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_OFST 8
971111718 #define        MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0
971211719 #define        MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12
11720
+#define        MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_OFST 8
971311721 #define        MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12
971411722 #define        MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
971511723 /* enum: reserved value - do not use (may indicate alternative interpretation
....@@ -9720,6 +11728,9 @@
972011728  * development only)
972111729  */
972211730 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
11731
+/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
11732
+ */
11733
+#define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
972311734 /* enum: RX PD firmware with approximately Siena-compatible behaviour
972411735  * (Huntington development only)
972511736  */
....@@ -9754,8 +11765,10 @@
975411765 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
975511766 #define       MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10
975611767 #define       MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2
11768
+#define        MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_OFST 10
975711769 #define        MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0
975811770 #define        MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12
11771
+#define        MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_OFST 10
975911772 #define        MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12
976011773 #define        MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
976111774 /* enum: reserved value - do not use (may indicate alternative interpretation
....@@ -9766,6 +11779,9 @@
976611779  * development only)
976711780  */
976811781 #define          MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
11782
+/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
11783
+ */
11784
+#define          MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
976911785 /* enum: TX PD firmware with approximately Siena-compatible behaviour
977011786  * (Huntington development only)
977111787  */
....@@ -9806,62 +11822,91 @@
980611822 /* First word of flags. */
980711823 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0
980811824 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_LEN 4
11825
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_OFST 0
980911826 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_LBN 3
981011827 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_WIDTH 1
11828
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_OFST 0
981111829 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4
981211830 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_WIDTH 1
11831
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_OFST 0
981311832 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_LBN 5
981411833 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_WIDTH 1
11834
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
981511835 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
981611836 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
11837
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_OFST 0
981711838 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_LBN 7
981811839 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
11840
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_OFST 0
981911841 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_LBN 8
982011842 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
11843
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_OFST 0
982111844 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_LBN 9
982211845 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_WIDTH 1
11846
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
982311847 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
982411848 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
11849
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
982511850 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
982611851 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
11852
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
982711853 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
982811854 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
11855
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_OFST 0
982911856 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_LBN 13
983011857 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
11858
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_OFST 0
983111859 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_LBN 14
983211860 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_WIDTH 1
11861
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
983311862 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
983411863 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
11864
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_OFST 0
983511865 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_LBN 16
983611866 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_WIDTH 1
11867
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_OFST 0
983711868 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_LBN 17
983811869 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_WIDTH 1
11870
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_OFST 0
983911871 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_LBN 18
984011872 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_WIDTH 1
11873
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_OFST 0
984111874 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_LBN 19
984211875 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_WIDTH 1
11876
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_OFST 0
984311877 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_LBN 20
984411878 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_WIDTH 1
11879
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_OFST 0
984511880 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_LBN 21
984611881 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_WIDTH 1
11882
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_OFST 0
984711883 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_LBN 22
984811884 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_WIDTH 1
11885
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_OFST 0
984911886 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_LBN 23
985011887 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_WIDTH 1
11888
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_OFST 0
985111889 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_LBN 24
985211890 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_WIDTH 1
11891
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_OFST 0
985311892 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_LBN 25
985411893 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_WIDTH 1
11894
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_OFST 0
985511895 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_LBN 26
985611896 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_WIDTH 1
11897
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_OFST 0
985711898 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_LBN 27
985811899 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
11900
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_OFST 0
985911901 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_LBN 28
986011902 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_WIDTH 1
11903
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
986111904 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
986211905 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
11906
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_OFST 0
986311907 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_LBN 30
986411908 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_WIDTH 1
11909
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_OFST 0
986511910 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_LBN 31
986611911 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_WIDTH 1
986711912 /* RxDPCPU firmware id. */
....@@ -9922,8 +11967,10 @@
992211967 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR 0x103
992311968 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_OFST 8
992411969 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_LEN 2
11970
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_OFST 8
992511971 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0
992611972 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_WIDTH 12
11973
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_OFST 8
992711974 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_LBN 12
992811975 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
992911976 /* enum: reserved value - do not use (may indicate alternative interpretation
....@@ -9934,6 +11981,9 @@
993411981  * development only)
993511982  */
993611983 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
11984
+/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
11985
+ */
11986
+#define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
993711987 /* enum: RX PD firmware with approximately Siena-compatible behaviour
993811988  * (Huntington development only)
993911989  */
....@@ -9968,8 +12018,10 @@
996812018 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
996912019 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_OFST 10
997012020 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_LEN 2
12021
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_OFST 10
997112022 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0
997212023 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_WIDTH 12
12024
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_OFST 10
997312025 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_LBN 12
997412026 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
997512027 /* enum: reserved value - do not use (may indicate alternative interpretation
....@@ -9980,6 +12032,9 @@
998012032  * development only)
998112033  */
998212034 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
12035
+/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
12036
+ */
12037
+#define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
998312038 /* enum: TX PD firmware with approximately Siena-compatible behaviour
998412039  * (Huntington development only)
998512040  */
....@@ -10014,58 +12069,110 @@
1001412069 /* Second word of flags. Not present on older firmware (check the length). */
1001512070 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_OFST 20
1001612071 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_LEN 4
12072
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_OFST 20
1001712073 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0
1001812074 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_WIDTH 1
12075
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_OFST 20
1001912076 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_LBN 1
1002012077 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_WIDTH 1
12078
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_OFST 20
1002112079 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_LBN 2
1002212080 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_WIDTH 1
12081
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_OFST 20
1002312082 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_LBN 3
1002412083 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_WIDTH 1
12084
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_OFST 20
1002512085 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_LBN 4
1002612086 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_WIDTH 1
12087
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_OFST 20
1002712088 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_LBN 5
1002812089 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
12090
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
1002912091 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
1003012092 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
12093
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
12094
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
12095
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
12096
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_OFST 20
1003112097 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN 7
1003212098 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_WIDTH 1
12099
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_OFST 20
1003312100 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_LBN 8
1003412101 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
12102
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_OFST 20
1003512103 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_LBN 9
1003612104 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_WIDTH 1
12105
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_OFST 20
1003712106 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_LBN 10
1003812107 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_WIDTH 1
12108
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_OFST 20
1003912109 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_LBN 11
1004012110 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_WIDTH 1
12111
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
1004112112 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
1004212113 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
12114
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_OFST 20
1004312115 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_LBN 13
1004412116 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_WIDTH 1
12117
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_OFST 20
1004512118 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_LBN 14
1004612119 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_WIDTH 1
12120
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_OFST 20
1004712121 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_LBN 15
1004812122 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_WIDTH 1
12123
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_OFST 20
1004912124 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_LBN 16
1005012125 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_WIDTH 1
12126
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_OFST 20
1005112127 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_LBN 17
1005212128 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_WIDTH 1
12129
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
1005312130 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
1005412131 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
12132
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_OFST 20
1005512133 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_LBN 19
1005612134 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_WIDTH 1
12135
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_OFST 20
1005712136 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_LBN 20
1005812137 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_WIDTH 1
12138
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
12139
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
12140
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
12141
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
1005912142 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
1006012143 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
12144
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_OFST 20
1006112145 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_LBN 22
1006212146 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_WIDTH 1
12147
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
1006312148 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
1006412149 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
12150
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_OFST 20
1006512151 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_LBN 24
1006612152 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_WIDTH 1
10067
-/* Number of FATSOv2 contexts per datapath supported by this NIC. Not present
10068
- * on older firmware (check the length).
12153
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_OFST 20
12154
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_LBN 25
12155
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_WIDTH 1
12156
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
12157
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
12158
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
12159
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
12160
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
12161
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
12162
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_BUNDLE_UPDATE_OFST 20
12163
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_BUNDLE_UPDATE_LBN 28
12164
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_BUNDLE_UPDATE_WIDTH 1
12165
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V3_OFST 20
12166
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V3_LBN 29
12167
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V3_WIDTH 1
12168
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_DYNAMIC_SENSORS_OFST 20
12169
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_DYNAMIC_SENSORS_LBN 30
12170
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_DYNAMIC_SENSORS_WIDTH 1
12171
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
12172
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
12173
+#define        MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
12174
+/* Number of FATSOv2 contexts per datapath supported by this NIC (when
12175
+ * TX_TSO_V2 == 1). Not present on older firmware (check the length).
1006912176  */
1007012177 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
1007112178 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
....@@ -10125,62 +12232,91 @@
1012512232 /* First word of flags. */
1012612233 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_OFST 0
1012712234 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_LEN 4
12235
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_OFST 0
1012812236 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_LBN 3
1012912237 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_WIDTH 1
12238
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_OFST 0
1013012239 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_LBN 4
1013112240 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_WIDTH 1
12241
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_OFST 0
1013212242 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_LBN 5
1013312243 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_WIDTH 1
12244
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
1013412245 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
1013512246 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
12247
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_OFST 0
1013612248 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_LBN 7
1013712249 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
12250
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_OFST 0
1013812251 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_LBN 8
1013912252 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
12253
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_OFST 0
1014012254 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_LBN 9
1014112255 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_WIDTH 1
12256
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
1014212257 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
1014312258 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
12259
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
1014412260 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
1014512261 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
12262
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
1014612263 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
1014712264 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
12265
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_OFST 0
1014812266 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_LBN 13
1014912267 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
12268
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_OFST 0
1015012269 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_LBN 14
1015112270 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_WIDTH 1
12271
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
1015212272 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
1015312273 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
12274
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_OFST 0
1015412275 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_LBN 16
1015512276 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_WIDTH 1
12277
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_OFST 0
1015612278 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_LBN 17
1015712279 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_WIDTH 1
12280
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_OFST 0
1015812281 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_LBN 18
1015912282 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_WIDTH 1
12283
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_OFST 0
1016012284 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_LBN 19
1016112285 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_WIDTH 1
12286
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_OFST 0
1016212287 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_LBN 20
1016312288 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_WIDTH 1
12289
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_OFST 0
1016412290 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_LBN 21
1016512291 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_WIDTH 1
12292
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_OFST 0
1016612293 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_LBN 22
1016712294 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_WIDTH 1
12295
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_OFST 0
1016812296 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_LBN 23
1016912297 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_WIDTH 1
12298
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_OFST 0
1017012299 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_LBN 24
1017112300 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_WIDTH 1
12301
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_OFST 0
1017212302 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_LBN 25
1017312303 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_WIDTH 1
12304
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_OFST 0
1017412305 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_LBN 26
1017512306 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_WIDTH 1
12307
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_OFST 0
1017612308 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_LBN 27
1017712309 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
12310
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_OFST 0
1017812311 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_LBN 28
1017912312 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_WIDTH 1
12313
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
1018012314 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
1018112315 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
12316
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_OFST 0
1018212317 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_LBN 30
1018312318 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_WIDTH 1
12319
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_OFST 0
1018412320 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_LBN 31
1018512321 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_WIDTH 1
1018612322 /* RxDPCPU firmware id. */
....@@ -10241,8 +12377,10 @@
1024112377 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_CSR 0x103
1024212378 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_OFST 8
1024312379 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_LEN 2
12380
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_OFST 8
1024412381 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_LBN 0
1024512382 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_WIDTH 12
12383
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_OFST 8
1024612384 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_LBN 12
1024712385 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
1024812386 /* enum: reserved value - do not use (may indicate alternative interpretation
....@@ -10253,6 +12391,9 @@
1025312391  * development only)
1025412392  */
1025512393 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
12394
+/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
12395
+ */
12396
+#define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
1025612397 /* enum: RX PD firmware with approximately Siena-compatible behaviour
1025712398  * (Huntington development only)
1025812399  */
....@@ -10287,8 +12428,10 @@
1028712428 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
1028812429 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_OFST 10
1028912430 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_LEN 2
12431
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_OFST 10
1029012432 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_LBN 0
1029112433 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_WIDTH 12
12434
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_OFST 10
1029212435 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_LBN 12
1029312436 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
1029412437 /* enum: reserved value - do not use (may indicate alternative interpretation
....@@ -10299,6 +12442,9 @@
1029912442  * development only)
1030012443  */
1030112444 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
12445
+/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
12446
+ */
12447
+#define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
1030212448 /* enum: TX PD firmware with approximately Siena-compatible behaviour
1030312449  * (Huntington development only)
1030412450  */
....@@ -10333,58 +12479,110 @@
1033312479 /* Second word of flags. Not present on older firmware (check the length). */
1033412480 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_OFST 20
1033512481 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_LEN 4
12482
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_OFST 20
1033612483 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_LBN 0
1033712484 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_WIDTH 1
12485
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_OFST 20
1033812486 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_LBN 1
1033912487 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_WIDTH 1
12488
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_OFST 20
1034012489 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_LBN 2
1034112490 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_WIDTH 1
12491
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_OFST 20
1034212492 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_LBN 3
1034312493 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_WIDTH 1
12494
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_OFST 20
1034412495 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_LBN 4
1034512496 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_WIDTH 1
12497
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_OFST 20
1034612498 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_LBN 5
1034712499 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
12500
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
1034812501 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
1034912502 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
12503
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
12504
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
12505
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
12506
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_OFST 20
1035012507 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_LBN 7
1035112508 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_WIDTH 1
12509
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_OFST 20
1035212510 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_LBN 8
1035312511 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
12512
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_OFST 20
1035412513 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_LBN 9
1035512514 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_WIDTH 1
12515
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_OFST 20
1035612516 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_LBN 10
1035712517 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_WIDTH 1
12518
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_OFST 20
1035812519 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_LBN 11
1035912520 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_WIDTH 1
12521
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
1036012522 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
1036112523 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
12524
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_OFST 20
1036212525 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_LBN 13
1036312526 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_WIDTH 1
12527
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_OFST 20
1036412528 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_LBN 14
1036512529 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_WIDTH 1
12530
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_OFST 20
1036612531 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_LBN 15
1036712532 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_WIDTH 1
12533
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_OFST 20
1036812534 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_LBN 16
1036912535 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_WIDTH 1
12536
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_OFST 20
1037012537 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_LBN 17
1037112538 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_WIDTH 1
12539
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
1037212540 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
1037312541 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
12542
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_OFST 20
1037412543 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_LBN 19
1037512544 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_WIDTH 1
12545
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_OFST 20
1037612546 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_LBN 20
1037712547 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_WIDTH 1
12548
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
12549
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
12550
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
12551
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
1037812552 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
1037912553 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
12554
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_OFST 20
1038012555 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_LBN 22
1038112556 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_WIDTH 1
12557
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
1038212558 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
1038312559 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
12560
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_OFST 20
1038412561 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_LBN 24
1038512562 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_WIDTH 1
10386
-/* Number of FATSOv2 contexts per datapath supported by this NIC. Not present
10387
- * on older firmware (check the length).
12563
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_OFST 20
12564
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_LBN 25
12565
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_WIDTH 1
12566
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
12567
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
12568
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
12569
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
12570
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
12571
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
12572
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_BUNDLE_UPDATE_OFST 20
12573
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_BUNDLE_UPDATE_LBN 28
12574
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_BUNDLE_UPDATE_WIDTH 1
12575
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V3_OFST 20
12576
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V3_LBN 29
12577
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V3_WIDTH 1
12578
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_DYNAMIC_SENSORS_OFST 20
12579
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_DYNAMIC_SENSORS_LBN 30
12580
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_DYNAMIC_SENSORS_WIDTH 1
12581
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
12582
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
12583
+#define        MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
12584
+/* Number of FATSOv2 contexts per datapath supported by this NIC (when
12585
+ * TX_TSO_V2 == 1). Not present on older firmware (check the length).
1038812586  */
1038912587 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
1039012588 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
....@@ -10469,62 +12667,91 @@
1046912667 /* First word of flags. */
1047012668 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST 0
1047112669 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_LEN 4
12670
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_OFST 0
1047212671 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_LBN 3
1047312672 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_WIDTH 1
12673
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_OFST 0
1047412674 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_LBN 4
1047512675 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_WIDTH 1
12676
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_OFST 0
1047612677 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_LBN 5
1047712678 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_WIDTH 1
12679
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
1047812680 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
1047912681 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
12682
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_OFST 0
1048012683 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_LBN 7
1048112684 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
12685
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_OFST 0
1048212686 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_LBN 8
1048312687 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
12688
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_OFST 0
1048412689 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_LBN 9
1048512690 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_WIDTH 1
12691
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
1048612692 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
1048712693 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
12694
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
1048812695 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
1048912696 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
12697
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
1049012698 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
1049112699 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
12700
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_OFST 0
1049212701 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_LBN 13
1049312702 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
12703
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_OFST 0
1049412704 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_LBN 14
1049512705 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_WIDTH 1
12706
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
1049612707 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
1049712708 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
12709
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_OFST 0
1049812710 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_LBN 16
1049912711 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_WIDTH 1
12712
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_OFST 0
1050012713 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_LBN 17
1050112714 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_WIDTH 1
12715
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_OFST 0
1050212716 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_LBN 18
1050312717 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_WIDTH 1
12718
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_OFST 0
1050412719 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_LBN 19
1050512720 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_WIDTH 1
12721
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_OFST 0
1050612722 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_LBN 20
1050712723 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_WIDTH 1
12724
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_OFST 0
1050812725 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_LBN 21
1050912726 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_WIDTH 1
12727
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_OFST 0
1051012728 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_LBN 22
1051112729 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_WIDTH 1
12730
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_OFST 0
1051212731 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_LBN 23
1051312732 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_WIDTH 1
12733
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_OFST 0
1051412734 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_LBN 24
1051512735 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_WIDTH 1
12736
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_OFST 0
1051612737 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_LBN 25
1051712738 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_WIDTH 1
12739
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_OFST 0
1051812740 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_LBN 26
1051912741 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_WIDTH 1
12742
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_OFST 0
1052012743 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_LBN 27
1052112744 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
12745
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_OFST 0
1052212746 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_LBN 28
1052312747 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_WIDTH 1
12748
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
1052412749 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
1052512750 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
12751
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_OFST 0
1052612752 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_LBN 30
1052712753 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_WIDTH 1
12754
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_OFST 0
1052812755 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_LBN 31
1052912756 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_WIDTH 1
1053012757 /* RxDPCPU firmware id. */
....@@ -10585,8 +12812,10 @@
1058512812 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_CSR 0x103
1058612813 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_OFST 8
1058712814 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_LEN 2
12815
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_OFST 8
1058812816 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_LBN 0
1058912817 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_WIDTH 12
12818
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_OFST 8
1059012819 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_LBN 12
1059112820 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
1059212821 /* enum: reserved value - do not use (may indicate alternative interpretation
....@@ -10597,6 +12826,9 @@
1059712826  * development only)
1059812827  */
1059912828 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
12829
+/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
12830
+ */
12831
+#define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
1060012832 /* enum: RX PD firmware with approximately Siena-compatible behaviour
1060112833  * (Huntington development only)
1060212834  */
....@@ -10631,8 +12863,10 @@
1063112863 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
1063212864 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_OFST 10
1063312865 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_LEN 2
12866
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_OFST 10
1063412867 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_LBN 0
1063512868 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_WIDTH 12
12869
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_OFST 10
1063612870 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_LBN 12
1063712871 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
1063812872 /* enum: reserved value - do not use (may indicate alternative interpretation
....@@ -10643,6 +12877,9 @@
1064312877  * development only)
1064412878  */
1064512879 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
12880
+/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
12881
+ */
12882
+#define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
1064612883 /* enum: TX PD firmware with approximately Siena-compatible behaviour
1064712884  * (Huntington development only)
1064812885  */
....@@ -10677,58 +12914,110 @@
1067712914 /* Second word of flags. Not present on older firmware (check the length). */
1067812915 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_OFST 20
1067912916 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_LEN 4
12917
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_OFST 20
1068012918 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_LBN 0
1068112919 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_WIDTH 1
12920
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_OFST 20
1068212921 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_LBN 1
1068312922 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_WIDTH 1
12923
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_OFST 20
1068412924 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_LBN 2
1068512925 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_WIDTH 1
12926
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_OFST 20
1068612927 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_LBN 3
1068712928 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_WIDTH 1
12929
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_OFST 20
1068812930 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_LBN 4
1068912931 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_WIDTH 1
12932
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_OFST 20
1069012933 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_LBN 5
1069112934 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
12935
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
1069212936 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
1069312937 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
12938
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
12939
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
12940
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
12941
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_OFST 20
1069412942 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_LBN 7
1069512943 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_WIDTH 1
12944
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_OFST 20
1069612945 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_LBN 8
1069712946 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
12947
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_OFST 20
1069812948 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_LBN 9
1069912949 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_WIDTH 1
12950
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_OFST 20
1070012951 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_LBN 10
1070112952 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_WIDTH 1
12953
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_OFST 20
1070212954 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_LBN 11
1070312955 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_WIDTH 1
12956
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
1070412957 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
1070512958 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
12959
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_OFST 20
1070612960 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_LBN 13
1070712961 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_WIDTH 1
12962
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_OFST 20
1070812963 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_LBN 14
1070912964 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_WIDTH 1
12965
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_OFST 20
1071012966 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_LBN 15
1071112967 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_WIDTH 1
12968
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_OFST 20
1071212969 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_LBN 16
1071312970 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_WIDTH 1
12971
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_OFST 20
1071412972 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_LBN 17
1071512973 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_WIDTH 1
12974
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
1071612975 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
1071712976 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
12977
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_OFST 20
1071812978 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_LBN 19
1071912979 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_WIDTH 1
12980
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_OFST 20
1072012981 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_LBN 20
1072112982 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_WIDTH 1
12983
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
12984
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
12985
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
12986
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
1072212987 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
1072312988 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
12989
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_OFST 20
1072412990 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_LBN 22
1072512991 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_WIDTH 1
12992
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
1072612993 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
1072712994 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
12995
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_OFST 20
1072812996 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_LBN 24
1072912997 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_WIDTH 1
10730
-/* Number of FATSOv2 contexts per datapath supported by this NIC. Not present
10731
- * on older firmware (check the length).
12998
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_OFST 20
12999
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_LBN 25
13000
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_WIDTH 1
13001
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
13002
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
13003
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
13004
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
13005
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
13006
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
13007
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_BUNDLE_UPDATE_OFST 20
13008
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_BUNDLE_UPDATE_LBN 28
13009
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_BUNDLE_UPDATE_WIDTH 1
13010
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V3_OFST 20
13011
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V3_LBN 29
13012
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V3_WIDTH 1
13013
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_DYNAMIC_SENSORS_OFST 20
13014
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_DYNAMIC_SENSORS_LBN 30
13015
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_DYNAMIC_SENSORS_WIDTH 1
13016
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
13017
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
13018
+#define        MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
13019
+/* Number of FATSOv2 contexts per datapath supported by this NIC (when
13020
+ * TX_TSO_V2 == 1). Not present on older firmware (check the length).
1073213021  */
1073313022 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
1073413023 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
....@@ -10816,6 +13105,2422 @@
1081613105 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_OFST 76
1081713106 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_LEN 2
1081813107 
13108
+/* MC_CMD_GET_CAPABILITIES_V5_OUT msgresponse */
13109
+#define    MC_CMD_GET_CAPABILITIES_V5_OUT_LEN 84
13110
+/* First word of flags. */
13111
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_OFST 0
13112
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_LEN 4
13113
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_OFST 0
13114
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_LBN 3
13115
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_WIDTH 1
13116
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_OFST 0
13117
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_LBN 4
13118
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_WIDTH 1
13119
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_OFST 0
13120
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_LBN 5
13121
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_WIDTH 1
13122
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
13123
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
13124
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
13125
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_OFST 0
13126
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_LBN 7
13127
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
13128
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_OFST 0
13129
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_LBN 8
13130
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
13131
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_OFST 0
13132
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_LBN 9
13133
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_WIDTH 1
13134
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
13135
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
13136
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
13137
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
13138
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
13139
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
13140
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
13141
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
13142
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
13143
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_OFST 0
13144
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_LBN 13
13145
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
13146
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_OFST 0
13147
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_LBN 14
13148
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_WIDTH 1
13149
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
13150
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
13151
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
13152
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_OFST 0
13153
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_LBN 16
13154
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_WIDTH 1
13155
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_OFST 0
13156
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_LBN 17
13157
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_WIDTH 1
13158
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_OFST 0
13159
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_LBN 18
13160
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_WIDTH 1
13161
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_OFST 0
13162
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_LBN 19
13163
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_WIDTH 1
13164
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_OFST 0
13165
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_LBN 20
13166
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_WIDTH 1
13167
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_OFST 0
13168
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_LBN 21
13169
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_WIDTH 1
13170
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_OFST 0
13171
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_LBN 22
13172
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_WIDTH 1
13173
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_OFST 0
13174
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_LBN 23
13175
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_WIDTH 1
13176
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_OFST 0
13177
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_LBN 24
13178
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_WIDTH 1
13179
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_OFST 0
13180
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_LBN 25
13181
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_WIDTH 1
13182
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_OFST 0
13183
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_LBN 26
13184
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_WIDTH 1
13185
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_OFST 0
13186
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_LBN 27
13187
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
13188
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_OFST 0
13189
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_LBN 28
13190
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_WIDTH 1
13191
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
13192
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
13193
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
13194
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_OFST 0
13195
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_LBN 30
13196
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_WIDTH 1
13197
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_OFST 0
13198
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_LBN 31
13199
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_WIDTH 1
13200
+/* RxDPCPU firmware id. */
13201
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DPCPU_FW_ID_OFST 4
13202
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DPCPU_FW_ID_LEN 2
13203
+/* enum: Standard RXDP firmware */
13204
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP 0x0
13205
+/* enum: Low latency RXDP firmware */
13206
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_LOW_LATENCY 0x1
13207
+/* enum: Packed stream RXDP firmware */
13208
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_PACKED_STREAM 0x2
13209
+/* enum: Rules engine RXDP firmware */
13210
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_RULES_ENGINE 0x5
13211
+/* enum: DPDK RXDP firmware */
13212
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_DPDK 0x6
13213
+/* enum: BIST RXDP firmware */
13214
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_BIST 0x10a
13215
+/* enum: RXDP Test firmware image 1 */
13216
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
13217
+/* enum: RXDP Test firmware image 2 */
13218
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
13219
+/* enum: RXDP Test firmware image 3 */
13220
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
13221
+/* enum: RXDP Test firmware image 4 */
13222
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
13223
+/* enum: RXDP Test firmware image 5 */
13224
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_BACKPRESSURE 0x105
13225
+/* enum: RXDP Test firmware image 6 */
13226
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
13227
+/* enum: RXDP Test firmware image 7 */
13228
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
13229
+/* enum: RXDP Test firmware image 8 */
13230
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
13231
+/* enum: RXDP Test firmware image 9 */
13232
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
13233
+/* enum: RXDP Test firmware image 10 */
13234
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_SLOW 0x10c
13235
+/* TxDPCPU firmware id. */
13236
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DPCPU_FW_ID_OFST 6
13237
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DPCPU_FW_ID_LEN 2
13238
+/* enum: Standard TXDP firmware */
13239
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP 0x0
13240
+/* enum: Low latency TXDP firmware */
13241
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_LOW_LATENCY 0x1
13242
+/* enum: High packet rate TXDP firmware */
13243
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_HIGH_PACKET_RATE 0x3
13244
+/* enum: Rules engine TXDP firmware */
13245
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_RULES_ENGINE 0x5
13246
+/* enum: DPDK TXDP firmware */
13247
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_DPDK 0x6
13248
+/* enum: BIST TXDP firmware */
13249
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_BIST 0x12d
13250
+/* enum: TXDP Test firmware image 1 */
13251
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
13252
+/* enum: TXDP Test firmware image 2 */
13253
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
13254
+/* enum: TXDP CSR bus test firmware */
13255
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_CSR 0x103
13256
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_OFST 8
13257
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_LEN 2
13258
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_OFST 8
13259
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_LBN 0
13260
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_WIDTH 12
13261
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_OFST 8
13262
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_LBN 12
13263
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
13264
+/* enum: reserved value - do not use (may indicate alternative interpretation
13265
+ * of REV field in future)
13266
+ */
13267
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_RESERVED 0x0
13268
+/* enum: Trivial RX PD firmware for early Huntington development (Huntington
13269
+ * development only)
13270
+ */
13271
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
13272
+/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
13273
+ */
13274
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
13275
+/* enum: RX PD firmware with approximately Siena-compatible behaviour
13276
+ * (Huntington development only)
13277
+ */
13278
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
13279
+/* enum: Full featured RX PD production firmware */
13280
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
13281
+/* enum: (deprecated original name for the FULL_FEATURED variant) */
13282
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_VSWITCH 0x3
13283
+/* enum: siena_compat variant RX PD firmware using PM rather than MAC
13284
+ * (Huntington development only)
13285
+ */
13286
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
13287
+/* enum: Low latency RX PD production firmware */
13288
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
13289
+/* enum: Packed stream RX PD production firmware */
13290
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
13291
+/* enum: RX PD firmware handling layer 2 only for high packet rate performance
13292
+ * tests (Medford development only)
13293
+ */
13294
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
13295
+/* enum: Rules engine RX PD production firmware */
13296
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
13297
+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
13298
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_L3XUDP 0x9
13299
+/* enum: DPDK RX PD production firmware */
13300
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_DPDK 0xa
13301
+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
13302
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
13303
+/* enum: RX PD firmware parsing but not filtering network overlay tunnel
13304
+ * encapsulations (Medford development only)
13305
+ */
13306
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
13307
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_OFST 10
13308
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_LEN 2
13309
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_OFST 10
13310
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_LBN 0
13311
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_WIDTH 12
13312
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_OFST 10
13313
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_LBN 12
13314
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
13315
+/* enum: reserved value - do not use (may indicate alternative interpretation
13316
+ * of REV field in future)
13317
+ */
13318
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_RESERVED 0x0
13319
+/* enum: Trivial TX PD firmware for early Huntington development (Huntington
13320
+ * development only)
13321
+ */
13322
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
13323
+/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
13324
+ */
13325
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
13326
+/* enum: TX PD firmware with approximately Siena-compatible behaviour
13327
+ * (Huntington development only)
13328
+ */
13329
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
13330
+/* enum: Full featured TX PD production firmware */
13331
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
13332
+/* enum: (deprecated original name for the FULL_FEATURED variant) */
13333
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_VSWITCH 0x3
13334
+/* enum: siena_compat variant TX PD firmware using PM rather than MAC
13335
+ * (Huntington development only)
13336
+ */
13337
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
13338
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
13339
+/* enum: TX PD firmware handling layer 2 only for high packet rate performance
13340
+ * tests (Medford development only)
13341
+ */
13342
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
13343
+/* enum: Rules engine TX PD production firmware */
13344
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
13345
+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
13346
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_L3XUDP 0x9
13347
+/* enum: DPDK TX PD production firmware */
13348
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_DPDK 0xa
13349
+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
13350
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
13351
+/* Hardware capabilities of NIC */
13352
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_HW_CAPABILITIES_OFST 12
13353
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_HW_CAPABILITIES_LEN 4
13354
+/* Licensed capabilities */
13355
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_LICENSE_CAPABILITIES_OFST 16
13356
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_LICENSE_CAPABILITIES_LEN 4
13357
+/* Second word of flags. Not present on older firmware (check the length). */
13358
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS2_OFST 20
13359
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS2_LEN 4
13360
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_OFST 20
13361
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_LBN 0
13362
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_WIDTH 1
13363
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_OFST 20
13364
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_LBN 1
13365
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_WIDTH 1
13366
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_OFST 20
13367
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_LBN 2
13368
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_WIDTH 1
13369
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_OFST 20
13370
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_LBN 3
13371
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_WIDTH 1
13372
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_OFST 20
13373
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_LBN 4
13374
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_WIDTH 1
13375
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_OFST 20
13376
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_LBN 5
13377
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
13378
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
13379
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
13380
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
13381
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
13382
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
13383
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
13384
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_OFST 20
13385
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_LBN 7
13386
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_WIDTH 1
13387
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_OFST 20
13388
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_LBN 8
13389
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
13390
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_OFST 20
13391
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_LBN 9
13392
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_WIDTH 1
13393
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_OFST 20
13394
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_LBN 10
13395
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_WIDTH 1
13396
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_OFST 20
13397
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_LBN 11
13398
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_WIDTH 1
13399
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
13400
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
13401
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
13402
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_OFST 20
13403
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_LBN 13
13404
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_WIDTH 1
13405
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_OFST 20
13406
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_LBN 14
13407
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_WIDTH 1
13408
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_OFST 20
13409
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_LBN 15
13410
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_WIDTH 1
13411
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_OFST 20
13412
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_LBN 16
13413
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_WIDTH 1
13414
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_OFST 20
13415
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_LBN 17
13416
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_WIDTH 1
13417
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
13418
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
13419
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
13420
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_OFST 20
13421
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_LBN 19
13422
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_WIDTH 1
13423
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_OFST 20
13424
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_LBN 20
13425
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_WIDTH 1
13426
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
13427
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
13428
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
13429
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
13430
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
13431
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
13432
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_OFST 20
13433
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_LBN 22
13434
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_WIDTH 1
13435
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
13436
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
13437
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
13438
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_OFST 20
13439
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_LBN 24
13440
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_WIDTH 1
13441
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_OFST 20
13442
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_LBN 25
13443
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_WIDTH 1
13444
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
13445
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
13446
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
13447
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
13448
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
13449
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
13450
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_BUNDLE_UPDATE_OFST 20
13451
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_BUNDLE_UPDATE_LBN 28
13452
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_BUNDLE_UPDATE_WIDTH 1
13453
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V3_OFST 20
13454
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V3_LBN 29
13455
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V3_WIDTH 1
13456
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_DYNAMIC_SENSORS_OFST 20
13457
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_DYNAMIC_SENSORS_LBN 30
13458
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_DYNAMIC_SENSORS_WIDTH 1
13459
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
13460
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
13461
+#define        MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
13462
+/* Number of FATSOv2 contexts per datapath supported by this NIC (when
13463
+ * TX_TSO_V2 == 1). Not present on older firmware (check the length).
13464
+ */
13465
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
13466
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
13467
+/* One byte per PF containing the number of the external port assigned to this
13468
+ * PF, indexed by PF number. Special values indicate that a PF is either not
13469
+ * present or not assigned.
13470
+ */
13471
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
13472
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
13473
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
13474
+/* enum: The caller is not permitted to access information on this PF. */
13475
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff
13476
+/* enum: PF does not exist. */
13477
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe
13478
+/* enum: PF does exist but is not assigned to any external port. */
13479
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_ASSIGNED 0xfd
13480
+/* enum: This value indicates that PF is assigned, but it cannot be expressed
13481
+ * in this field. It is intended for a possible future situation where a more
13482
+ * complex scheme of PFs to ports mapping is being used. The future driver
13483
+ * should look for a new field supporting the new scheme. The current/old
13484
+ * driver should treat this value as PF_NOT_ASSIGNED.
13485
+ */
13486
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
13487
+/* One byte per PF containing the number of its VFs, indexed by PF number. A
13488
+ * special value indicates that a PF is not present.
13489
+ */
13490
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VFS_PER_PF_OFST 42
13491
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VFS_PER_PF_LEN 1
13492
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VFS_PER_PF_NUM 16
13493
+/* enum: The caller is not permitted to access information on this PF. */
13494
+/*               MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff */
13495
+/* enum: PF does not exist. */
13496
+/*               MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe */
13497
+/* Number of VIs available for each external port */
13498
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_OFST 58
13499
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_LEN 2
13500
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_NUM 4
13501
+/* Size of RX descriptor cache expressed as binary logarithm The actual size
13502
+ * equals (2 ^ RX_DESC_CACHE_SIZE)
13503
+ */
13504
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DESC_CACHE_SIZE_OFST 66
13505
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DESC_CACHE_SIZE_LEN 1
13506
+/* Size of TX descriptor cache expressed as binary logarithm The actual size
13507
+ * equals (2 ^ TX_DESC_CACHE_SIZE)
13508
+ */
13509
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DESC_CACHE_SIZE_OFST 67
13510
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DESC_CACHE_SIZE_LEN 1
13511
+/* Total number of available PIO buffers */
13512
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_PIO_BUFFS_OFST 68
13513
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_PIO_BUFFS_LEN 2
13514
+/* Size of a single PIO buffer */
13515
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_SIZE_PIO_BUFF_OFST 70
13516
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_SIZE_PIO_BUFF_LEN 2
13517
+/* On chips later than Medford the amount of address space assigned to each VI
13518
+ * is configurable. This is a global setting that the driver must query to
13519
+ * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
13520
+ * with 8k VI windows.
13521
+ */
13522
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_OFST 72
13523
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_LEN 1
13524
+/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
13525
+ * CTPIO is not mapped.
13526
+ */
13527
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_8K 0x0
13528
+/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
13529
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_16K 0x1
13530
+/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
13531
+#define          MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_64K 0x2
13532
+/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
13533
+ * (SF-115995-SW) in the present configuration of firmware and port mode.
13534
+ */
13535
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
13536
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
13537
+/* Number of buffers per adapter that can be used for VFIFO Stuffing
13538
+ * (SF-115995-SW) in the present configuration of firmware and port mode.
13539
+ */
13540
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
13541
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
13542
+/* Entry count in the MAC stats array, including the final GENERATION_END
13543
+ * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
13544
+ * hold at least this many 64-bit stats values, if they wish to receive all
13545
+ * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
13546
+ * stats array returned will be truncated.
13547
+ */
13548
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_NUM_STATS_OFST 76
13549
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_NUM_STATS_LEN 2
13550
+/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field
13551
+ * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
13552
+ */
13553
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX_OFST 80
13554
+#define       MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX_LEN 4
13555
+
13556
+/* MC_CMD_GET_CAPABILITIES_V6_OUT msgresponse */
13557
+#define    MC_CMD_GET_CAPABILITIES_V6_OUT_LEN 148
13558
+/* First word of flags. */
13559
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS1_OFST 0
13560
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS1_LEN 4
13561
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_OFST 0
13562
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_LBN 3
13563
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_WIDTH 1
13564
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_OFST 0
13565
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_LBN 4
13566
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_WIDTH 1
13567
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_OFST 0
13568
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_LBN 5
13569
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_WIDTH 1
13570
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
13571
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
13572
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
13573
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_OFST 0
13574
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_LBN 7
13575
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
13576
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_OFST 0
13577
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_LBN 8
13578
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
13579
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_OFST 0
13580
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_LBN 9
13581
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_WIDTH 1
13582
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
13583
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
13584
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
13585
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
13586
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
13587
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
13588
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
13589
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
13590
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
13591
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_OFST 0
13592
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_LBN 13
13593
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
13594
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_QBB_OFST 0
13595
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_QBB_LBN 14
13596
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_QBB_WIDTH 1
13597
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
13598
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
13599
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
13600
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_OFST 0
13601
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_LBN 16
13602
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_WIDTH 1
13603
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_OFST 0
13604
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_LBN 17
13605
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_WIDTH 1
13606
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_OFST 0
13607
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_LBN 18
13608
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_WIDTH 1
13609
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_OFST 0
13610
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_LBN 19
13611
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_WIDTH 1
13612
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_OFST 0
13613
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_LBN 20
13614
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_WIDTH 1
13615
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_OFST 0
13616
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_LBN 21
13617
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_WIDTH 1
13618
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_OFST 0
13619
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_LBN 22
13620
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_WIDTH 1
13621
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_OFST 0
13622
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_LBN 23
13623
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_WIDTH 1
13624
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_OFST 0
13625
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_LBN 24
13626
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_WIDTH 1
13627
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_OFST 0
13628
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_LBN 25
13629
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_WIDTH 1
13630
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_OFST 0
13631
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_LBN 26
13632
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_WIDTH 1
13633
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_OFST 0
13634
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_LBN 27
13635
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
13636
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_OFST 0
13637
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_LBN 28
13638
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_WIDTH 1
13639
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
13640
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
13641
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
13642
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_OFST 0
13643
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_LBN 30
13644
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_WIDTH 1
13645
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_OFST 0
13646
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_LBN 31
13647
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_WIDTH 1
13648
+/* RxDPCPU firmware id. */
13649
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DPCPU_FW_ID_OFST 4
13650
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DPCPU_FW_ID_LEN 2
13651
+/* enum: Standard RXDP firmware */
13652
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP 0x0
13653
+/* enum: Low latency RXDP firmware */
13654
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_LOW_LATENCY 0x1
13655
+/* enum: Packed stream RXDP firmware */
13656
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_PACKED_STREAM 0x2
13657
+/* enum: Rules engine RXDP firmware */
13658
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_RULES_ENGINE 0x5
13659
+/* enum: DPDK RXDP firmware */
13660
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_DPDK 0x6
13661
+/* enum: BIST RXDP firmware */
13662
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_BIST 0x10a
13663
+/* enum: RXDP Test firmware image 1 */
13664
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
13665
+/* enum: RXDP Test firmware image 2 */
13666
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
13667
+/* enum: RXDP Test firmware image 3 */
13668
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
13669
+/* enum: RXDP Test firmware image 4 */
13670
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
13671
+/* enum: RXDP Test firmware image 5 */
13672
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_BACKPRESSURE 0x105
13673
+/* enum: RXDP Test firmware image 6 */
13674
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
13675
+/* enum: RXDP Test firmware image 7 */
13676
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
13677
+/* enum: RXDP Test firmware image 8 */
13678
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
13679
+/* enum: RXDP Test firmware image 9 */
13680
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
13681
+/* enum: RXDP Test firmware image 10 */
13682
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_SLOW 0x10c
13683
+/* TxDPCPU firmware id. */
13684
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DPCPU_FW_ID_OFST 6
13685
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DPCPU_FW_ID_LEN 2
13686
+/* enum: Standard TXDP firmware */
13687
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP 0x0
13688
+/* enum: Low latency TXDP firmware */
13689
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_LOW_LATENCY 0x1
13690
+/* enum: High packet rate TXDP firmware */
13691
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_HIGH_PACKET_RATE 0x3
13692
+/* enum: Rules engine TXDP firmware */
13693
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_RULES_ENGINE 0x5
13694
+/* enum: DPDK TXDP firmware */
13695
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_DPDK 0x6
13696
+/* enum: BIST TXDP firmware */
13697
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_BIST 0x12d
13698
+/* enum: TXDP Test firmware image 1 */
13699
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
13700
+/* enum: TXDP Test firmware image 2 */
13701
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
13702
+/* enum: TXDP CSR bus test firmware */
13703
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_CSR 0x103
13704
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_OFST 8
13705
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_LEN 2
13706
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_OFST 8
13707
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_LBN 0
13708
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_WIDTH 12
13709
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_OFST 8
13710
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_LBN 12
13711
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
13712
+/* enum: reserved value - do not use (may indicate alternative interpretation
13713
+ * of REV field in future)
13714
+ */
13715
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_RESERVED 0x0
13716
+/* enum: Trivial RX PD firmware for early Huntington development (Huntington
13717
+ * development only)
13718
+ */
13719
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
13720
+/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
13721
+ */
13722
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
13723
+/* enum: RX PD firmware with approximately Siena-compatible behaviour
13724
+ * (Huntington development only)
13725
+ */
13726
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
13727
+/* enum: Full featured RX PD production firmware */
13728
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
13729
+/* enum: (deprecated original name for the FULL_FEATURED variant) */
13730
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_VSWITCH 0x3
13731
+/* enum: siena_compat variant RX PD firmware using PM rather than MAC
13732
+ * (Huntington development only)
13733
+ */
13734
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
13735
+/* enum: Low latency RX PD production firmware */
13736
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
13737
+/* enum: Packed stream RX PD production firmware */
13738
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
13739
+/* enum: RX PD firmware handling layer 2 only for high packet rate performance
13740
+ * tests (Medford development only)
13741
+ */
13742
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
13743
+/* enum: Rules engine RX PD production firmware */
13744
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
13745
+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
13746
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_L3XUDP 0x9
13747
+/* enum: DPDK RX PD production firmware */
13748
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_DPDK 0xa
13749
+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
13750
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
13751
+/* enum: RX PD firmware parsing but not filtering network overlay tunnel
13752
+ * encapsulations (Medford development only)
13753
+ */
13754
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
13755
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_OFST 10
13756
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_LEN 2
13757
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_OFST 10
13758
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_LBN 0
13759
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_WIDTH 12
13760
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_OFST 10
13761
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_LBN 12
13762
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
13763
+/* enum: reserved value - do not use (may indicate alternative interpretation
13764
+ * of REV field in future)
13765
+ */
13766
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_RESERVED 0x0
13767
+/* enum: Trivial TX PD firmware for early Huntington development (Huntington
13768
+ * development only)
13769
+ */
13770
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
13771
+/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
13772
+ */
13773
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
13774
+/* enum: TX PD firmware with approximately Siena-compatible behaviour
13775
+ * (Huntington development only)
13776
+ */
13777
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
13778
+/* enum: Full featured TX PD production firmware */
13779
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
13780
+/* enum: (deprecated original name for the FULL_FEATURED variant) */
13781
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_VSWITCH 0x3
13782
+/* enum: siena_compat variant TX PD firmware using PM rather than MAC
13783
+ * (Huntington development only)
13784
+ */
13785
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
13786
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
13787
+/* enum: TX PD firmware handling layer 2 only for high packet rate performance
13788
+ * tests (Medford development only)
13789
+ */
13790
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
13791
+/* enum: Rules engine TX PD production firmware */
13792
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
13793
+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
13794
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_L3XUDP 0x9
13795
+/* enum: DPDK TX PD production firmware */
13796
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_DPDK 0xa
13797
+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
13798
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
13799
+/* Hardware capabilities of NIC */
13800
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_HW_CAPABILITIES_OFST 12
13801
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_HW_CAPABILITIES_LEN 4
13802
+/* Licensed capabilities */
13803
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_LICENSE_CAPABILITIES_OFST 16
13804
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_LICENSE_CAPABILITIES_LEN 4
13805
+/* Second word of flags. Not present on older firmware (check the length). */
13806
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS2_OFST 20
13807
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS2_LEN 4
13808
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_OFST 20
13809
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_LBN 0
13810
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_WIDTH 1
13811
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_OFST 20
13812
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_LBN 1
13813
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_WIDTH 1
13814
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_EVQ_TIMER_CTRL_OFST 20
13815
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_EVQ_TIMER_CTRL_LBN 2
13816
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_EVQ_TIMER_CTRL_WIDTH 1
13817
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_EVENT_CUT_THROUGH_OFST 20
13818
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_EVENT_CUT_THROUGH_LBN 3
13819
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_EVENT_CUT_THROUGH_WIDTH 1
13820
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_OFST 20
13821
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_LBN 4
13822
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_WIDTH 1
13823
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VFIFO_ULL_MODE_OFST 20
13824
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VFIFO_ULL_MODE_LBN 5
13825
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
13826
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
13827
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
13828
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
13829
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
13830
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
13831
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
13832
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_V2_OFST 20
13833
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_V2_LBN 7
13834
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_V2_WIDTH 1
13835
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_TIMESTAMPING_OFST 20
13836
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_TIMESTAMPING_LBN 8
13837
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
13838
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TIMESTAMP_OFST 20
13839
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TIMESTAMP_LBN 9
13840
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TIMESTAMP_WIDTH 1
13841
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_SNIFF_OFST 20
13842
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_SNIFF_LBN 10
13843
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RX_SNIFF_WIDTH 1
13844
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_SNIFF_OFST 20
13845
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_SNIFF_LBN 11
13846
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_SNIFF_WIDTH 1
13847
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
13848
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
13849
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
13850
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_BACKGROUND_OFST 20
13851
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_BACKGROUND_LBN 13
13852
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_BACKGROUND_WIDTH 1
13853
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_DB_RETURN_OFST 20
13854
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_DB_RETURN_LBN 14
13855
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_DB_RETURN_WIDTH 1
13856
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_CTPIO_OFST 20
13857
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_CTPIO_LBN 15
13858
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_CTPIO_WIDTH 1
13859
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_SUPPORT_OFST 20
13860
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_SUPPORT_LBN 16
13861
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_SUPPORT_WIDTH 1
13862
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_BOUND_OFST 20
13863
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_BOUND_LBN 17
13864
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_BOUND_WIDTH 1
13865
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
13866
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
13867
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
13868
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_FLAG_OFST 20
13869
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_FLAG_LBN 19
13870
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_FLAG_WIDTH 1
13871
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_OFST 20
13872
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_LBN 20
13873
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_WIDTH 1
13874
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
13875
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
13876
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
13877
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
13878
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
13879
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
13880
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_L3XUDP_SUPPORT_OFST 20
13881
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_L3XUDP_SUPPORT_LBN 22
13882
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_L3XUDP_SUPPORT_WIDTH 1
13883
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
13884
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
13885
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
13886
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_VI_SPREADING_OFST 20
13887
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_VI_SPREADING_LBN 24
13888
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_VI_SPREADING_WIDTH 1
13889
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_HLB_IDLE_OFST 20
13890
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_HLB_IDLE_LBN 25
13891
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_HLB_IDLE_WIDTH 1
13892
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
13893
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
13894
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
13895
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
13896
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
13897
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
13898
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_BUNDLE_UPDATE_OFST 20
13899
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_BUNDLE_UPDATE_LBN 28
13900
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_BUNDLE_UPDATE_WIDTH 1
13901
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V3_OFST 20
13902
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V3_LBN 29
13903
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V3_WIDTH 1
13904
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_DYNAMIC_SENSORS_OFST 20
13905
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_DYNAMIC_SENSORS_LBN 30
13906
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_DYNAMIC_SENSORS_WIDTH 1
13907
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
13908
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
13909
+#define        MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
13910
+/* Number of FATSOv2 contexts per datapath supported by this NIC (when
13911
+ * TX_TSO_V2 == 1). Not present on older firmware (check the length).
13912
+ */
13913
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
13914
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
13915
+/* One byte per PF containing the number of the external port assigned to this
13916
+ * PF, indexed by PF number. Special values indicate that a PF is either not
13917
+ * present or not assigned.
13918
+ */
13919
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
13920
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
13921
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
13922
+/* enum: The caller is not permitted to access information on this PF. */
13923
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_ACCESS_NOT_PERMITTED 0xff
13924
+/* enum: PF does not exist. */
13925
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_PRESENT 0xfe
13926
+/* enum: PF does exist but is not assigned to any external port. */
13927
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_ASSIGNED 0xfd
13928
+/* enum: This value indicates that PF is assigned, but it cannot be expressed
13929
+ * in this field. It is intended for a possible future situation where a more
13930
+ * complex scheme of PFs to ports mapping is being used. The future driver
13931
+ * should look for a new field supporting the new scheme. The current/old
13932
+ * driver should treat this value as PF_NOT_ASSIGNED.
13933
+ */
13934
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
13935
+/* One byte per PF containing the number of its VFs, indexed by PF number. A
13936
+ * special value indicates that a PF is not present.
13937
+ */
13938
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VFS_PER_PF_OFST 42
13939
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VFS_PER_PF_LEN 1
13940
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VFS_PER_PF_NUM 16
13941
+/* enum: The caller is not permitted to access information on this PF. */
13942
+/*               MC_CMD_GET_CAPABILITIES_V6_OUT_ACCESS_NOT_PERMITTED 0xff */
13943
+/* enum: PF does not exist. */
13944
+/*               MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_PRESENT 0xfe */
13945
+/* Number of VIs available for each external port */
13946
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_OFST 58
13947
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_LEN 2
13948
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_NUM 4
13949
+/* Size of RX descriptor cache expressed as binary logarithm The actual size
13950
+ * equals (2 ^ RX_DESC_CACHE_SIZE)
13951
+ */
13952
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DESC_CACHE_SIZE_OFST 66
13953
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DESC_CACHE_SIZE_LEN 1
13954
+/* Size of TX descriptor cache expressed as binary logarithm The actual size
13955
+ * equals (2 ^ TX_DESC_CACHE_SIZE)
13956
+ */
13957
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DESC_CACHE_SIZE_OFST 67
13958
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DESC_CACHE_SIZE_LEN 1
13959
+/* Total number of available PIO buffers */
13960
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_PIO_BUFFS_OFST 68
13961
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_PIO_BUFFS_LEN 2
13962
+/* Size of a single PIO buffer */
13963
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_SIZE_PIO_BUFF_OFST 70
13964
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_SIZE_PIO_BUFF_LEN 2
13965
+/* On chips later than Medford the amount of address space assigned to each VI
13966
+ * is configurable. This is a global setting that the driver must query to
13967
+ * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
13968
+ * with 8k VI windows.
13969
+ */
13970
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_OFST 72
13971
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_LEN 1
13972
+/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
13973
+ * CTPIO is not mapped.
13974
+ */
13975
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_8K 0x0
13976
+/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
13977
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_16K 0x1
13978
+/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
13979
+#define          MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_64K 0x2
13980
+/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
13981
+ * (SF-115995-SW) in the present configuration of firmware and port mode.
13982
+ */
13983
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
13984
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
13985
+/* Number of buffers per adapter that can be used for VFIFO Stuffing
13986
+ * (SF-115995-SW) in the present configuration of firmware and port mode.
13987
+ */
13988
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
13989
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
13990
+/* Entry count in the MAC stats array, including the final GENERATION_END
13991
+ * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
13992
+ * hold at least this many 64-bit stats values, if they wish to receive all
13993
+ * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
13994
+ * stats array returned will be truncated.
13995
+ */
13996
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_NUM_STATS_OFST 76
13997
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_NUM_STATS_LEN 2
13998
+/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field
13999
+ * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
14000
+ */
14001
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_MAX_OFST 80
14002
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_MAX_LEN 4
14003
+/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in
14004
+ * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when
14005
+ * they create an RX queue. Due to hardware limitations, only a small number of
14006
+ * different buffer sizes may be available concurrently. Nonzero entries in
14007
+ * this array are the sizes of buffers which the system guarantees will be
14008
+ * available for use. If the list is empty, there are no limitations on
14009
+ * concurrent buffer sizes.
14010
+ */
14011
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84
14012
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
14013
+#define       MC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16
14014
+
14015
+/* MC_CMD_GET_CAPABILITIES_V7_OUT msgresponse */
14016
+#define    MC_CMD_GET_CAPABILITIES_V7_OUT_LEN 152
14017
+/* First word of flags. */
14018
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS1_OFST 0
14019
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS1_LEN 4
14020
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_OFST 0
14021
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_LBN 3
14022
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_WIDTH 1
14023
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_OFST 0
14024
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_LBN 4
14025
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_WIDTH 1
14026
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_OFST 0
14027
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_LBN 5
14028
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_WIDTH 1
14029
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
14030
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
14031
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
14032
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_OFST 0
14033
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_LBN 7
14034
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
14035
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_OFST 0
14036
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_LBN 8
14037
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
14038
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_OFST 0
14039
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_LBN 9
14040
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_WIDTH 1
14041
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
14042
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
14043
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
14044
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
14045
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
14046
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
14047
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
14048
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
14049
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
14050
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_OFST 0
14051
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_LBN 13
14052
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
14053
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_QBB_OFST 0
14054
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_QBB_LBN 14
14055
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_QBB_WIDTH 1
14056
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
14057
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
14058
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
14059
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_OFST 0
14060
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_LBN 16
14061
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_WIDTH 1
14062
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_OFST 0
14063
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_LBN 17
14064
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_WIDTH 1
14065
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_OFST 0
14066
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_LBN 18
14067
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_WIDTH 1
14068
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_OFST 0
14069
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_LBN 19
14070
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_WIDTH 1
14071
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_OFST 0
14072
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_LBN 20
14073
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_WIDTH 1
14074
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_OFST 0
14075
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_LBN 21
14076
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_WIDTH 1
14077
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_OFST 0
14078
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_LBN 22
14079
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_WIDTH 1
14080
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_OFST 0
14081
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_LBN 23
14082
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_WIDTH 1
14083
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_OFST 0
14084
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_LBN 24
14085
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_WIDTH 1
14086
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_OFST 0
14087
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_LBN 25
14088
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_WIDTH 1
14089
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_OFST 0
14090
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_LBN 26
14091
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_WIDTH 1
14092
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_OFST 0
14093
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_LBN 27
14094
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
14095
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_OFST 0
14096
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_LBN 28
14097
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_WIDTH 1
14098
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
14099
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
14100
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
14101
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_OFST 0
14102
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_LBN 30
14103
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_WIDTH 1
14104
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_OFST 0
14105
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_LBN 31
14106
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_WIDTH 1
14107
+/* RxDPCPU firmware id. */
14108
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DPCPU_FW_ID_OFST 4
14109
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DPCPU_FW_ID_LEN 2
14110
+/* enum: Standard RXDP firmware */
14111
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP 0x0
14112
+/* enum: Low latency RXDP firmware */
14113
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_LOW_LATENCY 0x1
14114
+/* enum: Packed stream RXDP firmware */
14115
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_PACKED_STREAM 0x2
14116
+/* enum: Rules engine RXDP firmware */
14117
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_RULES_ENGINE 0x5
14118
+/* enum: DPDK RXDP firmware */
14119
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_DPDK 0x6
14120
+/* enum: BIST RXDP firmware */
14121
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_BIST 0x10a
14122
+/* enum: RXDP Test firmware image 1 */
14123
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
14124
+/* enum: RXDP Test firmware image 2 */
14125
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
14126
+/* enum: RXDP Test firmware image 3 */
14127
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
14128
+/* enum: RXDP Test firmware image 4 */
14129
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
14130
+/* enum: RXDP Test firmware image 5 */
14131
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_BACKPRESSURE 0x105
14132
+/* enum: RXDP Test firmware image 6 */
14133
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
14134
+/* enum: RXDP Test firmware image 7 */
14135
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
14136
+/* enum: RXDP Test firmware image 8 */
14137
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
14138
+/* enum: RXDP Test firmware image 9 */
14139
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
14140
+/* enum: RXDP Test firmware image 10 */
14141
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_SLOW 0x10c
14142
+/* TxDPCPU firmware id. */
14143
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DPCPU_FW_ID_OFST 6
14144
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DPCPU_FW_ID_LEN 2
14145
+/* enum: Standard TXDP firmware */
14146
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP 0x0
14147
+/* enum: Low latency TXDP firmware */
14148
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_LOW_LATENCY 0x1
14149
+/* enum: High packet rate TXDP firmware */
14150
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_HIGH_PACKET_RATE 0x3
14151
+/* enum: Rules engine TXDP firmware */
14152
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_RULES_ENGINE 0x5
14153
+/* enum: DPDK TXDP firmware */
14154
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_DPDK 0x6
14155
+/* enum: BIST TXDP firmware */
14156
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_BIST 0x12d
14157
+/* enum: TXDP Test firmware image 1 */
14158
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
14159
+/* enum: TXDP Test firmware image 2 */
14160
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
14161
+/* enum: TXDP CSR bus test firmware */
14162
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_CSR 0x103
14163
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_OFST 8
14164
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_LEN 2
14165
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_REV_OFST 8
14166
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_REV_LBN 0
14167
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_REV_WIDTH 12
14168
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_TYPE_OFST 8
14169
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_TYPE_LBN 12
14170
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
14171
+/* enum: reserved value - do not use (may indicate alternative interpretation
14172
+ * of REV field in future)
14173
+ */
14174
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_RESERVED 0x0
14175
+/* enum: Trivial RX PD firmware for early Huntington development (Huntington
14176
+ * development only)
14177
+ */
14178
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
14179
+/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
14180
+ */
14181
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14182
+/* enum: RX PD firmware with approximately Siena-compatible behaviour
14183
+ * (Huntington development only)
14184
+ */
14185
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
14186
+/* enum: Full featured RX PD production firmware */
14187
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
14188
+/* enum: (deprecated original name for the FULL_FEATURED variant) */
14189
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_VSWITCH 0x3
14190
+/* enum: siena_compat variant RX PD firmware using PM rather than MAC
14191
+ * (Huntington development only)
14192
+ */
14193
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14194
+/* enum: Low latency RX PD production firmware */
14195
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
14196
+/* enum: Packed stream RX PD production firmware */
14197
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
14198
+/* enum: RX PD firmware handling layer 2 only for high packet rate performance
14199
+ * tests (Medford development only)
14200
+ */
14201
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
14202
+/* enum: Rules engine RX PD production firmware */
14203
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
14204
+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14205
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_L3XUDP 0x9
14206
+/* enum: DPDK RX PD production firmware */
14207
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_DPDK 0xa
14208
+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
14209
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14210
+/* enum: RX PD firmware parsing but not filtering network overlay tunnel
14211
+ * encapsulations (Medford development only)
14212
+ */
14213
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
14214
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_OFST 10
14215
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_LEN 2
14216
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_REV_OFST 10
14217
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_REV_LBN 0
14218
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_REV_WIDTH 12
14219
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_TYPE_OFST 10
14220
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_TYPE_LBN 12
14221
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
14222
+/* enum: reserved value - do not use (may indicate alternative interpretation
14223
+ * of REV field in future)
14224
+ */
14225
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_RESERVED 0x0
14226
+/* enum: Trivial TX PD firmware for early Huntington development (Huntington
14227
+ * development only)
14228
+ */
14229
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
14230
+/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
14231
+ */
14232
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14233
+/* enum: TX PD firmware with approximately Siena-compatible behaviour
14234
+ * (Huntington development only)
14235
+ */
14236
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
14237
+/* enum: Full featured TX PD production firmware */
14238
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
14239
+/* enum: (deprecated original name for the FULL_FEATURED variant) */
14240
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_VSWITCH 0x3
14241
+/* enum: siena_compat variant TX PD firmware using PM rather than MAC
14242
+ * (Huntington development only)
14243
+ */
14244
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14245
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
14246
+/* enum: TX PD firmware handling layer 2 only for high packet rate performance
14247
+ * tests (Medford development only)
14248
+ */
14249
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
14250
+/* enum: Rules engine TX PD production firmware */
14251
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
14252
+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14253
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_L3XUDP 0x9
14254
+/* enum: DPDK TX PD production firmware */
14255
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_DPDK 0xa
14256
+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
14257
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14258
+/* Hardware capabilities of NIC */
14259
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_HW_CAPABILITIES_OFST 12
14260
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_HW_CAPABILITIES_LEN 4
14261
+/* Licensed capabilities */
14262
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_LICENSE_CAPABILITIES_OFST 16
14263
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_LICENSE_CAPABILITIES_LEN 4
14264
+/* Second word of flags. Not present on older firmware (check the length). */
14265
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS2_OFST 20
14266
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS2_LEN 4
14267
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_OFST 20
14268
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_LBN 0
14269
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_WIDTH 1
14270
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_ENCAP_OFST 20
14271
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_ENCAP_LBN 1
14272
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_ENCAP_WIDTH 1
14273
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_EVQ_TIMER_CTRL_OFST 20
14274
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_EVQ_TIMER_CTRL_LBN 2
14275
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_EVQ_TIMER_CTRL_WIDTH 1
14276
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_EVENT_CUT_THROUGH_OFST 20
14277
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_EVENT_CUT_THROUGH_LBN 3
14278
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_EVENT_CUT_THROUGH_WIDTH 1
14279
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_OFST 20
14280
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_LBN 4
14281
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_WIDTH 1
14282
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VFIFO_ULL_MODE_OFST 20
14283
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VFIFO_ULL_MODE_LBN 5
14284
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
14285
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
14286
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
14287
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
14288
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
14289
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
14290
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
14291
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_V2_OFST 20
14292
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_V2_LBN 7
14293
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_V2_WIDTH 1
14294
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_TIMESTAMPING_OFST 20
14295
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_TIMESTAMPING_LBN 8
14296
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
14297
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TIMESTAMP_OFST 20
14298
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TIMESTAMP_LBN 9
14299
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TIMESTAMP_WIDTH 1
14300
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_SNIFF_OFST 20
14301
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_SNIFF_LBN 10
14302
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_SNIFF_WIDTH 1
14303
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_SNIFF_OFST 20
14304
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_SNIFF_LBN 11
14305
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_SNIFF_WIDTH 1
14306
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
14307
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
14308
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
14309
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_BACKGROUND_OFST 20
14310
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_BACKGROUND_LBN 13
14311
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_BACKGROUND_WIDTH 1
14312
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_DB_RETURN_OFST 20
14313
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_DB_RETURN_LBN 14
14314
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_DB_RETURN_WIDTH 1
14315
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_CTPIO_OFST 20
14316
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_CTPIO_LBN 15
14317
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_CTPIO_WIDTH 1
14318
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_SUPPORT_OFST 20
14319
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_SUPPORT_LBN 16
14320
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_SUPPORT_WIDTH 1
14321
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_BOUND_OFST 20
14322
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_BOUND_LBN 17
14323
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_BOUND_WIDTH 1
14324
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
14325
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
14326
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
14327
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_FLAG_OFST 20
14328
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_FLAG_LBN 19
14329
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_FLAG_WIDTH 1
14330
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_OFST 20
14331
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_LBN 20
14332
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_WIDTH 1
14333
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
14334
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
14335
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
14336
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
14337
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
14338
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
14339
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_L3XUDP_SUPPORT_OFST 20
14340
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_L3XUDP_SUPPORT_LBN 22
14341
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_L3XUDP_SUPPORT_WIDTH 1
14342
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
14343
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
14344
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
14345
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_VI_SPREADING_OFST 20
14346
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_VI_SPREADING_LBN 24
14347
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_VI_SPREADING_WIDTH 1
14348
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_HLB_IDLE_OFST 20
14349
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_HLB_IDLE_LBN 25
14350
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_HLB_IDLE_WIDTH 1
14351
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
14352
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
14353
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
14354
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
14355
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
14356
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
14357
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_BUNDLE_UPDATE_OFST 20
14358
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_BUNDLE_UPDATE_LBN 28
14359
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_BUNDLE_UPDATE_WIDTH 1
14360
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V3_OFST 20
14361
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V3_LBN 29
14362
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V3_WIDTH 1
14363
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_SENSORS_OFST 20
14364
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_SENSORS_LBN 30
14365
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_SENSORS_WIDTH 1
14366
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
14367
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
14368
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
14369
+/* Number of FATSOv2 contexts per datapath supported by this NIC (when
14370
+ * TX_TSO_V2 == 1). Not present on older firmware (check the length).
14371
+ */
14372
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
14373
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
14374
+/* One byte per PF containing the number of the external port assigned to this
14375
+ * PF, indexed by PF number. Special values indicate that a PF is either not
14376
+ * present or not assigned.
14377
+ */
14378
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
14379
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
14380
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
14381
+/* enum: The caller is not permitted to access information on this PF. */
14382
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_ACCESS_NOT_PERMITTED 0xff
14383
+/* enum: PF does not exist. */
14384
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_PRESENT 0xfe
14385
+/* enum: PF does exist but is not assigned to any external port. */
14386
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_ASSIGNED 0xfd
14387
+/* enum: This value indicates that PF is assigned, but it cannot be expressed
14388
+ * in this field. It is intended for a possible future situation where a more
14389
+ * complex scheme of PFs to ports mapping is being used. The future driver
14390
+ * should look for a new field supporting the new scheme. The current/old
14391
+ * driver should treat this value as PF_NOT_ASSIGNED.
14392
+ */
14393
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
14394
+/* One byte per PF containing the number of its VFs, indexed by PF number. A
14395
+ * special value indicates that a PF is not present.
14396
+ */
14397
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VFS_PER_PF_OFST 42
14398
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VFS_PER_PF_LEN 1
14399
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VFS_PER_PF_NUM 16
14400
+/* enum: The caller is not permitted to access information on this PF. */
14401
+/*               MC_CMD_GET_CAPABILITIES_V7_OUT_ACCESS_NOT_PERMITTED 0xff */
14402
+/* enum: PF does not exist. */
14403
+/*               MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_PRESENT 0xfe */
14404
+/* Number of VIs available for each external port */
14405
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_OFST 58
14406
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_LEN 2
14407
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_NUM 4
14408
+/* Size of RX descriptor cache expressed as binary logarithm The actual size
14409
+ * equals (2 ^ RX_DESC_CACHE_SIZE)
14410
+ */
14411
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DESC_CACHE_SIZE_OFST 66
14412
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DESC_CACHE_SIZE_LEN 1
14413
+/* Size of TX descriptor cache expressed as binary logarithm The actual size
14414
+ * equals (2 ^ TX_DESC_CACHE_SIZE)
14415
+ */
14416
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DESC_CACHE_SIZE_OFST 67
14417
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DESC_CACHE_SIZE_LEN 1
14418
+/* Total number of available PIO buffers */
14419
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_PIO_BUFFS_OFST 68
14420
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_PIO_BUFFS_LEN 2
14421
+/* Size of a single PIO buffer */
14422
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_SIZE_PIO_BUFF_OFST 70
14423
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_SIZE_PIO_BUFF_LEN 2
14424
+/* On chips later than Medford the amount of address space assigned to each VI
14425
+ * is configurable. This is a global setting that the driver must query to
14426
+ * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
14427
+ * with 8k VI windows.
14428
+ */
14429
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_OFST 72
14430
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_LEN 1
14431
+/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
14432
+ * CTPIO is not mapped.
14433
+ */
14434
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_8K 0x0
14435
+/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
14436
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_16K 0x1
14437
+/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
14438
+#define          MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_64K 0x2
14439
+/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
14440
+ * (SF-115995-SW) in the present configuration of firmware and port mode.
14441
+ */
14442
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
14443
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
14444
+/* Number of buffers per adapter that can be used for VFIFO Stuffing
14445
+ * (SF-115995-SW) in the present configuration of firmware and port mode.
14446
+ */
14447
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
14448
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
14449
+/* Entry count in the MAC stats array, including the final GENERATION_END
14450
+ * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
14451
+ * hold at least this many 64-bit stats values, if they wish to receive all
14452
+ * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
14453
+ * stats array returned will be truncated.
14454
+ */
14455
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_NUM_STATS_OFST 76
14456
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_NUM_STATS_LEN 2
14457
+/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field
14458
+ * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
14459
+ */
14460
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_MAX_OFST 80
14461
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_MAX_LEN 4
14462
+/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in
14463
+ * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when
14464
+ * they create an RX queue. Due to hardware limitations, only a small number of
14465
+ * different buffer sizes may be available concurrently. Nonzero entries in
14466
+ * this array are the sizes of buffers which the system guarantees will be
14467
+ * available for use. If the list is empty, there are no limitations on
14468
+ * concurrent buffer sizes.
14469
+ */
14470
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84
14471
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
14472
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16
14473
+/* Third word of flags. Not present on older firmware (check the length). */
14474
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS3_OFST 148
14475
+#define       MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS3_LEN 4
14476
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_OFST 148
14477
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_LBN 0
14478
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_WIDTH 1
14479
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_EVEN_SPREADING_OFST 148
14480
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_EVEN_SPREADING_LBN 1
14481
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_EVEN_SPREADING_WIDTH 1
14482
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 148
14483
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 2
14484
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1
14485
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_SUPPORTED_OFST 148
14486
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_SUPPORTED_LBN 3
14487
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_SUPPORTED_WIDTH 1
14488
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_OFST 148
14489
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_LBN 4
14490
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_WIDTH 1
14491
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 148
14492
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 5
14493
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1
14494
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 148
14495
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 6
14496
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1
14497
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
14498
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
14499
+#define        MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
14500
+
14501
+/* MC_CMD_GET_CAPABILITIES_V8_OUT msgresponse */
14502
+#define    MC_CMD_GET_CAPABILITIES_V8_OUT_LEN 160
14503
+/* First word of flags. */
14504
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_OFST 0
14505
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_LEN 4
14506
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_OFST 0
14507
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_LBN 3
14508
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_WIDTH 1
14509
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_OFST 0
14510
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_LBN 4
14511
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_WIDTH 1
14512
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_OFST 0
14513
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_LBN 5
14514
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_WIDTH 1
14515
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
14516
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
14517
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
14518
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_OFST 0
14519
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_LBN 7
14520
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
14521
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_OFST 0
14522
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_LBN 8
14523
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
14524
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_OFST 0
14525
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_LBN 9
14526
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_WIDTH 1
14527
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
14528
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
14529
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
14530
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
14531
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
14532
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
14533
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
14534
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
14535
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
14536
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_OFST 0
14537
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_LBN 13
14538
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
14539
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_QBB_OFST 0
14540
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_QBB_LBN 14
14541
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_QBB_WIDTH 1
14542
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
14543
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
14544
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
14545
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_OFST 0
14546
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_LBN 16
14547
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_WIDTH 1
14548
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_OFST 0
14549
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_LBN 17
14550
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_WIDTH 1
14551
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_OFST 0
14552
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_LBN 18
14553
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_WIDTH 1
14554
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_OFST 0
14555
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_LBN 19
14556
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_WIDTH 1
14557
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_OFST 0
14558
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_LBN 20
14559
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_WIDTH 1
14560
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_OFST 0
14561
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_LBN 21
14562
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_WIDTH 1
14563
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_OFST 0
14564
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_LBN 22
14565
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_WIDTH 1
14566
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_OFST 0
14567
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_LBN 23
14568
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_WIDTH 1
14569
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_OFST 0
14570
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_LBN 24
14571
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_WIDTH 1
14572
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_OFST 0
14573
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_LBN 25
14574
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_WIDTH 1
14575
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_OFST 0
14576
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_LBN 26
14577
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_WIDTH 1
14578
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_OFST 0
14579
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_LBN 27
14580
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
14581
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_OFST 0
14582
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_LBN 28
14583
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_WIDTH 1
14584
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
14585
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
14586
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
14587
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_OFST 0
14588
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_LBN 30
14589
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_WIDTH 1
14590
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_OFST 0
14591
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_LBN 31
14592
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_WIDTH 1
14593
+/* RxDPCPU firmware id. */
14594
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DPCPU_FW_ID_OFST 4
14595
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DPCPU_FW_ID_LEN 2
14596
+/* enum: Standard RXDP firmware */
14597
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP 0x0
14598
+/* enum: Low latency RXDP firmware */
14599
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_LOW_LATENCY 0x1
14600
+/* enum: Packed stream RXDP firmware */
14601
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_PACKED_STREAM 0x2
14602
+/* enum: Rules engine RXDP firmware */
14603
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_RULES_ENGINE 0x5
14604
+/* enum: DPDK RXDP firmware */
14605
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_DPDK 0x6
14606
+/* enum: BIST RXDP firmware */
14607
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_BIST 0x10a
14608
+/* enum: RXDP Test firmware image 1 */
14609
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
14610
+/* enum: RXDP Test firmware image 2 */
14611
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
14612
+/* enum: RXDP Test firmware image 3 */
14613
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
14614
+/* enum: RXDP Test firmware image 4 */
14615
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
14616
+/* enum: RXDP Test firmware image 5 */
14617
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_BACKPRESSURE 0x105
14618
+/* enum: RXDP Test firmware image 6 */
14619
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
14620
+/* enum: RXDP Test firmware image 7 */
14621
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
14622
+/* enum: RXDP Test firmware image 8 */
14623
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
14624
+/* enum: RXDP Test firmware image 9 */
14625
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
14626
+/* enum: RXDP Test firmware image 10 */
14627
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_SLOW 0x10c
14628
+/* TxDPCPU firmware id. */
14629
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DPCPU_FW_ID_OFST 6
14630
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DPCPU_FW_ID_LEN 2
14631
+/* enum: Standard TXDP firmware */
14632
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP 0x0
14633
+/* enum: Low latency TXDP firmware */
14634
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_LOW_LATENCY 0x1
14635
+/* enum: High packet rate TXDP firmware */
14636
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_HIGH_PACKET_RATE 0x3
14637
+/* enum: Rules engine TXDP firmware */
14638
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_RULES_ENGINE 0x5
14639
+/* enum: DPDK TXDP firmware */
14640
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_DPDK 0x6
14641
+/* enum: BIST TXDP firmware */
14642
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_BIST 0x12d
14643
+/* enum: TXDP Test firmware image 1 */
14644
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
14645
+/* enum: TXDP Test firmware image 2 */
14646
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
14647
+/* enum: TXDP CSR bus test firmware */
14648
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_CSR 0x103
14649
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_OFST 8
14650
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_LEN 2
14651
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_REV_OFST 8
14652
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_REV_LBN 0
14653
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_REV_WIDTH 12
14654
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_TYPE_OFST 8
14655
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_TYPE_LBN 12
14656
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
14657
+/* enum: reserved value - do not use (may indicate alternative interpretation
14658
+ * of REV field in future)
14659
+ */
14660
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_RESERVED 0x0
14661
+/* enum: Trivial RX PD firmware for early Huntington development (Huntington
14662
+ * development only)
14663
+ */
14664
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
14665
+/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
14666
+ */
14667
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14668
+/* enum: RX PD firmware with approximately Siena-compatible behaviour
14669
+ * (Huntington development only)
14670
+ */
14671
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
14672
+/* enum: Full featured RX PD production firmware */
14673
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
14674
+/* enum: (deprecated original name for the FULL_FEATURED variant) */
14675
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_VSWITCH 0x3
14676
+/* enum: siena_compat variant RX PD firmware using PM rather than MAC
14677
+ * (Huntington development only)
14678
+ */
14679
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14680
+/* enum: Low latency RX PD production firmware */
14681
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
14682
+/* enum: Packed stream RX PD production firmware */
14683
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
14684
+/* enum: RX PD firmware handling layer 2 only for high packet rate performance
14685
+ * tests (Medford development only)
14686
+ */
14687
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
14688
+/* enum: Rules engine RX PD production firmware */
14689
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
14690
+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14691
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_L3XUDP 0x9
14692
+/* enum: DPDK RX PD production firmware */
14693
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_DPDK 0xa
14694
+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
14695
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14696
+/* enum: RX PD firmware parsing but not filtering network overlay tunnel
14697
+ * encapsulations (Medford development only)
14698
+ */
14699
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
14700
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_OFST 10
14701
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_LEN 2
14702
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_REV_OFST 10
14703
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_REV_LBN 0
14704
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_REV_WIDTH 12
14705
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_TYPE_OFST 10
14706
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_TYPE_LBN 12
14707
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
14708
+/* enum: reserved value - do not use (may indicate alternative interpretation
14709
+ * of REV field in future)
14710
+ */
14711
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_RESERVED 0x0
14712
+/* enum: Trivial TX PD firmware for early Huntington development (Huntington
14713
+ * development only)
14714
+ */
14715
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
14716
+/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
14717
+ */
14718
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14719
+/* enum: TX PD firmware with approximately Siena-compatible behaviour
14720
+ * (Huntington development only)
14721
+ */
14722
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
14723
+/* enum: Full featured TX PD production firmware */
14724
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
14725
+/* enum: (deprecated original name for the FULL_FEATURED variant) */
14726
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_VSWITCH 0x3
14727
+/* enum: siena_compat variant TX PD firmware using PM rather than MAC
14728
+ * (Huntington development only)
14729
+ */
14730
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14731
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
14732
+/* enum: TX PD firmware handling layer 2 only for high packet rate performance
14733
+ * tests (Medford development only)
14734
+ */
14735
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
14736
+/* enum: Rules engine TX PD production firmware */
14737
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
14738
+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14739
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_L3XUDP 0x9
14740
+/* enum: DPDK TX PD production firmware */
14741
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_DPDK 0xa
14742
+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
14743
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14744
+/* Hardware capabilities of NIC */
14745
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_HW_CAPABILITIES_OFST 12
14746
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_HW_CAPABILITIES_LEN 4
14747
+/* Licensed capabilities */
14748
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_LICENSE_CAPABILITIES_OFST 16
14749
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_LICENSE_CAPABILITIES_LEN 4
14750
+/* Second word of flags. Not present on older firmware (check the length). */
14751
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_OFST 20
14752
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_LEN 4
14753
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_OFST 20
14754
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_LBN 0
14755
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_WIDTH 1
14756
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_ENCAP_OFST 20
14757
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_ENCAP_LBN 1
14758
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_ENCAP_WIDTH 1
14759
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_EVQ_TIMER_CTRL_OFST 20
14760
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_EVQ_TIMER_CTRL_LBN 2
14761
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_EVQ_TIMER_CTRL_WIDTH 1
14762
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_EVENT_CUT_THROUGH_OFST 20
14763
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_EVENT_CUT_THROUGH_LBN 3
14764
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_EVENT_CUT_THROUGH_WIDTH 1
14765
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_OFST 20
14766
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_LBN 4
14767
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_WIDTH 1
14768
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VFIFO_ULL_MODE_OFST 20
14769
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VFIFO_ULL_MODE_LBN 5
14770
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
14771
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
14772
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
14773
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
14774
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
14775
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
14776
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
14777
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_V2_OFST 20
14778
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_V2_LBN 7
14779
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_V2_WIDTH 1
14780
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_TIMESTAMPING_OFST 20
14781
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_TIMESTAMPING_LBN 8
14782
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
14783
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TIMESTAMP_OFST 20
14784
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TIMESTAMP_LBN 9
14785
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TIMESTAMP_WIDTH 1
14786
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_SNIFF_OFST 20
14787
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_SNIFF_LBN 10
14788
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_SNIFF_WIDTH 1
14789
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_SNIFF_OFST 20
14790
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_SNIFF_LBN 11
14791
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_SNIFF_WIDTH 1
14792
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
14793
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
14794
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
14795
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_BACKGROUND_OFST 20
14796
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_BACKGROUND_LBN 13
14797
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_BACKGROUND_WIDTH 1
14798
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_DB_RETURN_OFST 20
14799
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_DB_RETURN_LBN 14
14800
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_DB_RETURN_WIDTH 1
14801
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_CTPIO_OFST 20
14802
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_CTPIO_LBN 15
14803
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_CTPIO_WIDTH 1
14804
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_SUPPORT_OFST 20
14805
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_SUPPORT_LBN 16
14806
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_SUPPORT_WIDTH 1
14807
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_BOUND_OFST 20
14808
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_BOUND_LBN 17
14809
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_BOUND_WIDTH 1
14810
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
14811
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
14812
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
14813
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_FLAG_OFST 20
14814
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_FLAG_LBN 19
14815
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_FLAG_WIDTH 1
14816
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_OFST 20
14817
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_LBN 20
14818
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_WIDTH 1
14819
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
14820
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
14821
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
14822
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
14823
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
14824
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
14825
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_L3XUDP_SUPPORT_OFST 20
14826
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_L3XUDP_SUPPORT_LBN 22
14827
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_L3XUDP_SUPPORT_WIDTH 1
14828
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
14829
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
14830
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
14831
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_VI_SPREADING_OFST 20
14832
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_VI_SPREADING_LBN 24
14833
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_VI_SPREADING_WIDTH 1
14834
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_HLB_IDLE_OFST 20
14835
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_HLB_IDLE_LBN 25
14836
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_HLB_IDLE_WIDTH 1
14837
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
14838
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
14839
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
14840
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
14841
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
14842
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
14843
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_BUNDLE_UPDATE_OFST 20
14844
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_BUNDLE_UPDATE_LBN 28
14845
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_BUNDLE_UPDATE_WIDTH 1
14846
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V3_OFST 20
14847
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V3_LBN 29
14848
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V3_WIDTH 1
14849
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_SENSORS_OFST 20
14850
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_SENSORS_LBN 30
14851
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_SENSORS_WIDTH 1
14852
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
14853
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
14854
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
14855
+/* Number of FATSOv2 contexts per datapath supported by this NIC (when
14856
+ * TX_TSO_V2 == 1). Not present on older firmware (check the length).
14857
+ */
14858
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
14859
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
14860
+/* One byte per PF containing the number of the external port assigned to this
14861
+ * PF, indexed by PF number. Special values indicate that a PF is either not
14862
+ * present or not assigned.
14863
+ */
14864
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
14865
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
14866
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
14867
+/* enum: The caller is not permitted to access information on this PF. */
14868
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_ACCESS_NOT_PERMITTED 0xff
14869
+/* enum: PF does not exist. */
14870
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_PRESENT 0xfe
14871
+/* enum: PF does exist but is not assigned to any external port. */
14872
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_ASSIGNED 0xfd
14873
+/* enum: This value indicates that PF is assigned, but it cannot be expressed
14874
+ * in this field. It is intended for a possible future situation where a more
14875
+ * complex scheme of PFs to ports mapping is being used. The future driver
14876
+ * should look for a new field supporting the new scheme. The current/old
14877
+ * driver should treat this value as PF_NOT_ASSIGNED.
14878
+ */
14879
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
14880
+/* One byte per PF containing the number of its VFs, indexed by PF number. A
14881
+ * special value indicates that a PF is not present.
14882
+ */
14883
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VFS_PER_PF_OFST 42
14884
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VFS_PER_PF_LEN 1
14885
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VFS_PER_PF_NUM 16
14886
+/* enum: The caller is not permitted to access information on this PF. */
14887
+/*               MC_CMD_GET_CAPABILITIES_V8_OUT_ACCESS_NOT_PERMITTED 0xff */
14888
+/* enum: PF does not exist. */
14889
+/*               MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_PRESENT 0xfe */
14890
+/* Number of VIs available for each external port */
14891
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_OFST 58
14892
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_LEN 2
14893
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_NUM 4
14894
+/* Size of RX descriptor cache expressed as binary logarithm The actual size
14895
+ * equals (2 ^ RX_DESC_CACHE_SIZE)
14896
+ */
14897
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DESC_CACHE_SIZE_OFST 66
14898
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DESC_CACHE_SIZE_LEN 1
14899
+/* Size of TX descriptor cache expressed as binary logarithm The actual size
14900
+ * equals (2 ^ TX_DESC_CACHE_SIZE)
14901
+ */
14902
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DESC_CACHE_SIZE_OFST 67
14903
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DESC_CACHE_SIZE_LEN 1
14904
+/* Total number of available PIO buffers */
14905
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_PIO_BUFFS_OFST 68
14906
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_PIO_BUFFS_LEN 2
14907
+/* Size of a single PIO buffer */
14908
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_SIZE_PIO_BUFF_OFST 70
14909
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_SIZE_PIO_BUFF_LEN 2
14910
+/* On chips later than Medford the amount of address space assigned to each VI
14911
+ * is configurable. This is a global setting that the driver must query to
14912
+ * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
14913
+ * with 8k VI windows.
14914
+ */
14915
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_OFST 72
14916
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_LEN 1
14917
+/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
14918
+ * CTPIO is not mapped.
14919
+ */
14920
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_8K 0x0
14921
+/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
14922
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_16K 0x1
14923
+/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
14924
+#define          MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_64K 0x2
14925
+/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
14926
+ * (SF-115995-SW) in the present configuration of firmware and port mode.
14927
+ */
14928
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
14929
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
14930
+/* Number of buffers per adapter that can be used for VFIFO Stuffing
14931
+ * (SF-115995-SW) in the present configuration of firmware and port mode.
14932
+ */
14933
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
14934
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
14935
+/* Entry count in the MAC stats array, including the final GENERATION_END
14936
+ * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
14937
+ * hold at least this many 64-bit stats values, if they wish to receive all
14938
+ * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
14939
+ * stats array returned will be truncated.
14940
+ */
14941
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_NUM_STATS_OFST 76
14942
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_NUM_STATS_LEN 2
14943
+/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field
14944
+ * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
14945
+ */
14946
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_MAX_OFST 80
14947
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_MAX_LEN 4
14948
+/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in
14949
+ * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when
14950
+ * they create an RX queue. Due to hardware limitations, only a small number of
14951
+ * different buffer sizes may be available concurrently. Nonzero entries in
14952
+ * this array are the sizes of buffers which the system guarantees will be
14953
+ * available for use. If the list is empty, there are no limitations on
14954
+ * concurrent buffer sizes.
14955
+ */
14956
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84
14957
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
14958
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16
14959
+/* Third word of flags. Not present on older firmware (check the length). */
14960
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_OFST 148
14961
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_LEN 4
14962
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_OFST 148
14963
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_LBN 0
14964
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_WIDTH 1
14965
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_EVEN_SPREADING_OFST 148
14966
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_EVEN_SPREADING_LBN 1
14967
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_EVEN_SPREADING_WIDTH 1
14968
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 148
14969
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 2
14970
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1
14971
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_SUPPORTED_OFST 148
14972
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_SUPPORTED_LBN 3
14973
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_SUPPORTED_WIDTH 1
14974
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_OFST 148
14975
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_LBN 4
14976
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_WIDTH 1
14977
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 148
14978
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 5
14979
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1
14980
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 148
14981
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 6
14982
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1
14983
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
14984
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
14985
+#define        MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
14986
+/* These bits are reserved for communicating test-specific capabilities to
14987
+ * host-side test software. All production drivers should treat this field as
14988
+ * opaque.
14989
+ */
14990
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_OFST 152
14991
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LEN 8
14992
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_OFST 152
14993
+#define       MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_OFST 156
14994
+
14995
+/* MC_CMD_GET_CAPABILITIES_V9_OUT msgresponse */
14996
+#define    MC_CMD_GET_CAPABILITIES_V9_OUT_LEN 184
14997
+/* First word of flags. */
14998
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS1_OFST 0
14999
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS1_LEN 4
15000
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_OFST 0
15001
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_LBN 3
15002
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_WIDTH 1
15003
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_OFST 0
15004
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_LBN 4
15005
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_WIDTH 1
15006
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_OFST 0
15007
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_LBN 5
15008
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_WIDTH 1
15009
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
15010
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
15011
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
15012
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_OFST 0
15013
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_LBN 7
15014
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
15015
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_OFST 0
15016
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_LBN 8
15017
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
15018
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_OFST 0
15019
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_LBN 9
15020
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_WIDTH 1
15021
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
15022
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
15023
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
15024
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
15025
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
15026
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
15027
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
15028
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
15029
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
15030
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_OFST 0
15031
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_LBN 13
15032
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
15033
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_QBB_OFST 0
15034
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_QBB_LBN 14
15035
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_QBB_WIDTH 1
15036
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
15037
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
15038
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
15039
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_OFST 0
15040
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_LBN 16
15041
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_WIDTH 1
15042
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_OFST 0
15043
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_LBN 17
15044
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_WIDTH 1
15045
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_OFST 0
15046
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_LBN 18
15047
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_WIDTH 1
15048
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_OFST 0
15049
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_LBN 19
15050
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_WIDTH 1
15051
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_OFST 0
15052
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_LBN 20
15053
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_WIDTH 1
15054
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_OFST 0
15055
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_LBN 21
15056
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_WIDTH 1
15057
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_OFST 0
15058
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_LBN 22
15059
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_WIDTH 1
15060
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_OFST 0
15061
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_LBN 23
15062
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_WIDTH 1
15063
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_OFST 0
15064
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_LBN 24
15065
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_WIDTH 1
15066
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_OFST 0
15067
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_LBN 25
15068
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_WIDTH 1
15069
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_OFST 0
15070
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_LBN 26
15071
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_WIDTH 1
15072
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_OFST 0
15073
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_LBN 27
15074
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
15075
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_OFST 0
15076
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_LBN 28
15077
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_WIDTH 1
15078
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
15079
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
15080
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
15081
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_OFST 0
15082
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_LBN 30
15083
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_WIDTH 1
15084
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_OFST 0
15085
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_LBN 31
15086
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_WIDTH 1
15087
+/* RxDPCPU firmware id. */
15088
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DPCPU_FW_ID_OFST 4
15089
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DPCPU_FW_ID_LEN 2
15090
+/* enum: Standard RXDP firmware */
15091
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP 0x0
15092
+/* enum: Low latency RXDP firmware */
15093
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_LOW_LATENCY 0x1
15094
+/* enum: Packed stream RXDP firmware */
15095
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_PACKED_STREAM 0x2
15096
+/* enum: Rules engine RXDP firmware */
15097
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_RULES_ENGINE 0x5
15098
+/* enum: DPDK RXDP firmware */
15099
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_DPDK 0x6
15100
+/* enum: BIST RXDP firmware */
15101
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_BIST 0x10a
15102
+/* enum: RXDP Test firmware image 1 */
15103
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
15104
+/* enum: RXDP Test firmware image 2 */
15105
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
15106
+/* enum: RXDP Test firmware image 3 */
15107
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
15108
+/* enum: RXDP Test firmware image 4 */
15109
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
15110
+/* enum: RXDP Test firmware image 5 */
15111
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_BACKPRESSURE 0x105
15112
+/* enum: RXDP Test firmware image 6 */
15113
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
15114
+/* enum: RXDP Test firmware image 7 */
15115
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
15116
+/* enum: RXDP Test firmware image 8 */
15117
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
15118
+/* enum: RXDP Test firmware image 9 */
15119
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
15120
+/* enum: RXDP Test firmware image 10 */
15121
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_SLOW 0x10c
15122
+/* TxDPCPU firmware id. */
15123
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DPCPU_FW_ID_OFST 6
15124
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DPCPU_FW_ID_LEN 2
15125
+/* enum: Standard TXDP firmware */
15126
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP 0x0
15127
+/* enum: Low latency TXDP firmware */
15128
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_LOW_LATENCY 0x1
15129
+/* enum: High packet rate TXDP firmware */
15130
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_HIGH_PACKET_RATE 0x3
15131
+/* enum: Rules engine TXDP firmware */
15132
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_RULES_ENGINE 0x5
15133
+/* enum: DPDK TXDP firmware */
15134
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_DPDK 0x6
15135
+/* enum: BIST TXDP firmware */
15136
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_BIST 0x12d
15137
+/* enum: TXDP Test firmware image 1 */
15138
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
15139
+/* enum: TXDP Test firmware image 2 */
15140
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
15141
+/* enum: TXDP CSR bus test firmware */
15142
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_CSR 0x103
15143
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_OFST 8
15144
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_LEN 2
15145
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_REV_OFST 8
15146
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_REV_LBN 0
15147
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_REV_WIDTH 12
15148
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_TYPE_OFST 8
15149
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_TYPE_LBN 12
15150
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
15151
+/* enum: reserved value - do not use (may indicate alternative interpretation
15152
+ * of REV field in future)
15153
+ */
15154
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_RESERVED 0x0
15155
+/* enum: Trivial RX PD firmware for early Huntington development (Huntington
15156
+ * development only)
15157
+ */
15158
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
15159
+/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
15160
+ */
15161
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
15162
+/* enum: RX PD firmware with approximately Siena-compatible behaviour
15163
+ * (Huntington development only)
15164
+ */
15165
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
15166
+/* enum: Full featured RX PD production firmware */
15167
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
15168
+/* enum: (deprecated original name for the FULL_FEATURED variant) */
15169
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_VSWITCH 0x3
15170
+/* enum: siena_compat variant RX PD firmware using PM rather than MAC
15171
+ * (Huntington development only)
15172
+ */
15173
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
15174
+/* enum: Low latency RX PD production firmware */
15175
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
15176
+/* enum: Packed stream RX PD production firmware */
15177
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
15178
+/* enum: RX PD firmware handling layer 2 only for high packet rate performance
15179
+ * tests (Medford development only)
15180
+ */
15181
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
15182
+/* enum: Rules engine RX PD production firmware */
15183
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
15184
+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
15185
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_L3XUDP 0x9
15186
+/* enum: DPDK RX PD production firmware */
15187
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_DPDK 0xa
15188
+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
15189
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
15190
+/* enum: RX PD firmware parsing but not filtering network overlay tunnel
15191
+ * encapsulations (Medford development only)
15192
+ */
15193
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
15194
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_OFST 10
15195
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_LEN 2
15196
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_REV_OFST 10
15197
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_REV_LBN 0
15198
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_REV_WIDTH 12
15199
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_TYPE_OFST 10
15200
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_TYPE_LBN 12
15201
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
15202
+/* enum: reserved value - do not use (may indicate alternative interpretation
15203
+ * of REV field in future)
15204
+ */
15205
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_RESERVED 0x0
15206
+/* enum: Trivial TX PD firmware for early Huntington development (Huntington
15207
+ * development only)
15208
+ */
15209
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
15210
+/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
15211
+ */
15212
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
15213
+/* enum: TX PD firmware with approximately Siena-compatible behaviour
15214
+ * (Huntington development only)
15215
+ */
15216
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
15217
+/* enum: Full featured TX PD production firmware */
15218
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
15219
+/* enum: (deprecated original name for the FULL_FEATURED variant) */
15220
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_VSWITCH 0x3
15221
+/* enum: siena_compat variant TX PD firmware using PM rather than MAC
15222
+ * (Huntington development only)
15223
+ */
15224
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
15225
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
15226
+/* enum: TX PD firmware handling layer 2 only for high packet rate performance
15227
+ * tests (Medford development only)
15228
+ */
15229
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
15230
+/* enum: Rules engine TX PD production firmware */
15231
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
15232
+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
15233
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_L3XUDP 0x9
15234
+/* enum: DPDK TX PD production firmware */
15235
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_DPDK 0xa
15236
+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
15237
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
15238
+/* Hardware capabilities of NIC */
15239
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_HW_CAPABILITIES_OFST 12
15240
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_HW_CAPABILITIES_LEN 4
15241
+/* Licensed capabilities */
15242
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_LICENSE_CAPABILITIES_OFST 16
15243
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_LICENSE_CAPABILITIES_LEN 4
15244
+/* Second word of flags. Not present on older firmware (check the length). */
15245
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS2_OFST 20
15246
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS2_LEN 4
15247
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_OFST 20
15248
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_LBN 0
15249
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_WIDTH 1
15250
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_ENCAP_OFST 20
15251
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_ENCAP_LBN 1
15252
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_ENCAP_WIDTH 1
15253
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_EVQ_TIMER_CTRL_OFST 20
15254
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_EVQ_TIMER_CTRL_LBN 2
15255
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_EVQ_TIMER_CTRL_WIDTH 1
15256
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_EVENT_CUT_THROUGH_OFST 20
15257
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_EVENT_CUT_THROUGH_LBN 3
15258
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_EVENT_CUT_THROUGH_WIDTH 1
15259
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_OFST 20
15260
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_LBN 4
15261
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_WIDTH 1
15262
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VFIFO_ULL_MODE_OFST 20
15263
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VFIFO_ULL_MODE_LBN 5
15264
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
15265
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
15266
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
15267
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
15268
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
15269
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
15270
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
15271
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_V2_OFST 20
15272
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_V2_LBN 7
15273
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_V2_WIDTH 1
15274
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_TIMESTAMPING_OFST 20
15275
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_TIMESTAMPING_LBN 8
15276
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
15277
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TIMESTAMP_OFST 20
15278
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TIMESTAMP_LBN 9
15279
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TIMESTAMP_WIDTH 1
15280
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_SNIFF_OFST 20
15281
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_SNIFF_LBN 10
15282
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_SNIFF_WIDTH 1
15283
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_SNIFF_OFST 20
15284
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_SNIFF_LBN 11
15285
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_SNIFF_WIDTH 1
15286
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
15287
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
15288
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
15289
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_BACKGROUND_OFST 20
15290
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_BACKGROUND_LBN 13
15291
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_BACKGROUND_WIDTH 1
15292
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_DB_RETURN_OFST 20
15293
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_DB_RETURN_LBN 14
15294
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_DB_RETURN_WIDTH 1
15295
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_CTPIO_OFST 20
15296
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_CTPIO_LBN 15
15297
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_CTPIO_WIDTH 1
15298
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_SUPPORT_OFST 20
15299
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_SUPPORT_LBN 16
15300
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_SUPPORT_WIDTH 1
15301
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_BOUND_OFST 20
15302
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_BOUND_LBN 17
15303
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_BOUND_WIDTH 1
15304
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
15305
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
15306
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
15307
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_FLAG_OFST 20
15308
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_FLAG_LBN 19
15309
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_FLAG_WIDTH 1
15310
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_OFST 20
15311
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_LBN 20
15312
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_WIDTH 1
15313
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
15314
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
15315
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
15316
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
15317
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
15318
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
15319
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_L3XUDP_SUPPORT_OFST 20
15320
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_L3XUDP_SUPPORT_LBN 22
15321
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_L3XUDP_SUPPORT_WIDTH 1
15322
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
15323
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
15324
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
15325
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_VI_SPREADING_OFST 20
15326
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_VI_SPREADING_LBN 24
15327
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_VI_SPREADING_WIDTH 1
15328
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_HLB_IDLE_OFST 20
15329
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_HLB_IDLE_LBN 25
15330
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_HLB_IDLE_WIDTH 1
15331
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
15332
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
15333
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
15334
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
15335
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
15336
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
15337
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_BUNDLE_UPDATE_OFST 20
15338
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_BUNDLE_UPDATE_LBN 28
15339
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_BUNDLE_UPDATE_WIDTH 1
15340
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V3_OFST 20
15341
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V3_LBN 29
15342
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V3_WIDTH 1
15343
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_SENSORS_OFST 20
15344
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_SENSORS_LBN 30
15345
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_SENSORS_WIDTH 1
15346
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
15347
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
15348
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
15349
+/* Number of FATSOv2 contexts per datapath supported by this NIC (when
15350
+ * TX_TSO_V2 == 1). Not present on older firmware (check the length).
15351
+ */
15352
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
15353
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
15354
+/* One byte per PF containing the number of the external port assigned to this
15355
+ * PF, indexed by PF number. Special values indicate that a PF is either not
15356
+ * present or not assigned.
15357
+ */
15358
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
15359
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
15360
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
15361
+/* enum: The caller is not permitted to access information on this PF. */
15362
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_ACCESS_NOT_PERMITTED 0xff
15363
+/* enum: PF does not exist. */
15364
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_PRESENT 0xfe
15365
+/* enum: PF does exist but is not assigned to any external port. */
15366
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_ASSIGNED 0xfd
15367
+/* enum: This value indicates that PF is assigned, but it cannot be expressed
15368
+ * in this field. It is intended for a possible future situation where a more
15369
+ * complex scheme of PFs to ports mapping is being used. The future driver
15370
+ * should look for a new field supporting the new scheme. The current/old
15371
+ * driver should treat this value as PF_NOT_ASSIGNED.
15372
+ */
15373
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
15374
+/* One byte per PF containing the number of its VFs, indexed by PF number. A
15375
+ * special value indicates that a PF is not present.
15376
+ */
15377
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VFS_PER_PF_OFST 42
15378
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VFS_PER_PF_LEN 1
15379
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VFS_PER_PF_NUM 16
15380
+/* enum: The caller is not permitted to access information on this PF. */
15381
+/*               MC_CMD_GET_CAPABILITIES_V9_OUT_ACCESS_NOT_PERMITTED 0xff */
15382
+/* enum: PF does not exist. */
15383
+/*               MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_PRESENT 0xfe */
15384
+/* Number of VIs available for each external port */
15385
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_OFST 58
15386
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_LEN 2
15387
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_NUM 4
15388
+/* Size of RX descriptor cache expressed as binary logarithm The actual size
15389
+ * equals (2 ^ RX_DESC_CACHE_SIZE)
15390
+ */
15391
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DESC_CACHE_SIZE_OFST 66
15392
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DESC_CACHE_SIZE_LEN 1
15393
+/* Size of TX descriptor cache expressed as binary logarithm The actual size
15394
+ * equals (2 ^ TX_DESC_CACHE_SIZE)
15395
+ */
15396
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DESC_CACHE_SIZE_OFST 67
15397
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DESC_CACHE_SIZE_LEN 1
15398
+/* Total number of available PIO buffers */
15399
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_PIO_BUFFS_OFST 68
15400
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_PIO_BUFFS_LEN 2
15401
+/* Size of a single PIO buffer */
15402
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_SIZE_PIO_BUFF_OFST 70
15403
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_SIZE_PIO_BUFF_LEN 2
15404
+/* On chips later than Medford the amount of address space assigned to each VI
15405
+ * is configurable. This is a global setting that the driver must query to
15406
+ * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
15407
+ * with 8k VI windows.
15408
+ */
15409
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_OFST 72
15410
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_LEN 1
15411
+/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
15412
+ * CTPIO is not mapped.
15413
+ */
15414
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_8K 0x0
15415
+/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
15416
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_16K 0x1
15417
+/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
15418
+#define          MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_64K 0x2
15419
+/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
15420
+ * (SF-115995-SW) in the present configuration of firmware and port mode.
15421
+ */
15422
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
15423
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
15424
+/* Number of buffers per adapter that can be used for VFIFO Stuffing
15425
+ * (SF-115995-SW) in the present configuration of firmware and port mode.
15426
+ */
15427
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
15428
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
15429
+/* Entry count in the MAC stats array, including the final GENERATION_END
15430
+ * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
15431
+ * hold at least this many 64-bit stats values, if they wish to receive all
15432
+ * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
15433
+ * stats array returned will be truncated.
15434
+ */
15435
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_NUM_STATS_OFST 76
15436
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_NUM_STATS_LEN 2
15437
+/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field
15438
+ * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
15439
+ */
15440
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_MAX_OFST 80
15441
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_MAX_LEN 4
15442
+/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in
15443
+ * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when
15444
+ * they create an RX queue. Due to hardware limitations, only a small number of
15445
+ * different buffer sizes may be available concurrently. Nonzero entries in
15446
+ * this array are the sizes of buffers which the system guarantees will be
15447
+ * available for use. If the list is empty, there are no limitations on
15448
+ * concurrent buffer sizes.
15449
+ */
15450
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84
15451
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
15452
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16
15453
+/* Third word of flags. Not present on older firmware (check the length). */
15454
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS3_OFST 148
15455
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS3_LEN 4
15456
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_OFST 148
15457
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_LBN 0
15458
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_WIDTH 1
15459
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_EVEN_SPREADING_OFST 148
15460
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_EVEN_SPREADING_LBN 1
15461
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_EVEN_SPREADING_WIDTH 1
15462
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 148
15463
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 2
15464
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1
15465
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_SUPPORTED_OFST 148
15466
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_SUPPORTED_LBN 3
15467
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_SUPPORTED_WIDTH 1
15468
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_OFST 148
15469
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_LBN 4
15470
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_WIDTH 1
15471
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 148
15472
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 5
15473
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1
15474
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 148
15475
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 6
15476
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1
15477
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
15478
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
15479
+#define        MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
15480
+/* These bits are reserved for communicating test-specific capabilities to
15481
+ * host-side test software. All production drivers should treat this field as
15482
+ * opaque.
15483
+ */
15484
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_OFST 152
15485
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LEN 8
15486
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_OFST 152
15487
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_OFST 156
15488
+/* The minimum size (in table entries) of indirection table to be allocated
15489
+ * from the pool for an RSS context. Note that the table size used must be a
15490
+ * power of 2.
15491
+ */
15492
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_OFST 160
15493
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 4
15494
+/* The maximum size (in table entries) of indirection table to be allocated
15495
+ * from the pool for an RSS context. Note that the table size used must be a
15496
+ * power of 2.
15497
+ */
15498
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_OFST 164
15499
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 4
15500
+/* The maximum number of queues that can be used by an RSS context in exclusive
15501
+ * mode. In exclusive mode the context has a configurable indirection table and
15502
+ * a configurable RSS key.
15503
+ */
15504
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_QUEUES_OFST 168
15505
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 4
15506
+/* The maximum number of queues that can be used by an RSS context in even-
15507
+ * spreading mode. In even-spreading mode the context has no indirection table
15508
+ * but it does have a configurable RSS key.
15509
+ */
15510
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_OFST 172
15511
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 4
15512
+/* The total number of RSS contexts supported. Note that the number of
15513
+ * available contexts using indirection tables is also limited by the
15514
+ * availability of indirection table space allocated from a common pool.
15515
+ */
15516
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_NUM_CONTEXTS_OFST 176
15517
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_NUM_CONTEXTS_LEN 4
15518
+/* The total amount of indirection table space that can be shared between RSS
15519
+ * contexts.
15520
+ */
15521
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_TABLE_POOL_SIZE_OFST 180
15522
+#define       MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_TABLE_POOL_SIZE_LEN 4
15523
+
1081915524 
1082015525 /***********************************/
1082115526 /* MC_CMD_V2_EXTN
....@@ -10853,6 +15558,7 @@
1085315558  * Allocate a pacer bucket (for qau rp or a snapper test)
1085415559  */
1085515560 #define MC_CMD_TCM_BUCKET_ALLOC 0xb2
15561
+#undef MC_CMD_0xb2_PRIVILEGE_CTG
1085615562 
1085715563 #define MC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1085815564 
....@@ -10871,6 +15577,7 @@
1087115577  * Free a pacer bucket
1087215578  */
1087315579 #define MC_CMD_TCM_BUCKET_FREE 0xb3
15580
+#undef MC_CMD_0xb3_PRIVILEGE_CTG
1087415581 
1087515582 #define MC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1087615583 
....@@ -10889,6 +15596,7 @@
1088915596  * Initialise pacer bucket with a given rate
1089015597  */
1089115598 #define MC_CMD_TCM_BUCKET_INIT 0xb4
15599
+#undef MC_CMD_0xb4_PRIVILEGE_CTG
1089215600 
1089315601 #define MC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1089415602 
....@@ -10922,6 +15630,7 @@
1092215630  * Initialise txq in pacer with given options or set options
1092315631  */
1092415632 #define MC_CMD_TCM_TXQ_INIT 0xb5
15633
+#undef MC_CMD_0xb5_PRIVILEGE_CTG
1092515634 
1092615635 #define MC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1092715636 
....@@ -10936,10 +15645,13 @@
1093615645 /* bitmask of the priority queues this txq is inserted into when inserted. */
1093715646 #define       MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8
1093815647 #define       MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_LEN 4
15648
+#define        MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_OFST 8
1093915649 #define        MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 0
1094015650 #define        MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_WIDTH 1
15651
+#define        MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_OFST 8
1094115652 #define        MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_LBN 1
1094215653 #define        MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_WIDTH 1
15654
+#define        MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_OFST 8
1094315655 #define        MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_LBN 2
1094415656 #define        MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_WIDTH 1
1094515657 /* the reaction point (RP) bucket */
....@@ -10970,10 +15682,13 @@
1097015682 /* bitmask of the priority queues this txq is inserted into when inserted. */
1097115683 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_OFST 8
1097215684 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_LEN 4
15685
+#define        MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_OFST 8
1097315686 #define        MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 0
1097415687 #define        MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_WIDTH 1
15688
+#define        MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_OFST 8
1097515689 #define        MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_LBN 1
1097615690 #define        MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_WIDTH 1
15691
+#define        MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_OFST 8
1097715692 #define        MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_LBN 2
1097815693 #define        MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_WIDTH 1
1097915694 /* the reaction point (RP) bucket */
....@@ -11005,6 +15720,7 @@
1100515720  * Link a push I/O buffer to a TxQ
1100615721  */
1100715722 #define MC_CMD_LINK_PIOBUF 0x92
15723
+#undef MC_CMD_0x92_PRIVILEGE_CTG
1100815724 
1100915725 #define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
1101015726 
....@@ -11026,6 +15742,7 @@
1102615742  * Unlink a push I/O buffer from a TxQ
1102715743  */
1102815744 #define MC_CMD_UNLINK_PIOBUF 0x93
15745
+#undef MC_CMD_0x93_PRIVILEGE_CTG
1102915746 
1103015747 #define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
1103115748 
....@@ -11044,6 +15761,7 @@
1104415761  * allocate and initialise a v-switch.
1104515762  */
1104615763 #define MC_CMD_VSWITCH_ALLOC 0x94
15764
+#undef MC_CMD_0x94_PRIVILEGE_CTG
1104715765 
1104815766 #define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1104915767 
....@@ -11068,6 +15786,7 @@
1106815786 /* Flags controlling v-port creation */
1106915787 #define       MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8
1107015788 #define       MC_CMD_VSWITCH_ALLOC_IN_FLAGS_LEN 4
15789
+#define        MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_OFST 8
1107115790 #define        MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
1107215791 #define        MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1
1107315792 /* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators,
....@@ -11089,6 +15808,7 @@
1108915808  * de-allocate a v-switch.
1109015809  */
1109115810 #define MC_CMD_VSWITCH_FREE 0x95
15811
+#undef MC_CMD_0x95_PRIVILEGE_CTG
1109215812 
1109315813 #define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1109415814 
....@@ -11109,6 +15829,7 @@
1110915829  * not, then the command returns ENOENT).
1111015830  */
1111115831 #define MC_CMD_VSWITCH_QUERY 0x63
15832
+#undef MC_CMD_0x63_PRIVILEGE_CTG
1111215833 
1111315834 #define MC_CMD_0x63_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1111415835 
....@@ -11127,6 +15848,7 @@
1112715848  * allocate a v-port.
1112815849  */
1112915850 #define MC_CMD_VPORT_ALLOC 0x96
15851
+#undef MC_CMD_0x96_PRIVILEGE_CTG
1113015852 
1113115853 #define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1113215854 
....@@ -11159,8 +15881,10 @@
1115915881 /* Flags controlling v-port creation */
1116015882 #define       MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8
1116115883 #define       MC_CMD_VPORT_ALLOC_IN_FLAGS_LEN 4
15884
+#define        MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_OFST 8
1116215885 #define        MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
1116315886 #define        MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1
15887
+#define        MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_OFST 8
1116415888 #define        MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_LBN 1
1116515889 #define        MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_WIDTH 1
1116615890 /* The number of VLAN tags to insert/remove. An error will be returned if
....@@ -11172,8 +15896,10 @@
1117215896 /* The actual VLAN tags to insert/remove */
1117315897 #define       MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16
1117415898 #define       MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_LEN 4
15899
+#define        MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_OFST 16
1117515900 #define        MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0
1117615901 #define        MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16
15902
+#define        MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_OFST 16
1117715903 #define        MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16
1117815904 #define        MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16
1117915905 
....@@ -11189,6 +15915,7 @@
1118915915  * de-allocate a v-port.
1119015916  */
1119115917 #define MC_CMD_VPORT_FREE 0x97
15918
+#undef MC_CMD_0x97_PRIVILEGE_CTG
1119215919 
1119315920 #define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1119415921 
....@@ -11207,6 +15934,7 @@
1120715934  * allocate a v-adaptor.
1120815935  */
1120915936 #define MC_CMD_VADAPTOR_ALLOC 0x98
15937
+#undef MC_CMD_0x98_PRIVILEGE_CTG
1121015938 
1121115939 #define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1121215940 
....@@ -11218,8 +15946,10 @@
1121815946 /* Flags controlling v-adaptor creation */
1121915947 #define       MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8
1122015948 #define       MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_LEN 4
15949
+#define        MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_OFST 8
1122115950 #define        MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0
1122215951 #define        MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1
15952
+#define        MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 8
1122315953 #define        MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1
1122415954 #define        MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
1122515955 /* The number of VLAN tags to strip on receive */
....@@ -11231,8 +15961,10 @@
1123115961 /* The actual VLAN tags to insert/remove */
1123215962 #define       MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 20
1123315963 #define       MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_LEN 4
15964
+#define        MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_OFST 20
1123415965 #define        MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0
1123515966 #define        MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 16
15967
+#define        MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_OFST 20
1123615968 #define        MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 16
1123715969 #define        MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_WIDTH 16
1123815970 /* The MAC address to assign to this v-adaptor */
....@@ -11250,6 +15982,7 @@
1125015982  * de-allocate a v-adaptor.
1125115983  */
1125215984 #define MC_CMD_VADAPTOR_FREE 0x99
15985
+#undef MC_CMD_0x99_PRIVILEGE_CTG
1125315986 
1125415987 #define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1125515988 
....@@ -11268,6 +16001,7 @@
1126816001  * assign a new MAC address to a v-adaptor.
1126916002  */
1127016003 #define MC_CMD_VADAPTOR_SET_MAC 0x5d
16004
+#undef MC_CMD_0x5d_PRIVILEGE_CTG
1127116005 
1127216006 #define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1127316007 
....@@ -11289,6 +16023,7 @@
1128916023  * read the MAC address assigned to a v-adaptor.
1129016024  */
1129116025 #define MC_CMD_VADAPTOR_GET_MAC 0x5e
16026
+#undef MC_CMD_0x5e_PRIVILEGE_CTG
1129216027 
1129316028 #define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1129416029 
....@@ -11310,6 +16045,7 @@
1131016045  * read some config of v-adaptor.
1131116046  */
1131216047 #define MC_CMD_VADAPTOR_QUERY 0x61
16048
+#undef MC_CMD_0x61_PRIVILEGE_CTG
1131316049 
1131416050 #define MC_CMD_0x61_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1131516051 
....@@ -11337,6 +16073,7 @@
1133716073  * assign a port to a PCI function.
1133816074  */
1133916075 #define MC_CMD_EVB_PORT_ASSIGN 0x9a
16076
+#undef MC_CMD_0x9a_PRIVILEGE_CTG
1134016077 
1134116078 #define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1134216079 
....@@ -11348,8 +16085,10 @@
1134816085 /* The target function to modify. */
1134916086 #define       MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4
1135016087 #define       MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_LEN 4
16088
+#define        MC_CMD_EVB_PORT_ASSIGN_IN_PF_OFST 4
1135116089 #define        MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0
1135216090 #define        MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16
16091
+#define        MC_CMD_EVB_PORT_ASSIGN_IN_VF_OFST 4
1135316092 #define        MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16
1135416093 #define        MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16
1135516094 
....@@ -11362,6 +16101,7 @@
1136216101  * Assign the 64 bit region addresses.
1136316102  */
1136416103 #define MC_CMD_RDWR_A64_REGIONS 0x9b
16104
+#undef MC_CMD_0x9b_PRIVILEGE_CTG
1136516105 
1136616106 #define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1136716107 
....@@ -11400,6 +16140,7 @@
1140016140  * Allocate an Onload stack ID.
1140116141  */
1140216142 #define MC_CMD_ONLOAD_STACK_ALLOC 0x9c
16143
+#undef MC_CMD_0x9c_PRIVILEGE_CTG
1140316144 
1140416145 #define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
1140516146 
....@@ -11421,6 +16162,7 @@
1142116162  * Free an Onload stack ID.
1142216163  */
1142316164 #define MC_CMD_ONLOAD_STACK_FREE 0x9d
16165
+#undef MC_CMD_0x9d_PRIVILEGE_CTG
1142416166 
1142516167 #define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
1142616168 
....@@ -11439,6 +16181,7 @@
1143916181  * Allocate an RSS context.
1144016182  */
1144116183 #define MC_CMD_RSS_CONTEXT_ALLOC 0x9e
16184
+#undef MC_CMD_0x9e_PRIVILEGE_CTG
1144216185 
1144316186 #define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1144416187 
....@@ -11459,11 +16202,67 @@
1145916202  * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.
1146016203  */
1146116204 #define          MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1
11462
-/* Number of queues spanned by this context, in the range 1-64; valid offsets
11463
- * in the indirection table will be in the range 0 to NUM_QUEUES-1.
16205
+/* enum: Allocate a context to spread evenly across an arbitrary number of
16206
+ * queues. No indirection table space is allocated for this context. (EF100 and
16207
+ * later)
16208
+ */
16209
+#define          MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EVEN_SPREADING 0x2
16210
+/* Number of queues spanned by this context. For exclusive contexts this must
16211
+ * be in the range 1 to RSS_MAX_INDIRECTION_QUEUES, where
16212
+ * RSS_MAX_INDIRECTION_QUEUES is queried from MC_CMD_GET_CAPABILITIES_V9 or if
16213
+ * V9 is not supported then RSS_MAX_INDIRECTION_QUEUES is 64. Valid entries in
16214
+ * the indirection table will be in the range 0 to NUM_QUEUES-1. For even-
16215
+ * spreading contexts this must be in the range 1 to
16216
+ * RSS_MAX_EVEN_SPREADING_QUEUES as queried from MC_CMD_GET_CAPABILITIES. Note
16217
+ * that specifying NUM_QUEUES = 1 will not perform any spreading but may still
16218
+ * be useful as a way of obtaining the Toeplitz hash.
1146416219  */
1146516220 #define       MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8
1146616221 #define       MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_LEN 4
16222
+
16223
+/* MC_CMD_RSS_CONTEXT_ALLOC_V2_IN msgrequest */
16224
+#define    MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_LEN 16
16225
+/* The handle of the owning upstream port */
16226
+#define       MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_UPSTREAM_PORT_ID_OFST 0
16227
+#define       MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_UPSTREAM_PORT_ID_LEN 4
16228
+/* The type of context to allocate */
16229
+#define       MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_OFST 4
16230
+#define       MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_LEN 4
16231
+/* enum: Allocate a context for exclusive use. The key and indirection table
16232
+ * must be explicitly configured.
16233
+ */
16234
+#define          MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_EXCLUSIVE 0x0
16235
+/* enum: Allocate a context for shared use; this will spread across a range of
16236
+ * queues, but the key and indirection table are pre-configured and may not be
16237
+ * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.
16238
+ */
16239
+#define          MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_SHARED 0x1
16240
+/* enum: Allocate a context to spread evenly across an arbitrary number of
16241
+ * queues. No indirection table space is allocated for this context. (EF100 and
16242
+ * later)
16243
+ */
16244
+#define          MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_EVEN_SPREADING 0x2
16245
+/* Number of queues spanned by this context. For exclusive contexts this must
16246
+ * be in the range 1 to RSS_MAX_INDIRECTION_QUEUES, where
16247
+ * RSS_MAX_INDIRECTION_QUEUES is queried from MC_CMD_GET_CAPABILITIES_V9 or if
16248
+ * V9 is not supported then RSS_MAX_INDIRECTION_QUEUES is 64. Valid entries in
16249
+ * the indirection table will be in the range 0 to NUM_QUEUES-1. For even-
16250
+ * spreading contexts this must be in the range 1 to
16251
+ * RSS_MAX_EVEN_SPREADING_QUEUES as queried from MC_CMD_GET_CAPABILITIES. Note
16252
+ * that specifying NUM_QUEUES = 1 will not perform any spreading but may still
16253
+ * be useful as a way of obtaining the Toeplitz hash.
16254
+ */
16255
+#define       MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_NUM_QUEUES_OFST 8
16256
+#define       MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_NUM_QUEUES_LEN 4
16257
+/* Size of indirection table to be allocated to this context from the pool.
16258
+ * Must be a power of 2. The minimum and maximum table size can be queried
16259
+ * using MC_CMD_GET_CAPABILITIES_V9. If there is not enough space remaining in
16260
+ * the common pool to allocate the requested table size, due to allocating
16261
+ * table space to other RSS contexts, then the command will fail with
16262
+ * MC_CMD_ERR_ENOSPC.
16263
+ */
16264
+#define       MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_INDIRECTION_TABLE_SIZE_OFST 12
16265
+#define       MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_INDIRECTION_TABLE_SIZE_LEN 4
1146716266 
1146816267 /* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */
1146916268 #define    MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4
....@@ -11482,6 +16281,7 @@
1148216281  * Free an RSS context.
1148316282  */
1148416283 #define MC_CMD_RSS_CONTEXT_FREE 0x9f
16284
+#undef MC_CMD_0x9f_PRIVILEGE_CTG
1148516285 
1148616286 #define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1148716287 
....@@ -11500,6 +16300,7 @@
1150016300  * Set the Toeplitz hash key for an RSS context.
1150116301  */
1150216302 #define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0
16303
+#undef MC_CMD_0xa0_PRIVILEGE_CTG
1150316304 
1150416305 #define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1150516306 
....@@ -11521,6 +16322,7 @@
1152116322  * Get the Toeplitz hash key for an RSS context.
1152216323  */
1152316324 #define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1
16325
+#undef MC_CMD_0xa1_PRIVILEGE_CTG
1152416326 
1152516327 #define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1152616328 
....@@ -11539,9 +16341,12 @@
1153916341 
1154016342 /***********************************/
1154116343 /* MC_CMD_RSS_CONTEXT_SET_TABLE
11542
- * Set the indirection table for an RSS context.
16344
+ * Set the indirection table for an RSS context. This command should only be
16345
+ * used with indirection tables containing 128 entries, which is the default
16346
+ * when the RSS context is allocated without specifying a table size.
1154316347  */
1154416348 #define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2
16349
+#undef MC_CMD_0xa2_PRIVILEGE_CTG
1154516350 
1154616351 #define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1154716352 
....@@ -11560,9 +16365,12 @@
1156016365 
1156116366 /***********************************/
1156216367 /* MC_CMD_RSS_CONTEXT_GET_TABLE
11563
- * Get the indirection table for an RSS context.
16368
+ * Get the indirection table for an RSS context. This command should only be
16369
+ * used with indirection tables containing 128 entries, which is the default
16370
+ * when the RSS context is allocated without specifying a table size.
1156416371  */
1156516372 #define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3
16373
+#undef MC_CMD_0xa3_PRIVILEGE_CTG
1156616374 
1156716375 #define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1156816376 
....@@ -11580,10 +16388,98 @@
1158016388 
1158116389 
1158216390 /***********************************/
16391
+/* MC_CMD_RSS_CONTEXT_WRITE_TABLE
16392
+ * Write a portion of a selectable-size indirection table for an RSS context.
16393
+ * This command must be used instead of MC_CMD_RSS_CONTEXT_SET_TABLE if the
16394
+ * RSS_SELECTABLE_TABLE_SIZE bit is set in MC_CMD_GET_CAPABILITIES.
16395
+ */
16396
+#define MC_CMD_RSS_CONTEXT_WRITE_TABLE 0x13e
16397
+#undef MC_CMD_0x13e_PRIVILEGE_CTG
16398
+
16399
+#define MC_CMD_0x13e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
16400
+
16401
+/* MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN msgrequest */
16402
+#define    MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LENMIN 8
16403
+#define    MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LENMAX 252
16404
+#define    MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LENMAX_MCDI2 1020
16405
+#define    MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LEN(num) (4+4*(num))
16406
+#define    MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_NUM(len) (((len)-4)/4)
16407
+/* The handle of the RSS context */
16408
+#define       MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_RSS_CONTEXT_ID_OFST 0
16409
+#define       MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_RSS_CONTEXT_ID_LEN 4
16410
+/* An array of index-value pairs to be written to the table. Structure is
16411
+ * MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY.
16412
+ */
16413
+#define       MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_OFST 4
16414
+#define       MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_LEN 4
16415
+#define       MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_MINNUM 1
16416
+#define       MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_MAXNUM 62
16417
+#define       MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_MAXNUM_MCDI2 254
16418
+
16419
+/* MC_CMD_RSS_CONTEXT_WRITE_TABLE_OUT msgresponse */
16420
+#define    MC_CMD_RSS_CONTEXT_WRITE_TABLE_OUT_LEN 0
16421
+
16422
+/* MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY structuredef */
16423
+#define    MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_LEN 4
16424
+/* The index of the table entry to be written. */
16425
+#define       MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_OFST 0
16426
+#define       MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_LEN 2
16427
+#define       MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_LBN 0
16428
+#define       MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_WIDTH 16
16429
+/* The value to write into the table entry. */
16430
+#define       MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_OFST 2
16431
+#define       MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_LEN 2
16432
+#define       MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_LBN 16
16433
+#define       MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_WIDTH 16
16434
+
16435
+
16436
+/***********************************/
16437
+/* MC_CMD_RSS_CONTEXT_READ_TABLE
16438
+ * Read a portion of a selectable-size indirection table for an RSS context.
16439
+ * This command must be used instead of MC_CMD_RSS_CONTEXT_GET_TABLE if the
16440
+ * RSS_SELECTABLE_TABLE_SIZE bit is set in MC_CMD_GET_CAPABILITIES.
16441
+ */
16442
+#define MC_CMD_RSS_CONTEXT_READ_TABLE 0x13f
16443
+#undef MC_CMD_0x13f_PRIVILEGE_CTG
16444
+
16445
+#define MC_CMD_0x13f_PRIVILEGE_CTG SRIOV_CTG_GENERAL
16446
+
16447
+/* MC_CMD_RSS_CONTEXT_READ_TABLE_IN msgrequest */
16448
+#define    MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LENMIN 6
16449
+#define    MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LENMAX 252
16450
+#define    MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LENMAX_MCDI2 1020
16451
+#define    MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LEN(num) (4+2*(num))
16452
+#define    MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_NUM(len) (((len)-4)/2)
16453
+/* The handle of the RSS context */
16454
+#define       MC_CMD_RSS_CONTEXT_READ_TABLE_IN_RSS_CONTEXT_ID_OFST 0
16455
+#define       MC_CMD_RSS_CONTEXT_READ_TABLE_IN_RSS_CONTEXT_ID_LEN 4
16456
+/* An array containing the indices of the entries to be read. */
16457
+#define       MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_OFST 4
16458
+#define       MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_LEN 2
16459
+#define       MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_MINNUM 1
16460
+#define       MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_MAXNUM 124
16461
+#define       MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_MAXNUM_MCDI2 508
16462
+
16463
+/* MC_CMD_RSS_CONTEXT_READ_TABLE_OUT msgresponse */
16464
+#define    MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LENMIN 2
16465
+#define    MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LENMAX 252
16466
+#define    MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LENMAX_MCDI2 1020
16467
+#define    MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LEN(num) (0+2*(num))
16468
+#define    MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_NUM(len) (((len)-0)/2)
16469
+/* A buffer containing the requested entries read from the table. */
16470
+#define       MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_OFST 0
16471
+#define       MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_LEN 2
16472
+#define       MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_MINNUM 1
16473
+#define       MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_MAXNUM 126
16474
+#define       MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_MAXNUM_MCDI2 510
16475
+
16476
+
16477
+/***********************************/
1158316478 /* MC_CMD_RSS_CONTEXT_SET_FLAGS
1158416479  * Set various control flags for an RSS context.
1158516480  */
1158616481 #define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1
16482
+#undef MC_CMD_0xe1_PRIVILEGE_CTG
1158716483 
1158816484 #define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1158916485 
....@@ -11606,26 +16502,37 @@
1160616502  */
1160716503 #define       MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4
1160816504 #define       MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_LEN 4
16505
+#define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_OFST 4
1160916506 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0
1161016507 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1
16508
+#define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_OFST 4
1161116509 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1
1161216510 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1
16511
+#define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_OFST 4
1161316512 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2
1161416513 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1
16514
+#define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_OFST 4
1161516515 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3
1161616516 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1
16517
+#define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_OFST 4
1161716518 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4
1161816519 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4
16520
+#define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_OFST 4
1161916521 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN 8
1162016522 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4
16523
+#define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_OFST 4
1162116524 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_LBN 12
1162216525 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4
16526
+#define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_OFST 4
1162316527 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN 16
1162416528 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4
16529
+#define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_OFST 4
1162516530 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN 20
1162616531 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4
16532
+#define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_OFST 4
1162716533 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_LBN 24
1162816534 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4
16535
+#define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_OFST 4
1162916536 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN 28
1163016537 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4
1163116538 
....@@ -11638,6 +16545,7 @@
1163816545  * Get various control flags for an RSS context.
1163916546  */
1164016547 #define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2
16548
+#undef MC_CMD_0xe2_PRIVILEGE_CTG
1164116549 
1164216550 #define MC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1164316551 
....@@ -11664,26 +16572,37 @@
1166416572  */
1166516573 #define       MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4
1166616574 #define       MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_LEN 4
16575
+#define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_OFST 4
1166716576 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0
1166816577 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1
16578
+#define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_OFST 4
1166916579 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1
1167016580 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1
16581
+#define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_OFST 4
1167116582 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2
1167216583 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1
16584
+#define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_OFST 4
1167316585 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3
1167416586 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1
16587
+#define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_OFST 4
1167516588 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4
1167616589 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4
16590
+#define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_OFST 4
1167716591 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN 8
1167816592 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4
16593
+#define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_OFST 4
1167916594 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN 12
1168016595 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4
16596
+#define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_OFST 4
1168116597 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN 16
1168216598 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4
16599
+#define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_OFST 4
1168316600 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN 20
1168416601 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4
16602
+#define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_OFST 4
1168516603 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN 24
1168616604 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4
16605
+#define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_OFST 4
1168716606 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN 28
1168816607 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4
1168916608 
....@@ -11693,6 +16612,7 @@
1169316612  * Allocate a .1p mapping.
1169416613  */
1169516614 #define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4
16615
+#undef MC_CMD_0xa4_PRIVILEGE_CTG
1169616616 
1169716617 #define MC_CMD_0xa4_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1169816618 
....@@ -11725,6 +16645,7 @@
1172516645  * Free a .1p mapping.
1172616646  */
1172716647 #define MC_CMD_DOT1P_MAPPING_FREE 0xa5
16648
+#undef MC_CMD_0xa5_PRIVILEGE_CTG
1172816649 
1172916650 #define MC_CMD_0xa5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1173016651 
....@@ -11743,6 +16664,7 @@
1174316664  * Set the mapping table for a .1p mapping.
1174416665  */
1174516666 #define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6
16667
+#undef MC_CMD_0xa6_PRIVILEGE_CTG
1174616668 
1174716669 #define MC_CMD_0xa6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1174816670 
....@@ -11766,6 +16688,7 @@
1176616688  * Get the mapping table for a .1p mapping.
1176716689  */
1176816690 #define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7
16691
+#undef MC_CMD_0xa7_PRIVILEGE_CTG
1176916692 
1177016693 #define MC_CMD_0xa7_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1177116694 
....@@ -11789,6 +16712,7 @@
1178916712  * Get Interrupt Vector config for this PF.
1179016713  */
1179116714 #define MC_CMD_GET_VECTOR_CFG 0xbf
16715
+#undef MC_CMD_0xbf_PRIVILEGE_CTG
1179216716 
1179316717 #define MC_CMD_0xbf_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1179416718 
....@@ -11813,6 +16737,7 @@
1181316737  * Set Interrupt Vector config for this PF.
1181416738  */
1181516739 #define MC_CMD_SET_VECTOR_CFG 0xc0
16740
+#undef MC_CMD_0xc0_PRIVILEGE_CTG
1181616741 
1181716742 #define MC_CMD_0xc0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1181816743 
....@@ -11839,6 +16764,7 @@
1183916764  * Add a MAC address to a v-port
1184016765  */
1184116766 #define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8
16767
+#undef MC_CMD_0xa8_PRIVILEGE_CTG
1184216768 
1184316769 #define MC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1184416770 
....@@ -11860,6 +16786,7 @@
1186016786  * Delete a MAC address from a v-port
1186116787  */
1186216788 #define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9
16789
+#undef MC_CMD_0xa9_PRIVILEGE_CTG
1186316790 
1186416791 #define MC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1186516792 
....@@ -11881,6 +16808,7 @@
1188116808  * Delete a MAC address from a v-port
1188216809  */
1188316810 #define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa
16811
+#undef MC_CMD_0xaa_PRIVILEGE_CTG
1188416812 
1188516813 #define MC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1188616814 
....@@ -11893,7 +16821,9 @@
1189316821 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */
1189416822 #define    MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4
1189516823 #define    MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250
16824
+#define    MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX_MCDI2 1018
1189616825 #define    MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num))
16826
+#define    MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_NUM(len) (((len)-4)/6)
1189716827 /* The number of MAC addresses returned */
1189816828 #define       MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0
1189916829 #define       MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_LEN 4
....@@ -11902,6 +16832,7 @@
1190216832 #define       MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6
1190316833 #define       MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0
1190416834 #define       MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41
16835
+#define       MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM_MCDI2 169
1190516836 
1190616837 
1190716838 /***********************************/
....@@ -11911,6 +16842,7 @@
1191116842  * function will be reset before applying the changes.
1191216843  */
1191316844 #define MC_CMD_VPORT_RECONFIGURE 0xeb
16845
+#undef MC_CMD_0xeb_PRIVILEGE_CTG
1191416846 
1191516847 #define MC_CMD_0xeb_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1191616848 
....@@ -11922,8 +16854,10 @@
1192216854 /* Flags requesting what should be changed. */
1192316855 #define       MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 4
1192416856 #define       MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_LEN 4
16857
+#define        MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_OFST 4
1192516858 #define        MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 0
1192616859 #define        MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_WIDTH 1
16860
+#define        MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_OFST 4
1192716861 #define        MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_LBN 1
1192816862 #define        MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_WIDTH 1
1192916863 /* The number of VLAN tags to insert/remove. An error will be returned if
....@@ -11935,8 +16869,10 @@
1193516869 /* The actual VLAN tags to insert/remove */
1193616870 #define       MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_OFST 12
1193716871 #define       MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_LEN 4
16872
+#define        MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_OFST 12
1193816873 #define        MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 0
1193916874 #define        MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_WIDTH 16
16875
+#define        MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_OFST 12
1194016876 #define        MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_LBN 16
1194116877 #define        MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_WIDTH 16
1194216878 /* The number of MAC addresses to add */
....@@ -11951,6 +16887,7 @@
1195116887 #define    MC_CMD_VPORT_RECONFIGURE_OUT_LEN 4
1195216888 #define       MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 0
1195316889 #define       MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_LEN 4
16890
+#define        MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_OFST 0
1195416891 #define        MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0
1195516892 #define        MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_WIDTH 1
1195616893 
....@@ -11960,6 +16897,7 @@
1196016897  * read some config of v-port.
1196116898  */
1196216899 #define MC_CMD_EVB_PORT_QUERY 0x62
16900
+#undef MC_CMD_0x62_PRIVILEGE_CTG
1196316901 
1196416902 #define MC_CMD_0x62_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1196516903 
....@@ -11989,6 +16927,7 @@
1198916927  * lifted in future.
1199016928  */
1199116929 #define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab
16930
+#undef MC_CMD_0xab_PRIVILEGE_CTG
1199216931 
1199316932 #define MC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_INSECURE
1199416933 
....@@ -12004,12 +16943,15 @@
1200416943 /* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */
1200516944 #define    MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12
1200616945 #define    MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252
16946
+#define    MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX_MCDI2 1020
1200716947 #define    MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num))
16948
+#define    MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_NUM(len) (((len)-0)/12)
1200816949 /* Raw buffer table entries, layed out as BUFTBL_ENTRY. */
1200916950 #define       MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0
1201016951 #define       MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12
1201116952 #define       MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1
1201216953 #define       MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21
16954
+#define       MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM_MCDI2 85
1201316955 
1201416956 
1201516957 /***********************************/
....@@ -12017,6 +16959,7 @@
1201716959  * Set global RXDP configuration settings
1201816960  */
1201916961 #define MC_CMD_SET_RXDP_CONFIG 0xc1
16962
+#undef MC_CMD_0xc1_PRIVILEGE_CTG
1202016963 
1202116964 #define MC_CMD_0xc1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1202216965 
....@@ -12024,8 +16967,10 @@
1202416967 #define    MC_CMD_SET_RXDP_CONFIG_IN_LEN 4
1202516968 #define       MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0
1202616969 #define       MC_CMD_SET_RXDP_CONFIG_IN_DATA_LEN 4
16970
+#define        MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_OFST 0
1202716971 #define        MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0
1202816972 #define        MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1
16973
+#define        MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_OFST 0
1202916974 #define        MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_LBN 1
1203016975 #define        MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_WIDTH 2
1203116976 /* enum: pad to 64 bytes */
....@@ -12044,6 +16989,7 @@
1204416989  * Get global RXDP configuration settings
1204516990  */
1204616991 #define MC_CMD_GET_RXDP_CONFIG 0xc2
16992
+#undef MC_CMD_0xc2_PRIVILEGE_CTG
1204716993 
1204816994 #define MC_CMD_0xc2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1204916995 
....@@ -12054,8 +17000,10 @@
1205417000 #define    MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4
1205517001 #define       MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0
1205617002 #define       MC_CMD_GET_RXDP_CONFIG_OUT_DATA_LEN 4
17003
+#define        MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_OFST 0
1205717004 #define        MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0
1205817005 #define        MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1
17006
+#define        MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_OFST 0
1205917007 #define        MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_LBN 1
1206017008 #define        MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_WIDTH 2
1206117009 /*             Enum values, see field(s): */
....@@ -12067,6 +17015,7 @@
1206717015  * Return the system and PDCPU clock frequencies.
1206817016  */
1206917017 #define MC_CMD_GET_CLOCK 0xac
17018
+#undef MC_CMD_0xac_PRIVILEGE_CTG
1207017019 
1207117020 #define MC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1207217021 
....@@ -12088,6 +17037,7 @@
1208817037  * Control the system and DPCPU clock frequencies. Changes are lost reboot.
1208917038  */
1209017039 #define MC_CMD_SET_CLOCK 0xad
17040
+#undef MC_CMD_0xad_PRIVILEGE_CTG
1209117041 
1209217042 #define MC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_INSECURE
1209317043 
....@@ -12173,6 +17123,7 @@
1217317123  * Send an arbitrary DPCPU message.
1217417124  */
1217517125 #define MC_CMD_DPCPU_RPC 0xae
17126
+#undef MC_CMD_0xae_PRIVILEGE_CTG
1217617127 
1217717128 #define MC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_INSECURE
1217817129 
....@@ -12201,6 +17152,7 @@
1220117152  */
1220217153 #define       MC_CMD_DPCPU_RPC_IN_DATA_OFST 4
1220317154 #define       MC_CMD_DPCPU_RPC_IN_DATA_LEN 32
17155
+#define        MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_OFST 4
1220417156 #define        MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8
1220517157 #define        MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8
1220617158 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */
....@@ -12212,14 +17164,19 @@
1221217164 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */
1221317165 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */
1221417166 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */
17167
+#define        MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_OFST 4
1221517168 #define        MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16
1221617169 #define        MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16
17170
+#define        MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_OFST 4
1221717171 #define        MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16
1221817172 #define        MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16
17173
+#define        MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_OFST 4
1221917174 #define        MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48
1222017175 #define        MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16
17176
+#define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_OFST 4
1222117177 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16
1222217178 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240
17179
+#define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_OFST 4
1222317180 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16
1222417181 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16
1222517182 #define          MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */
....@@ -12227,17 +17184,22 @@
1222717184 #define          MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */
1222817185 #define          MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */
1222917186 #define          MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */
17187
+#define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_OFST 4
1223017188 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48
1223117189 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16
17190
+#define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_OFST 4
1223217191 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64
1223317192 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16
17193
+#define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_OFST 4
1223417194 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80
1223517195 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16
17196
+#define        MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_OFST 4
1223617197 #define        MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16
1223717198 #define        MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16
1223817199 #define          MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */
1223917200 #define          MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */
1224017201 #define          MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */
17202
+#define        MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_OFST 4
1224117203 #define        MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64
1224217204 #define        MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16
1224317205 #define       MC_CMD_DPCPU_RPC_IN_WDATA_OFST 12
....@@ -12256,8 +17218,10 @@
1225617218 /* DATA */
1225717219 #define       MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4
1225817220 #define       MC_CMD_DPCPU_RPC_OUT_DATA_LEN 32
17221
+#define        MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_OFST 4
1225917222 #define        MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32
1226017223 #define        MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16
17224
+#define        MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_OFST 4
1226117225 #define        MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48
1226217226 #define        MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16
1226317227 #define       MC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12
....@@ -12277,6 +17241,7 @@
1227717241  * Trigger an interrupt by prodding the BIU.
1227817242  */
1227917243 #define MC_CMD_TRIGGER_INTERRUPT 0xe3
17244
+#undef MC_CMD_0xe3_PRIVILEGE_CTG
1228017245 
1228117246 #define MC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1228217247 
....@@ -12295,6 +17260,7 @@
1229517260  * Special operations to support (for now) shmboot.
1229617261  */
1229717262 #define MC_CMD_SHMBOOT_OP 0xe6
17263
+#undef MC_CMD_0xe6_PRIVILEGE_CTG
1229817264 
1229917265 #define MC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1230017266 
....@@ -12315,6 +17281,7 @@
1231517281  * Read multiple 64bit words from capture block memory
1231617282  */
1231717283 #define MC_CMD_CAP_BLK_READ 0xe7
17284
+#undef MC_CMD_0xe7_PRIVILEGE_CTG
1231817285 
1231917286 #define MC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_INSECURE
1232017287 
....@@ -12330,13 +17297,16 @@
1233017297 /* MC_CMD_CAP_BLK_READ_OUT msgresponse */
1233117298 #define    MC_CMD_CAP_BLK_READ_OUT_LENMIN 8
1233217299 #define    MC_CMD_CAP_BLK_READ_OUT_LENMAX 248
17300
+#define    MC_CMD_CAP_BLK_READ_OUT_LENMAX_MCDI2 1016
1233317301 #define    MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num))
17302
+#define    MC_CMD_CAP_BLK_READ_OUT_BUFFER_NUM(len) (((len)-0)/8)
1233417303 #define       MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0
1233517304 #define       MC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8
1233617305 #define       MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0
1233717306 #define       MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4
1233817307 #define       MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1
1233917308 #define       MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31
17309
+#define       MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM_MCDI2 127
1234017310 
1234117311 
1234217312 /***********************************/
....@@ -12344,6 +17314,7 @@
1234417314  * Take a dump of the DUT state
1234517315  */
1234617316 #define MC_CMD_DUMP_DO 0xe8
17317
+#undef MC_CMD_0xe8_PRIVILEGE_CTG
1234717318 
1234817319 #define MC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_INSECURE
1234917320 
....@@ -12423,6 +17394,7 @@
1242317394  * Configure unsolicited dumps
1242417395  */
1242517396 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9
17397
+#undef MC_CMD_0xe9_PRIVILEGE_CTG
1242617398 
1242717399 #define MC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_INSECURE
1242817400 
....@@ -12491,6 +17463,7 @@
1249117463  * the parameter is out of range.
1249217464  */
1249317465 #define MC_CMD_SET_PSU 0xea
17466
+#undef MC_CMD_0xea_PRIVILEGE_CTG
1249417467 
1249517468 #define MC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_INSECURE
1249617469 
....@@ -12516,6 +17489,7 @@
1251617489  * Get function information. PF and VF number.
1251717490  */
1251817491 #define MC_CMD_GET_FUNCTION_INFO 0xec
17492
+#undef MC_CMD_0xec_PRIVILEGE_CTG
1251917493 
1252017494 #define MC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1252117495 
....@@ -12537,6 +17511,7 @@
1253717511  * reboot.
1253817512  */
1253917513 #define MC_CMD_ENABLE_OFFLINE_BIST 0xed
17514
+#undef MC_CMD_0xed_PRIVILEGE_CTG
1254017515 
1254117516 #define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1254217517 
....@@ -12554,13 +17529,16 @@
1255417529  * forget.
1255517530  */
1255617531 #define MC_CMD_UART_SEND_DATA 0xee
17532
+#undef MC_CMD_0xee_PRIVILEGE_CTG
1255717533 
1255817534 #define MC_CMD_0xee_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1255917535 
1256017536 /* MC_CMD_UART_SEND_DATA_OUT msgrequest */
1256117537 #define    MC_CMD_UART_SEND_DATA_OUT_LENMIN 16
1256217538 #define    MC_CMD_UART_SEND_DATA_OUT_LENMAX 252
17539
+#define    MC_CMD_UART_SEND_DATA_OUT_LENMAX_MCDI2 1020
1256317540 #define    MC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num))
17541
+#define    MC_CMD_UART_SEND_DATA_OUT_DATA_NUM(len) (((len)-16)/1)
1256417542 /* CRC32 over OFFSET, LENGTH, RESERVED, DATA */
1256517543 #define       MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0
1256617544 #define       MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_LEN 4
....@@ -12577,6 +17555,7 @@
1257717555 #define       MC_CMD_UART_SEND_DATA_OUT_DATA_LEN 1
1257817556 #define       MC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0
1257917557 #define       MC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM 236
17558
+#define       MC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM_MCDI2 1004
1258017559 
1258117560 /* MC_CMD_UART_SEND_DATA_IN msgresponse */
1258217561 #define    MC_CMD_UART_SEND_DATA_IN_LEN 0
....@@ -12588,6 +17567,7 @@
1258817567  * subject to change and not currently implemented.
1258917568  */
1259017569 #define MC_CMD_UART_RECV_DATA 0xef
17570
+#undef MC_CMD_0xef_PRIVILEGE_CTG
1259117571 
1259217572 #define MC_CMD_0xef_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1259317573 
....@@ -12609,7 +17589,9 @@
1260917589 /* MC_CMD_UART_RECV_DATA_IN msgresponse */
1261017590 #define    MC_CMD_UART_RECV_DATA_IN_LENMIN 16
1261117591 #define    MC_CMD_UART_RECV_DATA_IN_LENMAX 252
17592
+#define    MC_CMD_UART_RECV_DATA_IN_LENMAX_MCDI2 1020
1261217593 #define    MC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num))
17594
+#define    MC_CMD_UART_RECV_DATA_IN_DATA_NUM(len) (((len)-16)/1)
1261317595 /* CRC32 over RESERVED1, RESERVED2, RESERVED3, DATA */
1261417596 #define       MC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0
1261517597 #define       MC_CMD_UART_RECV_DATA_IN_CHECKSUM_LEN 4
....@@ -12626,6 +17608,7 @@
1262617608 #define       MC_CMD_UART_RECV_DATA_IN_DATA_LEN 1
1262717609 #define       MC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0
1262817610 #define       MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM 236
17611
+#define       MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM_MCDI2 1004
1262917612 
1263017613 
1263117614 /***********************************/
....@@ -12633,6 +17616,7 @@
1263317616  * Read data programmed into the device One-Time-Programmable (OTP) Fuses
1263417617  */
1263517618 #define MC_CMD_READ_FUSES 0xf0
17619
+#undef MC_CMD_0xf0_PRIVILEGE_CTG
1263617620 
1263717621 #define MC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_INSECURE
1263817622 
....@@ -12648,7 +17632,9 @@
1264817632 /* MC_CMD_READ_FUSES_OUT msgresponse */
1264917633 #define    MC_CMD_READ_FUSES_OUT_LENMIN 4
1265017634 #define    MC_CMD_READ_FUSES_OUT_LENMAX 252
17635
+#define    MC_CMD_READ_FUSES_OUT_LENMAX_MCDI2 1020
1265117636 #define    MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num))
17637
+#define    MC_CMD_READ_FUSES_OUT_DATA_NUM(len) (((len)-4)/1)
1265217638 /* Length of returned OTP data in bytes */
1265317639 #define       MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0
1265417640 #define       MC_CMD_READ_FUSES_OUT_LENGTH_LEN 4
....@@ -12657,6 +17643,7 @@
1265717643 #define       MC_CMD_READ_FUSES_OUT_DATA_LEN 1
1265817644 #define       MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0
1265917645 #define       MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248
17646
+#define       MC_CMD_READ_FUSES_OUT_DATA_MAXNUM_MCDI2 1016
1266017647 
1266117648 
1266217649 /***********************************/
....@@ -12664,13 +17651,16 @@
1266417651  * Get or set KR Serdes RXEQ and TX Driver settings
1266517652  */
1266617653 #define MC_CMD_KR_TUNE 0xf1
17654
+#undef MC_CMD_0xf1_PRIVILEGE_CTG
1266717655 
1266817656 #define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1266917657 
1267017658 /* MC_CMD_KR_TUNE_IN msgrequest */
1267117659 #define    MC_CMD_KR_TUNE_IN_LENMIN 4
1267217660 #define    MC_CMD_KR_TUNE_IN_LENMAX 252
17661
+#define    MC_CMD_KR_TUNE_IN_LENMAX_MCDI2 1020
1267317662 #define    MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num))
17663
+#define    MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_NUM(len) (((len)-4)/4)
1267417664 /* Requested operation */
1267517665 #define       MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0
1267617666 #define       MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1
....@@ -12707,6 +17697,7 @@
1270717697 #define       MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4
1270817698 #define       MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0
1270917699 #define       MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM 62
17700
+#define       MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM_MCDI2 254
1271017701 
1271117702 /* MC_CMD_KR_TUNE_OUT msgresponse */
1271217703 #define    MC_CMD_KR_TUNE_OUT_LEN 0
....@@ -12723,12 +17714,16 @@
1272317714 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT msgresponse */
1272417715 #define    MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4
1272517716 #define    MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252
17717
+#define    MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX_MCDI2 1020
1272617718 #define    MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
17719
+#define    MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
1272717720 /* RXEQ Parameter */
1272817721 #define       MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0
1272917722 #define       MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4
1273017723 #define       MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1
1273117724 #define       MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63
17725
+#define       MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM_MCDI2 255
17726
+#define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_OFST 0
1273217727 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0
1273317728 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8
1273417729 /* enum: Attenuation (0-15, Huntington) */
....@@ -12817,6 +17812,45 @@
1281717812 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_PVT 0x20
1281817813 /* enum: CDR integral loop code (Medford2) */
1281917814 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_INTEG 0x21
17815
+/* enum: CTLE Boost stages - retimer lineside (Medford2 with DS250x retimer - 4
17816
+ * stages, 2 bits per stage)
17817
+ */
17818
+#define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST_RT_LS 0x22
17819
+/* enum: DFE Tap1 - retimer lineside (Medford2 with DS250x retimer (-31 - 31))
17820
+ */
17821
+#define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_RT_LS 0x23
17822
+/* enum: DFE Tap2 - retimer lineside (Medford2 with DS250x retimer (-15 - 15))
17823
+ */
17824
+#define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2_RT_LS 0x24
17825
+/* enum: DFE Tap3 - retimer lineside (Medford2 with DS250x retimer (-15 - 15))
17826
+ */
17827
+#define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3_RT_LS 0x25
17828
+/* enum: DFE Tap4 - retimer lineside (Medford2 with DS250x retimer (-15 - 15))
17829
+ */
17830
+#define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4_RT_LS 0x26
17831
+/* enum: DFE Tap5 - retimer lineside (Medford2 with DS250x retimer (-15 - 15))
17832
+ */
17833
+#define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5_RT_LS 0x27
17834
+/* enum: CTLE Boost stages - retimer hostside (Medford2 with DS250x retimer - 4
17835
+ * stages, 2 bits per stage)
17836
+ */
17837
+#define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST_RT_HS 0x28
17838
+/* enum: DFE Tap1 - retimer hostside (Medford2 with DS250x retimer (-31 - 31))
17839
+ */
17840
+#define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_RT_HS 0x29
17841
+/* enum: DFE Tap2 - retimer hostside (Medford2 with DS250x retimer (-15 - 15))
17842
+ */
17843
+#define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2_RT_HS 0x2a
17844
+/* enum: DFE Tap3 - retimer hostside (Medford2 with DS250x retimer (-15 - 15))
17845
+ */
17846
+#define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3_RT_HS 0x2b
17847
+/* enum: DFE Tap4 - retimer hostside (Medford2 with DS250x retimer (-15 - 15))
17848
+ */
17849
+#define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4_RT_HS 0x2c
17850
+/* enum: DFE Tap5 - retimer hostside (Medford2 with DS250x retimer (-15 - 15))
17851
+ */
17852
+#define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5_RT_HS 0x2d
17853
+#define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_OFST 0
1282017854 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8
1282117855 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3
1282217856 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
....@@ -12824,19 +17858,25 @@
1282417858 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */
1282517859 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */
1282617860 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
17861
+#define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_OFST 0
1282717862 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11
1282817863 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1
17864
+#define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_OFST 0
1282917865 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12
1283017866 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4
17867
+#define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_OFST 0
1283117868 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16
1283217869 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8
17870
+#define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_OFST 0
1283317871 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24
1283417872 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8
1283517873 
1283617874 /* MC_CMD_KR_TUNE_RXEQ_SET_IN msgrequest */
1283717875 #define    MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMIN 8
1283817876 #define    MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252
17877
+#define    MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX_MCDI2 1020
1283917878 #define    MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num))
17879
+#define    MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_NUM(len) (((len)-4)/4)
1284017880 /* Requested operation */
1284117881 #define       MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0
1284217882 #define       MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1
....@@ -12848,20 +17888,27 @@
1284817888 #define       MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4
1284917889 #define       MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1
1285017890 #define       MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62
17891
+#define       MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM_MCDI2 254
17892
+#define        MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_OFST 4
1285117893 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0
1285217894 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8
1285317895 /*             Enum values, see field(s): */
1285417896 /*                MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */
17897
+#define        MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_OFST 4
1285517898 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8
1285617899 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3
1285717900 /*             Enum values, see field(s): */
1285817901 /*                MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */
17902
+#define        MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_OFST 4
1285917903 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11
1286017904 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1
17905
+#define        MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_OFST 4
1286117906 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12
1286217907 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4
17908
+#define        MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_OFST 4
1286317909 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16
1286417910 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8
17911
+#define        MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_OFST 4
1286517912 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24
1286617913 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8
1286717914 
....@@ -12880,12 +17927,16 @@
1288017927 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT msgresponse */
1288117928 #define    MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4
1288217929 #define    MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX 252
17930
+#define    MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX_MCDI2 1020
1288317931 #define    MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))
17932
+#define    MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
1288417933 /* TXEQ Parameter */
1288517934 #define       MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0
1288617935 #define       MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4
1288717936 #define       MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1
1288817937 #define       MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63
17938
+#define       MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM_MCDI2 255
17939
+#define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_OFST 0
1288917940 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0
1289017941 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8
1289117942 /* enum: TX Amplitude (Huntington, Medford, Medford2) */
....@@ -12910,10 +17961,23 @@
1291017961 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9
1291117962 /* enum: TX Amplitude Fine control (Medford) */
1291217963 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_FINE 0xa
12913
-/* enum: Pre-shoot Tap (Medford, Medford2) */
17964
+/* enum: Pre-cursor Tap (Medford, Medford2) */
1291417965 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV 0xb
12915
-/* enum: De-emphasis Tap (Medford, Medford2) */
17966
+/* enum: Post-cursor Tap (Medford, Medford2) */
1291617967 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY 0xc
17968
+/* enum: TX Amplitude (Retimer Lineside) */
17969
+#define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_RT_LS 0xd
17970
+/* enum: Pre-cursor Tap (Retimer Lineside) */
17971
+#define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV_RT_LS 0xe
17972
+/* enum: Post-cursor Tap (Retimer Lineside) */
17973
+#define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY_RT_LS 0xf
17974
+/* enum: TX Amplitude (Retimer Hostside) */
17975
+#define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_RT_HS 0x10
17976
+/* enum: Pre-cursor Tap (Retimer Hostside) */
17977
+#define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV_RT_HS 0x11
17978
+/* enum: Post-cursor Tap (Retimer Hostside) */
17979
+#define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY_RT_HS 0x12
17980
+#define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_OFST 0
1291717981 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8
1291817982 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3
1291917983 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */
....@@ -12921,17 +17985,22 @@
1292117985 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */
1292217986 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */
1292317987 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
17988
+#define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_OFST 0
1292417989 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_LBN 11
1292517990 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 5
17991
+#define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_OFST 0
1292617992 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_LBN 16
1292717993 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8
17994
+#define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_OFST 0
1292817995 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_LBN 24
1292917996 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_WIDTH 8
1293017997 
1293117998 /* MC_CMD_KR_TUNE_TXEQ_SET_IN msgrequest */
1293217999 #define    MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMIN 8
1293318000 #define    MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX 252
18001
+#define    MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX_MCDI2 1020
1293418002 #define    MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num))
18003
+#define    MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_NUM(len) (((len)-4)/4)
1293518004 /* Requested operation */
1293618005 #define       MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0
1293718006 #define       MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_LEN 1
....@@ -12943,18 +18012,24 @@
1294318012 #define       MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4
1294418013 #define       MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MINNUM 1
1294518014 #define       MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM 62
18015
+#define       MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM_MCDI2 254
18016
+#define        MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_OFST 4
1294618017 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0
1294718018 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_WIDTH 8
1294818019 /*             Enum values, see field(s): */
1294918020 /*                MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_ID */
18021
+#define        MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_OFST 4
1295018022 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_LBN 8
1295118023 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_WIDTH 3
1295218024 /*             Enum values, see field(s): */
1295318025 /*                MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_LANE */
18026
+#define        MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_OFST 4
1295418027 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_LBN 11
1295518028 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_WIDTH 5
18029
+#define        MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_OFST 4
1295618030 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_LBN 16
1295718031 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_WIDTH 8
18032
+#define        MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_OFST 4
1295818033 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_LBN 24
1295918034 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_WIDTH 8
1296018035 
....@@ -12995,8 +18070,10 @@
1299518070 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_LEN 3
1299618071 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_OFST 4
1299718072 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_LEN 4
18073
+#define        MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_OFST 4
1299818074 #define        MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_LBN 0
1299918075 #define        MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_WIDTH 8
18076
+#define        MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_OFST 4
1300018077 #define        MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_LBN 31
1300118078 #define        MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_WIDTH 1
1300218079 /* Scan duration / cycle count */
....@@ -13018,11 +18095,14 @@
1301818095 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT msgresponse */
1301918096 #define    MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0
1302018097 #define    MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252
18098
+#define    MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX_MCDI2 1020
1302118099 #define    MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num))
18100
+#define    MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_NUM(len) (((len)-0)/2)
1302218101 #define       MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0
1302318102 #define       MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2
1302418103 #define       MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0
1302518104 #define       MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126
18105
+#define       MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM_MCDI2 510
1302618106 
1302718107 /* MC_CMD_KR_TUNE_READ_FOM_IN msgrequest */
1302818108 #define    MC_CMD_KR_TUNE_READ_FOM_IN_LEN 8
....@@ -13034,8 +18114,10 @@
1303418114 #define       MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_LEN 3
1303518115 #define       MC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4
1303618116 #define       MC_CMD_KR_TUNE_READ_FOM_IN_LANE_LEN 4
18117
+#define        MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_OFST 4
1303718118 #define        MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_LBN 0
1303818119 #define        MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_WIDTH 8
18120
+#define        MC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_OFST 4
1303918121 #define        MC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_LBN 31
1304018122 #define        MC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_WIDTH 1
1304118123 
....@@ -13125,13 +18207,16 @@
1312518207  * Get or set PCIE Serdes RXEQ and TX Driver settings
1312618208  */
1312718209 #define MC_CMD_PCIE_TUNE 0xf2
18210
+#undef MC_CMD_0xf2_PRIVILEGE_CTG
1312818211 
1312918212 #define MC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1313018213 
1313118214 /* MC_CMD_PCIE_TUNE_IN msgrequest */
1313218215 #define    MC_CMD_PCIE_TUNE_IN_LENMIN 4
1313318216 #define    MC_CMD_PCIE_TUNE_IN_LENMAX 252
18217
+#define    MC_CMD_PCIE_TUNE_IN_LENMAX_MCDI2 1020
1313418218 #define    MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num))
18219
+#define    MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_NUM(len) (((len)-4)/4)
1313518220 /* Requested operation */
1313618221 #define       MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0
1313718222 #define       MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1
....@@ -13160,6 +18245,7 @@
1316018245 #define       MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4
1316118246 #define       MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0
1316218247 #define       MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM 62
18248
+#define       MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM_MCDI2 254
1316318249 
1316418250 /* MC_CMD_PCIE_TUNE_OUT msgresponse */
1316518251 #define    MC_CMD_PCIE_TUNE_OUT_LEN 0
....@@ -13176,12 +18262,16 @@
1317618262 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT msgresponse */
1317718263 #define    MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4
1317818264 #define    MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252
18265
+#define    MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX_MCDI2 1020
1317918266 #define    MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
18267
+#define    MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
1318018268 /* RXEQ Parameter */
1318118269 #define       MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0
1318218270 #define       MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4
1318318271 #define       MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1
1318418272 #define       MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63
18273
+#define       MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM_MCDI2 255
18274
+#define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_OFST 0
1318518275 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0
1318618276 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8
1318718277 /* enum: Attenuation (0-15) */
....@@ -13206,6 +18296,7 @@
1320618296 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9
1320718297 /* enum: CTLE EQ Resistor (DC Gain) */
1320818298 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa
18299
+#define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_OFST 0
1320918300 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8
1321018301 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 5
1321118302 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
....@@ -13225,17 +18316,22 @@
1322518316 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_14 0xe /* enum */
1322618317 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_15 0xf /* enum */
1322718318 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x10 /* enum */
18319
+#define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_OFST 0
1322818320 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 13
1322918321 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1
18322
+#define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_OFST 0
1323018323 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 14
1323118324 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 10
18325
+#define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_OFST 0
1323218326 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24
1323318327 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8
1323418328 
1323518329 /* MC_CMD_PCIE_TUNE_RXEQ_SET_IN msgrequest */
1323618330 #define    MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMIN 8
1323718331 #define    MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMAX 252
18332
+#define    MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMAX_MCDI2 1020
1323818333 #define    MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num))
18334
+#define    MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_NUM(len) (((len)-4)/4)
1323918335 /* Requested operation */
1324018336 #define       MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_OFST 0
1324118337 #define       MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_LEN 1
....@@ -13247,20 +18343,27 @@
1324718343 #define       MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LEN 4
1324818344 #define       MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1
1324918345 #define       MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62
18346
+#define       MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MAXNUM_MCDI2 254
18347
+#define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_OFST 4
1325018348 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0
1325118349 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8
1325218350 /*             Enum values, see field(s): */
1325318351 /*                MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_ID */
18352
+#define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_OFST 4
1325418353 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8
1325518354 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 5
1325618355 /*             Enum values, see field(s): */
1325718356 /*                MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */
18357
+#define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_OFST 4
1325818358 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 13
1325918359 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1
18360
+#define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_OFST 4
1326018361 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_LBN 14
1326118362 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 2
18363
+#define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_OFST 4
1326218364 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16
1326318365 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8
18366
+#define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_OFST 4
1326418367 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24
1326518368 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8
1326618369 
....@@ -13279,12 +18382,16 @@
1327918382 /* MC_CMD_PCIE_TUNE_TXEQ_GET_OUT msgresponse */
1328018383 #define    MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4
1328118384 #define    MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252
18385
+#define    MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX_MCDI2 1020
1328218386 #define    MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))
18387
+#define    MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
1328318388 /* RXEQ Parameter */
1328418389 #define       MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0
1328518390 #define       MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4
1328618391 #define       MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1
1328718392 #define       MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63
18393
+#define       MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM_MCDI2 255
18394
+#define        MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_OFST 0
1328818395 #define        MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0
1328918396 #define        MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8
1329018397 /* enum: TxMargin (PIPE) */
....@@ -13297,12 +18404,15 @@
1329718404 #define          MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3
1329818405 /* enum: De-emphasis coefficient C(+1) (PIPE) */
1329918406 #define          MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4
18407
+#define        MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_OFST 0
1330018408 #define        MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8
1330118409 #define        MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4
1330218410 /*             Enum values, see field(s): */
1330318411 /*                MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */
18412
+#define        MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_OFST 0
1330418413 #define        MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12
1330518414 #define        MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12
18415
+#define        MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_OFST 0
1330618416 #define        MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24
1330718417 #define        MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8
1330818418 
....@@ -13332,11 +18442,14 @@
1333218442 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT msgresponse */
1333318443 #define    MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0
1333418444 #define    MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252
18445
+#define    MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX_MCDI2 1020
1333518446 #define    MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num))
18447
+#define    MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_NUM(len) (((len)-0)/2)
1333618448 #define       MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0
1333718449 #define       MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2
1333818450 #define       MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0
1333918451 #define       MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126
18452
+#define       MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM_MCDI2 510
1334018453 
1334118454 /* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN msgrequest */
1334218455 #define    MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN_LEN 0
....@@ -13351,6 +18464,7 @@
1335118464  * - not used for V3 licensing
1335218465  */
1335318466 #define MC_CMD_LICENSING 0xf3
18467
+#undef MC_CMD_0xf3_PRIVILEGE_CTG
1335418468 
1335518469 #define MC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1335618470 
....@@ -13406,6 +18520,7 @@
1340618520  * - V3 licensing (Medford)
1340718521  */
1340818522 #define MC_CMD_LICENSING_V3 0xd0
18523
+#undef MC_CMD_0xd0_PRIVILEGE_CTG
1340918524 
1341018525 #define MC_CMD_0xd0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1341118526 
....@@ -13475,6 +18590,7 @@
1347518590  * partition - V3 licensing (Medford)
1347618591  */
1347718592 #define MC_CMD_LICENSING_GET_ID_V3 0xd1
18593
+#undef MC_CMD_0xd1_PRIVILEGE_CTG
1347818594 
1347918595 #define MC_CMD_0xd1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1348018596 
....@@ -13484,7 +18600,9 @@
1348418600 /* MC_CMD_LICENSING_GET_ID_V3_OUT msgresponse */
1348518601 #define    MC_CMD_LICENSING_GET_ID_V3_OUT_LENMIN 8
1348618602 #define    MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX 252
18603
+#define    MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX_MCDI2 1020
1348718604 #define    MC_CMD_LICENSING_GET_ID_V3_OUT_LEN(num) (8+1*(num))
18605
+#define    MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_NUM(len) (((len)-8)/1)
1348818606 /* type of license (eg 3) */
1348918607 #define       MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 0
1349018608 #define       MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_LEN 4
....@@ -13496,6 +18614,7 @@
1349618614 #define       MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LEN 1
1349718615 #define       MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MINNUM 0
1349818616 #define       MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM 244
18617
+#define       MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM_MCDI2 1012
1349918618 
1350018619 
1350118620 /***********************************/
....@@ -13504,6 +18623,7 @@
1350418623  * This will fail on a single-core system.
1350518624  */
1350618625 #define MC_CMD_MC2MC_PROXY 0xf4
18626
+#undef MC_CMD_0xf4_PRIVILEGE_CTG
1350718627 
1350818628 #define MC_CMD_0xf4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1350918629 
....@@ -13521,6 +18641,7 @@
1352118641  * or a reboot of the MC.) Not used for V3 licensing
1352218642  */
1352318643 #define MC_CMD_GET_LICENSED_APP_STATE 0xf5
18644
+#undef MC_CMD_0xf5_PRIVILEGE_CTG
1352418645 
1352518646 #define MC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1352618647 
....@@ -13548,6 +18669,7 @@
1354818669  * operation or a reboot of the MC.) Used for V3 licensing (Medford)
1354918670  */
1355018671 #define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd2
18672
+#undef MC_CMD_0xd2_PRIVILEGE_CTG
1355118673 
1355218674 #define MC_CMD_0xd2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1355318675 
....@@ -13574,11 +18696,12 @@
1357418696 
1357518697 /***********************************/
1357618698 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES
13577
- * Query the state of one or more licensed features. (Note that the actual
18699
+ * Query the state of an one or more licensed features. (Note that the actual
1357818700  * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE
1357918701  * operation or a reboot of the MC.) Used for V3 licensing (Medford)
1358018702  */
1358118703 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3
18704
+#undef MC_CMD_0xd3_PRIVILEGE_CTG
1358218705 
1358318706 #define MC_CMD_0xd3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1358418707 
....@@ -13607,13 +18730,16 @@
1360718730  * licensing.
1360818731  */
1360918732 #define MC_CMD_LICENSED_APP_OP 0xf6
18733
+#undef MC_CMD_0xf6_PRIVILEGE_CTG
1361018734 
1361118735 #define MC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1361218736 
1361318737 /* MC_CMD_LICENSED_APP_OP_IN msgrequest */
1361418738 #define    MC_CMD_LICENSED_APP_OP_IN_LENMIN 8
1361518739 #define    MC_CMD_LICENSED_APP_OP_IN_LENMAX 252
18740
+#define    MC_CMD_LICENSED_APP_OP_IN_LENMAX_MCDI2 1020
1361618741 #define    MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num))
18742
+#define    MC_CMD_LICENSED_APP_OP_IN_ARGS_NUM(len) (((len)-8)/4)
1361718743 /* application ID */
1361818744 #define       MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0
1361918745 #define       MC_CMD_LICENSED_APP_OP_IN_APP_ID_LEN 4
....@@ -13629,16 +18755,20 @@
1362918755 #define       MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4
1363018756 #define       MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0
1363118757 #define       MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM 61
18758
+#define       MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM_MCDI2 253
1363218759 
1363318760 /* MC_CMD_LICENSED_APP_OP_OUT msgresponse */
1363418761 #define    MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0
1363518762 #define    MC_CMD_LICENSED_APP_OP_OUT_LENMAX 252
18763
+#define    MC_CMD_LICENSED_APP_OP_OUT_LENMAX_MCDI2 1020
1363618764 #define    MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num))
18765
+#define    MC_CMD_LICENSED_APP_OP_OUT_RESULT_NUM(len) (((len)-0)/4)
1363718766 /* result specific to this particular operation */
1363818767 #define       MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0
1363918768 #define       MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4
1364018769 #define       MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0
1364118770 #define       MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM 63
18771
+#define       MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM_MCDI2 255
1364218772 
1364318773 /* MC_CMD_LICENSED_APP_OP_VALIDATE_IN msgrequest */
1364418774 #define    MC_CMD_LICENSED_APP_OP_VALIDATE_IN_LEN 72
....@@ -13683,6 +18813,7 @@
1368318813  * (Medford)
1368418814  */
1368518815 #define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd4
18816
+#undef MC_CMD_0xd4_PRIVILEGE_CTG
1368618817 
1368718818 #define MC_CMD_0xd4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1368818819 
....@@ -13735,6 +18866,7 @@
1373518866  * Mask features - V3 licensing (Medford)
1373618867  */
1373718868 #define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd5
18869
+#undef MC_CMD_0xd5_PRIVILEGE_CTG
1373818870 
1373918871 #define MC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1374018872 
....@@ -13766,6 +18898,7 @@
1376618898  * erased when the adapter is power cycled
1376718899  */
1376818900 #define MC_CMD_LICENSING_V3_TEMPORARY 0xd6
18901
+#undef MC_CMD_0xd6_PRIVILEGE_CTG
1376918902 
1377018903 #define MC_CMD_0xd6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1377118904 
....@@ -13835,6 +18968,7 @@
1383518968  * delivered to a specific queue, or a set of queues with RSS.
1383618969  */
1383718970 #define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7
18971
+#undef MC_CMD_0xf7_PRIVILEGE_CTG
1383818972 
1383918973 #define MC_CMD_0xf7_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1384018974 
....@@ -13843,8 +18977,10 @@
1384318977 /* configuration flags */
1384418978 #define       MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0
1384518979 #define       MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4
18980
+#define        MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_OFST 0
1384618981 #define        MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0
1384718982 #define        MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1
18983
+#define        MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_OFST 0
1384818984 #define        MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1
1384918985 #define        MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1
1385018986 /* receive queue handle (for RSS mode, this is the base queue) */
....@@ -13875,6 +19011,7 @@
1387519011  * the configuration.
1387619012  */
1387719013 #define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8
19014
+#undef MC_CMD_0xf8_PRIVILEGE_CTG
1387819015 
1387919016 #define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1388019017 
....@@ -13886,8 +19023,10 @@
1388619023 /* configuration flags */
1388719024 #define       MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0
1388819025 #define       MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4
19026
+#define        MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_OFST 0
1388919027 #define        MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0
1389019028 #define        MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1
19029
+#define        MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_OFST 0
1389119030 #define        MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1
1389219031 #define        MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1
1389319032 /* receiving queue handle (for RSS mode, this is the base queue) */
....@@ -13910,13 +19049,16 @@
1391019049  * Change configuration related to the parser-dispatcher subsystem.
1391119050  */
1391219051 #define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9
19052
+#undef MC_CMD_0xf9_PRIVILEGE_CTG
1391319053 
1391419054 #define MC_CMD_0xf9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1391519055 
1391619056 /* MC_CMD_SET_PARSER_DISP_CONFIG_IN msgrequest */
1391719057 #define    MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMIN 12
1391819058 #define    MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX 252
19059
+#define    MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX_MCDI2 1020
1391919060 #define    MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num))
19061
+#define    MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_NUM(len) (((len)-8)/4)
1392019062 /* the type of configuration setting to change */
1392119063 #define       MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0
1392219064 #define       MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4
....@@ -13941,6 +19083,7 @@
1394119083 #define       MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 4
1394219084 #define       MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MINNUM 1
1394319085 #define       MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM 61
19086
+#define       MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM_MCDI2 253
1394419087 
1394519088 /* MC_CMD_SET_PARSER_DISP_CONFIG_OUT msgresponse */
1394619089 #define    MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0
....@@ -13951,6 +19094,7 @@
1395119094  * Read configuration related to the parser-dispatcher subsystem.
1395219095  */
1395319096 #define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa
19097
+#undef MC_CMD_0xfa_PRIVILEGE_CTG
1395419098 
1395519099 #define MC_CMD_0xfa_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1395619100 
....@@ -13970,7 +19114,9 @@
1397019114 /* MC_CMD_GET_PARSER_DISP_CONFIG_OUT msgresponse */
1397119115 #define    MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 4
1397219116 #define    MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX 252
19117
+#define    MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX_MCDI2 1020
1397319118 #define    MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num))
19119
+#define    MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_NUM(len) (((len)-0)/4)
1397419120 /* current value: the details depend on the type of configuration setting being
1397519121  * read
1397619122  */
....@@ -13978,6 +19124,7 @@
1397819124 #define       MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_LEN 4
1397919125 #define       MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MINNUM 1
1398019126 #define       MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM 63
19127
+#define       MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM_MCDI2 255
1398119128 
1398219129 
1398319130 /***********************************/
....@@ -13991,6 +19138,7 @@
1399119138  * dedicated as TX sniff receivers.
1399219139  */
1399319140 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb
19141
+#undef MC_CMD_0xfb_PRIVILEGE_CTG
1399419142 
1399519143 #define MC_CMD_0xfb_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1399619144 
....@@ -13999,6 +19147,7 @@
1399919147 /* configuration flags */
1400019148 #define       MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0
1400119149 #define       MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4
19150
+#define        MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_OFST 0
1400219151 #define        MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0
1400319152 #define        MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1
1400419153 /* receive queue handle (for RSS mode, this is the base queue) */
....@@ -14029,6 +19178,7 @@
1402919178  * the configuration.
1403019179  */
1403119180 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc
19181
+#undef MC_CMD_0xfc_PRIVILEGE_CTG
1403219182 
1403319183 #define MC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1403419184 
....@@ -14040,6 +19190,7 @@
1404019190 /* configuration flags */
1404119191 #define       MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0
1404219192 #define       MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4
19193
+#define        MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_OFST 0
1404319194 #define        MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0
1404419195 #define        MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1
1404519196 /* receiving queue handle (for RSS mode, this is the base queue) */
....@@ -14062,6 +19213,7 @@
1406219213  * Per queue rx error stats.
1406319214  */
1406419215 #define MC_CMD_RMON_STATS_RX_ERRORS 0xfe
19216
+#undef MC_CMD_0xfe_PRIVILEGE_CTG
1406519217 
1406619218 #define MC_CMD_0xfe_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1406719219 
....@@ -14072,6 +19224,7 @@
1407219224 #define       MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_LEN 4
1407319225 #define       MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_OFST 4
1407419226 #define       MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_LEN 4
19227
+#define        MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_OFST 4
1407519228 #define        MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_LBN 0
1407619229 #define        MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_WIDTH 1
1407719230 
....@@ -14092,6 +19245,7 @@
1409219245  * Find out about available PCIE resources
1409319246  */
1409419247 #define MC_CMD_GET_PCIE_RESOURCE_INFO 0xfd
19248
+#undef MC_CMD_0xfd_PRIVILEGE_CTG
1409519249 
1409619250 #define MC_CMD_0xfd_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1409719251 
....@@ -14130,6 +19284,7 @@
1413019284  * Find out about available port modes
1413119285  */
1413219286 #define MC_CMD_GET_PORT_MODES 0xff
19287
+#undef MC_CMD_0xff_PRIVILEGE_CTG
1413319288 
1413419289 #define MC_CMD_0xff_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1413519290 
....@@ -14138,7 +19293,9 @@
1413819293 
1413919294 /* MC_CMD_GET_PORT_MODES_OUT msgresponse */
1414019295 #define    MC_CMD_GET_PORT_MODES_OUT_LEN 12
14141
-/* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*) */
19296
+/* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*)
19297
+ * that are supported for customer use in production firmware.
19298
+ */
1414219299 #define       MC_CMD_GET_PORT_MODES_OUT_MODES_OFST 0
1414319300 #define       MC_CMD_GET_PORT_MODES_OUT_MODES_LEN 4
1414419301 /* Default (canonical) board mode */
....@@ -14148,12 +19305,66 @@
1414819305 #define       MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST 8
1414919306 #define       MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_LEN 4
1415019307 
19308
+/* MC_CMD_GET_PORT_MODES_OUT_V2 msgresponse */
19309
+#define    MC_CMD_GET_PORT_MODES_OUT_V2_LEN 16
19310
+/* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*)
19311
+ * that are supported for customer use in production firmware.
19312
+ */
19313
+#define       MC_CMD_GET_PORT_MODES_OUT_V2_MODES_OFST 0
19314
+#define       MC_CMD_GET_PORT_MODES_OUT_V2_MODES_LEN 4
19315
+/* Default (canonical) board mode */
19316
+#define       MC_CMD_GET_PORT_MODES_OUT_V2_DEFAULT_MODE_OFST 4
19317
+#define       MC_CMD_GET_PORT_MODES_OUT_V2_DEFAULT_MODE_LEN 4
19318
+/* Current board mode */
19319
+#define       MC_CMD_GET_PORT_MODES_OUT_V2_CURRENT_MODE_OFST 8
19320
+#define       MC_CMD_GET_PORT_MODES_OUT_V2_CURRENT_MODE_LEN 4
19321
+/* Bitmask of engineering port modes available on the board (indexed by
19322
+ * TLV_PORT_MODE_*). A superset of MC_CMD_GET_PORT_MODES_OUT/MODES that
19323
+ * contains all modes implemented in firmware for a particular board. Modes
19324
+ * listed in MODES are considered production modes and should be exposed in
19325
+ * userland tools. Modes listed in in ENGINEERING_MODES, but not in MODES
19326
+ * should be considered hidden (not to be exposed in userland tools) and for
19327
+ * engineering use only. There are no other semantic differences and any mode
19328
+ * listed in either MODES or ENGINEERING_MODES can be set on the board.
19329
+ */
19330
+#define       MC_CMD_GET_PORT_MODES_OUT_V2_ENGINEERING_MODES_OFST 12
19331
+#define       MC_CMD_GET_PORT_MODES_OUT_V2_ENGINEERING_MODES_LEN 4
19332
+
19333
+
19334
+/***********************************/
19335
+/* MC_CMD_OVERRIDE_PORT_MODE
19336
+ * Override flash config port mode for subsequent MC reboot(s). Override data
19337
+ * is stored in the presistent data section of DMEM and activated on next MC
19338
+ * warm reboot. A cold reboot resets the override. It is assumed that a
19339
+ * sufficient number of PFs are available and that port mapping is valid for
19340
+ * the new port mode, as the override does not affect PF configuration.
19341
+ */
19342
+#define MC_CMD_OVERRIDE_PORT_MODE 0x137
19343
+#undef MC_CMD_0x137_PRIVILEGE_CTG
19344
+
19345
+#define MC_CMD_0x137_PRIVILEGE_CTG SRIOV_CTG_ADMIN
19346
+
19347
+/* MC_CMD_OVERRIDE_PORT_MODE_IN msgrequest */
19348
+#define    MC_CMD_OVERRIDE_PORT_MODE_IN_LEN 8
19349
+#define       MC_CMD_OVERRIDE_PORT_MODE_IN_FLAGS_OFST 0
19350
+#define       MC_CMD_OVERRIDE_PORT_MODE_IN_FLAGS_LEN 4
19351
+#define        MC_CMD_OVERRIDE_PORT_MODE_IN_ENABLE_OFST 0
19352
+#define        MC_CMD_OVERRIDE_PORT_MODE_IN_ENABLE_LBN 0
19353
+#define        MC_CMD_OVERRIDE_PORT_MODE_IN_ENABLE_WIDTH 1
19354
+/* New mode (TLV_PORT_MODE_*) to set, if override enabled */
19355
+#define       MC_CMD_OVERRIDE_PORT_MODE_IN_MODE_OFST 4
19356
+#define       MC_CMD_OVERRIDE_PORT_MODE_IN_MODE_LEN 4
19357
+
19358
+/* MC_CMD_OVERRIDE_PORT_MODE_OUT msgresponse */
19359
+#define    MC_CMD_OVERRIDE_PORT_MODE_OUT_LEN 0
19360
+
1415119361 
1415219362 /***********************************/
1415319363 /* MC_CMD_READ_ATB
1415419364  * Sample voltages on the ATB
1415519365  */
1415619366 #define MC_CMD_READ_ATB 0x100
19367
+#undef MC_CMD_0x100_PRIVILEGE_CTG
1415719368 
1415819369 #define MC_CMD_0x100_PRIVILEGE_CTG SRIOV_CTG_INSECURE
1415919370 
....@@ -14183,6 +19394,7 @@
1418319394  * enums here must correspond with those in MC_CMD_WORKAROUND.
1418419395  */
1418519396 #define MC_CMD_GET_WORKAROUNDS 0x59
19397
+#undef MC_CMD_0x59_PRIVILEGE_CTG
1418619398 
1418719399 #define MC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1418819400 
....@@ -14219,6 +19431,7 @@
1421919431  * Read/set privileges of an arbitrary PCIe function
1422019432  */
1422119433 #define MC_CMD_PRIVILEGE_MASK 0x5a
19434
+#undef MC_CMD_0x5a_PRIVILEGE_CTG
1422219435 
1422319436 #define MC_CMD_0x5a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1422419437 
....@@ -14229,8 +19442,10 @@
1422919442  */
1423019443 #define       MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0
1423119444 #define       MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_LEN 4
19445
+#define        MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_OFST 0
1423219446 #define        MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0
1423319447 #define        MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_WIDTH 16
19448
+#define        MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_OFST 0
1423419449 #define        MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_LBN 16
1423519450 #define        MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_WIDTH 16
1423619451 #define          MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */
....@@ -14269,6 +19484,12 @@
1426919484  * are not permitted on secure adapters regardless of the privilege mask.
1427019485  */
1427119486 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE 0x4000
19487
+/* enum: Trusted Server Adapter (TSA) / ServerLock. Privilege for
19488
+ * administrator-level operations that are not allowed from the local host once
19489
+ * an adapter has Bound to a remote ServerLock Controller (see doxbox
19490
+ * SF-117064-DG for background).
19491
+ */
19492
+#define          MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN_TSA_UNBOUND 0x8000
1427219493 /* enum: Set this bit to indicate that a new privilege mask is to be set,
1427319494  * otherwise the command will only read the existing mask.
1427419495  */
....@@ -14286,6 +19507,7 @@
1428619507  * Read/set link state mode of a VF
1428719508  */
1428819509 #define MC_CMD_LINK_STATE_MODE 0x5c
19510
+#undef MC_CMD_0x5c_PRIVILEGE_CTG
1428919511 
1429019512 #define MC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1429119513 
....@@ -14296,8 +19518,10 @@
1429619518  */
1429719519 #define       MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0
1429819520 #define       MC_CMD_LINK_STATE_MODE_IN_FUNCTION_LEN 4
19521
+#define        MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_OFST 0
1429919522 #define        MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0
1430019523 #define        MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_WIDTH 16
19524
+#define        MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_OFST 0
1430119525 #define        MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_LBN 16
1430219526 #define        MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_WIDTH 16
1430319527 /* New link state mode to be set */
....@@ -14322,6 +19546,7 @@
1432219546  * parameter to MC_CMD_INIT_RXQ.
1432319547  */
1432419548 #define MC_CMD_GET_SNAPSHOT_LENGTH 0x101
19549
+#undef MC_CMD_0x101_PRIVILEGE_CTG
1432519550 
1432619551 #define MC_CMD_0x101_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1432719552 
....@@ -14343,6 +19568,7 @@
1434319568  * Additional fuse diagnostics
1434419569  */
1434519570 #define MC_CMD_FUSE_DIAGS 0x102
19571
+#undef MC_CMD_0x102_PRIVILEGE_CTG
1434619572 
1434719573 #define MC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_INSECURE
1434819574 
....@@ -14396,6 +19622,7 @@
1439619622  * included in one of the masks provided.
1439719623  */
1439819624 #define MC_CMD_PRIVILEGE_MODIFY 0x60
19625
+#undef MC_CMD_0x60_PRIVILEGE_CTG
1439919626 
1440019627 #define MC_CMD_0x60_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1440119628 
....@@ -14413,8 +19640,10 @@
1441319640 /* For VFS_OF_PF specify the PF, for ONE specify the target function */
1441419641 #define       MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4
1441519642 #define       MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_LEN 4
19643
+#define        MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_OFST 4
1441619644 #define        MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0
1441719645 #define        MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_WIDTH 16
19646
+#define        MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_OFST 4
1441819647 #define        MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_LBN 16
1441919648 #define        MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_WIDTH 16
1442019649 /* Privileges to be added to the target functions. For privilege definitions
....@@ -14437,6 +19666,7 @@
1443719666  * Read XPM memory
1443819667  */
1443919668 #define MC_CMD_XPM_READ_BYTES 0x103
19669
+#undef MC_CMD_0x103_PRIVILEGE_CTG
1444019670 
1444119671 #define MC_CMD_0x103_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1444219672 
....@@ -14452,12 +19682,15 @@
1445219682 /* MC_CMD_XPM_READ_BYTES_OUT msgresponse */
1445319683 #define    MC_CMD_XPM_READ_BYTES_OUT_LENMIN 0
1445419684 #define    MC_CMD_XPM_READ_BYTES_OUT_LENMAX 252
19685
+#define    MC_CMD_XPM_READ_BYTES_OUT_LENMAX_MCDI2 1020
1445519686 #define    MC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num))
19687
+#define    MC_CMD_XPM_READ_BYTES_OUT_DATA_NUM(len) (((len)-0)/1)
1445619688 /* Data */
1445719689 #define       MC_CMD_XPM_READ_BYTES_OUT_DATA_OFST 0
1445819690 #define       MC_CMD_XPM_READ_BYTES_OUT_DATA_LEN 1
1445919691 #define       MC_CMD_XPM_READ_BYTES_OUT_DATA_MINNUM 0
1446019692 #define       MC_CMD_XPM_READ_BYTES_OUT_DATA_MAXNUM 252
19693
+#define       MC_CMD_XPM_READ_BYTES_OUT_DATA_MAXNUM_MCDI2 1020
1446119694 
1446219695 
1446319696 /***********************************/
....@@ -14465,13 +19698,16 @@
1446519698  * Write XPM memory
1446619699  */
1446719700 #define MC_CMD_XPM_WRITE_BYTES 0x104
19701
+#undef MC_CMD_0x104_PRIVILEGE_CTG
1446819702 
1446919703 #define MC_CMD_0x104_PRIVILEGE_CTG SRIOV_CTG_INSECURE
1447019704 
1447119705 /* MC_CMD_XPM_WRITE_BYTES_IN msgrequest */
1447219706 #define    MC_CMD_XPM_WRITE_BYTES_IN_LENMIN 8
1447319707 #define    MC_CMD_XPM_WRITE_BYTES_IN_LENMAX 252
19708
+#define    MC_CMD_XPM_WRITE_BYTES_IN_LENMAX_MCDI2 1020
1447419709 #define    MC_CMD_XPM_WRITE_BYTES_IN_LEN(num) (8+1*(num))
19710
+#define    MC_CMD_XPM_WRITE_BYTES_IN_DATA_NUM(len) (((len)-8)/1)
1447519711 /* Start address (byte) */
1447619712 #define       MC_CMD_XPM_WRITE_BYTES_IN_ADDR_OFST 0
1447719713 #define       MC_CMD_XPM_WRITE_BYTES_IN_ADDR_LEN 4
....@@ -14483,6 +19719,7 @@
1448319719 #define       MC_CMD_XPM_WRITE_BYTES_IN_DATA_LEN 1
1448419720 #define       MC_CMD_XPM_WRITE_BYTES_IN_DATA_MINNUM 0
1448519721 #define       MC_CMD_XPM_WRITE_BYTES_IN_DATA_MAXNUM 244
19722
+#define       MC_CMD_XPM_WRITE_BYTES_IN_DATA_MAXNUM_MCDI2 1012
1448619723 
1448719724 /* MC_CMD_XPM_WRITE_BYTES_OUT msgresponse */
1448819725 #define    MC_CMD_XPM_WRITE_BYTES_OUT_LEN 0
....@@ -14493,6 +19730,7 @@
1449319730  * Read XPM sector
1449419731  */
1449519732 #define MC_CMD_XPM_READ_SECTOR 0x105
19733
+#undef MC_CMD_0x105_PRIVILEGE_CTG
1449619734 
1449719735 #define MC_CMD_0x105_PRIVILEGE_CTG SRIOV_CTG_INSECURE
1449819736 
....@@ -14508,7 +19746,9 @@
1450819746 /* MC_CMD_XPM_READ_SECTOR_OUT msgresponse */
1450919747 #define    MC_CMD_XPM_READ_SECTOR_OUT_LENMIN 4
1451019748 #define    MC_CMD_XPM_READ_SECTOR_OUT_LENMAX 36
19749
+#define    MC_CMD_XPM_READ_SECTOR_OUT_LENMAX_MCDI2 36
1451119750 #define    MC_CMD_XPM_READ_SECTOR_OUT_LEN(num) (4+1*(num))
19751
+#define    MC_CMD_XPM_READ_SECTOR_OUT_DATA_NUM(len) (((len)-4)/1)
1451219752 /* Sector type */
1451319753 #define       MC_CMD_XPM_READ_SECTOR_OUT_TYPE_OFST 0
1451419754 #define       MC_CMD_XPM_READ_SECTOR_OUT_TYPE_LEN 4
....@@ -14522,6 +19762,7 @@
1452219762 #define       MC_CMD_XPM_READ_SECTOR_OUT_DATA_LEN 1
1452319763 #define       MC_CMD_XPM_READ_SECTOR_OUT_DATA_MINNUM 0
1452419764 #define       MC_CMD_XPM_READ_SECTOR_OUT_DATA_MAXNUM 32
19765
+#define       MC_CMD_XPM_READ_SECTOR_OUT_DATA_MAXNUM_MCDI2 32
1452519766 
1452619767 
1452719768 /***********************************/
....@@ -14529,13 +19770,16 @@
1452919770  * Write XPM sector
1453019771  */
1453119772 #define MC_CMD_XPM_WRITE_SECTOR 0x106
19773
+#undef MC_CMD_0x106_PRIVILEGE_CTG
1453219774 
1453319775 #define MC_CMD_0x106_PRIVILEGE_CTG SRIOV_CTG_INSECURE
1453419776 
1453519777 /* MC_CMD_XPM_WRITE_SECTOR_IN msgrequest */
1453619778 #define    MC_CMD_XPM_WRITE_SECTOR_IN_LENMIN 12
1453719779 #define    MC_CMD_XPM_WRITE_SECTOR_IN_LENMAX 44
19780
+#define    MC_CMD_XPM_WRITE_SECTOR_IN_LENMAX_MCDI2 44
1453819781 #define    MC_CMD_XPM_WRITE_SECTOR_IN_LEN(num) (12+1*(num))
19782
+#define    MC_CMD_XPM_WRITE_SECTOR_IN_DATA_NUM(len) (((len)-12)/1)
1453919783 /* If writing fails due to an uncorrectable error, try up to RETRIES following
1454019784  * sectors (or until no more space available). If 0, only one write attempt is
1454119785  * made. Note that uncorrectable errors are unlikely, thanks to XPM self-repair
....@@ -14558,6 +19802,7 @@
1455819802 #define       MC_CMD_XPM_WRITE_SECTOR_IN_DATA_LEN 1
1455919803 #define       MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MINNUM 0
1456019804 #define       MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MAXNUM 32
19805
+#define       MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MAXNUM_MCDI2 32
1456119806 
1456219807 /* MC_CMD_XPM_WRITE_SECTOR_OUT msgresponse */
1456319808 #define    MC_CMD_XPM_WRITE_SECTOR_OUT_LEN 4
....@@ -14571,6 +19816,7 @@
1457119816  * Invalidate XPM sector
1457219817  */
1457319818 #define MC_CMD_XPM_INVALIDATE_SECTOR 0x107
19819
+#undef MC_CMD_0x107_PRIVILEGE_CTG
1457419820 
1457519821 #define MC_CMD_0x107_PRIVILEGE_CTG SRIOV_CTG_INSECURE
1457619822 
....@@ -14589,6 +19835,7 @@
1458919835  * Blank-check XPM memory and report bad locations
1459019836  */
1459119837 #define MC_CMD_XPM_BLANK_CHECK 0x108
19838
+#undef MC_CMD_0x108_PRIVILEGE_CTG
1459219839 
1459319840 #define MC_CMD_0x108_PRIVILEGE_CTG SRIOV_CTG_INSECURE
1459419841 
....@@ -14604,7 +19851,9 @@
1460419851 /* MC_CMD_XPM_BLANK_CHECK_OUT msgresponse */
1460519852 #define    MC_CMD_XPM_BLANK_CHECK_OUT_LENMIN 4
1460619853 #define    MC_CMD_XPM_BLANK_CHECK_OUT_LENMAX 252
19854
+#define    MC_CMD_XPM_BLANK_CHECK_OUT_LENMAX_MCDI2 1020
1460719855 #define    MC_CMD_XPM_BLANK_CHECK_OUT_LEN(num) (4+2*(num))
19856
+#define    MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_NUM(len) (((len)-4)/2)
1460819857 /* Total number of bad (non-blank) locations */
1460919858 #define       MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_OFST 0
1461019859 #define       MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_LEN 4
....@@ -14615,6 +19864,7 @@
1461519864 #define       MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_LEN 2
1461619865 #define       MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MINNUM 0
1461719866 #define       MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MAXNUM 124
19867
+#define       MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MAXNUM_MCDI2 508
1461819868 
1461919869 
1462019870 /***********************************/
....@@ -14622,6 +19872,7 @@
1462219872  * Blank-check and repair XPM memory
1462319873  */
1462419874 #define MC_CMD_XPM_REPAIR 0x109
19875
+#undef MC_CMD_0x109_PRIVILEGE_CTG
1462519876 
1462619877 #define MC_CMD_0x109_PRIVILEGE_CTG SRIOV_CTG_INSECURE
1462719878 
....@@ -14644,6 +19895,7 @@
1464419895  * be performed on an unprogrammed part.
1464519896  */
1464619897 #define MC_CMD_XPM_DECODER_TEST 0x10a
19898
+#undef MC_CMD_0x10a_PRIVILEGE_CTG
1464719899 
1464819900 #define MC_CMD_0x10a_PRIVILEGE_CTG SRIOV_CTG_INSECURE
1464919901 
....@@ -14663,6 +19915,7 @@
1466319915  * first available location to use, or fail with ENOSPC if none left.
1466419916  */
1466519917 #define MC_CMD_XPM_WRITE_TEST 0x10b
19918
+#undef MC_CMD_0x10b_PRIVILEGE_CTG
1466619919 
1466719920 #define MC_CMD_0x10b_PRIVILEGE_CTG SRIOV_CTG_INSECURE
1466819921 
....@@ -14683,6 +19936,7 @@
1468319936  * does match, otherwise it will respond with success before it jumps to IMEM.
1468419937  */
1468519938 #define MC_CMD_EXEC_SIGNED 0x10c
19939
+#undef MC_CMD_0x10c_PRIVILEGE_CTG
1468619940 
1468719941 #define MC_CMD_0x10c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1468819942 
....@@ -14712,6 +19966,7 @@
1471219966  * MC_CMD_EXEC_SIGNED.
1471319967  */
1471419968 #define MC_CMD_PREPARE_SIGNED 0x10d
19969
+#undef MC_CMD_0x10d_PRIVILEGE_CTG
1471519970 
1471619971 #define MC_CMD_0x10d_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1471719972 
....@@ -14756,16 +20011,20 @@
1475620011  * cause all functions to see a reset. (Available on Medford only.)
1475720012  */
1475820013 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117
20014
+#undef MC_CMD_0x117_PRIVILEGE_CTG
1475920015 
1476020016 #define MC_CMD_0x117_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1476120017 
1476220018 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN msgrequest */
1476320019 #define    MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMIN 4
1476420020 #define    MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX 68
20021
+#define    MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX_MCDI2 68
1476520022 #define    MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num) (4+4*(num))
20023
+#define    MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_NUM(len) (((len)-4)/4)
1476620024 /* Flags */
1476720025 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST 0
1476820026 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_LEN 2
20027
+#define        MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_OFST 0
1476920028 #define        MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_LBN 0
1477020029 #define        MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_WIDTH 1
1477120030 /* The number of entries in the ENTRIES array */
....@@ -14778,12 +20037,14 @@
1477820037 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_LEN 4
1477920038 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MINNUM 0
1478020039 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM 16
20040
+#define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM_MCDI2 16
1478120041 
1478220042 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT msgresponse */
1478320043 #define    MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN 2
1478420044 /* Flags */
1478520045 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_OFST 0
1478620046 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_LEN 2
20047
+#define        MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_OFST 0
1478720048 #define        MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 0
1478820049 #define        MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_WIDTH 1
1478920050 
....@@ -14796,6 +20057,7 @@
1479620057  * priority.
1479720058  */
1479820059 #define MC_CMD_RX_BALANCING 0x118
20060
+#undef MC_CMD_0x118_PRIVILEGE_CTG
1479920061 
1480020062 #define MC_CMD_0x118_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1480120063 
....@@ -14824,13 +20086,16 @@
1482420086  * if the tag is already present.
1482520087  */
1482620088 #define MC_CMD_NVRAM_PRIVATE_APPEND 0x11c
20089
+#undef MC_CMD_0x11c_PRIVILEGE_CTG
1482720090 
1482820091 #define MC_CMD_0x11c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1482920092 
1483020093 /* MC_CMD_NVRAM_PRIVATE_APPEND_IN msgrequest */
1483120094 #define    MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMIN 9
1483220095 #define    MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMAX 252
20096
+#define    MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMAX_MCDI2 1020
1483320097 #define    MC_CMD_NVRAM_PRIVATE_APPEND_IN_LEN(num) (8+1*(num))
20098
+#define    MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_NUM(len) (((len)-8)/1)
1483420099 /* The tag to be appended */
1483520100 #define       MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_OFST 0
1483620101 #define       MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_LEN 4
....@@ -14842,6 +20107,7 @@
1484220107 #define       MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_LEN 1
1484320108 #define       MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MINNUM 1
1484420109 #define       MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MAXNUM 244
20110
+#define       MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MAXNUM_MCDI2 1012
1484520111 
1484620112 /* MC_CMD_NVRAM_PRIVATE_APPEND_OUT msgresponse */
1484720113 #define    MC_CMD_NVRAM_PRIVATE_APPEND_OUT_LEN 0
....@@ -14854,6 +20120,7 @@
1485420120  * correctly at ATE.
1485520121  */
1485620122 #define MC_CMD_XPM_VERIFY_CONTENTS 0x11b
20123
+#undef MC_CMD_0x11b_PRIVILEGE_CTG
1485720124 
1485820125 #define MC_CMD_0x11b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1485920126 
....@@ -14866,7 +20133,9 @@
1486620133 /* MC_CMD_XPM_VERIFY_CONTENTS_OUT msgresponse */
1486720134 #define    MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMIN 12
1486820135 #define    MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMAX 252
20136
+#define    MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMAX_MCDI2 1020
1486920137 #define    MC_CMD_XPM_VERIFY_CONTENTS_OUT_LEN(num) (12+1*(num))
20138
+#define    MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_NUM(len) (((len)-12)/1)
1487020139 /* Number of sectors found (test builds only) */
1487120140 #define       MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_OFST 0
1487220141 #define       MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_LEN 4
....@@ -14881,6 +20150,7 @@
1488120150 #define       MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_LEN 1
1488220151 #define       MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MINNUM 0
1488320152 #define       MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MAXNUM 240
20153
+#define       MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MAXNUM_MCDI2 1008
1488420154 
1488520155 
1488620156 /***********************************/
....@@ -14893,6 +20163,7 @@
1489320163  * and TMR_RELOAD_ACT_NS).
1489420164  */
1489520165 #define MC_CMD_SET_EVQ_TMR 0x120
20166
+#undef MC_CMD_0x120_PRIVILEGE_CTG
1489620167 
1489720168 #define MC_CMD_0x120_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1489820169 
....@@ -14930,6 +20201,7 @@
1493020201  * Query properties about the event queue timers.
1493120202  */
1493220203 #define MC_CMD_GET_EVQ_TMR_PROPERTIES 0x122
20204
+#undef MC_CMD_0x122_PRIVILEGE_CTG
1493320205 
1493420206 #define MC_CMD_0x122_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1493520207 
....@@ -14998,6 +20270,7 @@
1499820270  * non used switch buffers.
1499920271  */
1500020272 #define MC_CMD_ALLOCATE_TX_VFIFO_CP 0x11d
20273
+#undef MC_CMD_0x11d_PRIVILEGE_CTG
1500120274 
1500220275 #define MC_CMD_0x11d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1500320276 
....@@ -15049,6 +20322,7 @@
1504920322  * previously allocated common pools.
1505020323  */
1505120324 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 0x11e
20325
+#undef MC_CMD_0x11e_PRIVILEGE_CTG
1505220326 
1505320327 #define MC_CMD_0x11e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1505420328 
....@@ -15101,6 +20375,7 @@
1510120375  * ready to be re-used.
1510220376  */
1510320377 #define MC_CMD_TEARDOWN_TX_VFIFO_VF 0x11f
20378
+#undef MC_CMD_0x11f_PRIVILEGE_CTG
1510420379 
1510520380 #define MC_CMD_0x11f_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1510620381 
....@@ -15120,6 +20395,7 @@
1512020395  * it ready to be re-used.
1512120396  */
1512220397 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP 0x121
20398
+#undef MC_CMD_0x121_PRIVILEGE_CTG
1512320399 
1512420400 #define MC_CMD_0x121_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1512520401 
....@@ -15139,6 +20415,7 @@
1513920415  * not yet assigned.
1514020416  */
1514120417 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 0x124
20418
+#undef MC_CMD_0x124_PRIVILEGE_CTG
1514220419 
1514320420 #define MC_CMD_0x124_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1514420421 
....@@ -15155,4 +20432,1537 @@
1515520432 #define       MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_LEN 4
1515620433 
1515720434 
20435
+/***********************************/
20436
+/* MC_CMD_SUC_VERSION
20437
+ * Get the version of the SUC
20438
+ */
20439
+#define MC_CMD_SUC_VERSION 0x134
20440
+#undef MC_CMD_0x134_PRIVILEGE_CTG
20441
+
20442
+#define MC_CMD_0x134_PRIVILEGE_CTG SRIOV_CTG_GENERAL
20443
+
20444
+/* MC_CMD_SUC_VERSION_IN msgrequest */
20445
+#define    MC_CMD_SUC_VERSION_IN_LEN 0
20446
+
20447
+/* MC_CMD_SUC_VERSION_OUT msgresponse */
20448
+#define    MC_CMD_SUC_VERSION_OUT_LEN 24
20449
+/* The SUC firmware version as four numbers - a.b.c.d */
20450
+#define       MC_CMD_SUC_VERSION_OUT_VERSION_OFST 0
20451
+#define       MC_CMD_SUC_VERSION_OUT_VERSION_LEN 4
20452
+#define       MC_CMD_SUC_VERSION_OUT_VERSION_NUM 4
20453
+/* The date, in seconds since the Unix epoch, when the firmware image was
20454
+ * built.
20455
+ */
20456
+#define       MC_CMD_SUC_VERSION_OUT_BUILD_DATE_OFST 16
20457
+#define       MC_CMD_SUC_VERSION_OUT_BUILD_DATE_LEN 4
20458
+/* The ID of the SUC chip. This is specific to the platform but typically
20459
+ * indicates family, memory sizes etc. See SF-116728-SW for further details.
20460
+ */
20461
+#define       MC_CMD_SUC_VERSION_OUT_CHIP_ID_OFST 20
20462
+#define       MC_CMD_SUC_VERSION_OUT_CHIP_ID_LEN 4
20463
+
20464
+/* MC_CMD_SUC_BOOT_VERSION_IN msgrequest: Get the version of the SUC boot
20465
+ * loader.
20466
+ */
20467
+#define    MC_CMD_SUC_BOOT_VERSION_IN_LEN 4
20468
+#define       MC_CMD_SUC_BOOT_VERSION_IN_MAGIC_OFST 0
20469
+#define       MC_CMD_SUC_BOOT_VERSION_IN_MAGIC_LEN 4
20470
+/* enum: Requests the SUC boot version. */
20471
+#define          MC_CMD_SUC_VERSION_GET_BOOT_VERSION 0xb007700b
20472
+
20473
+/* MC_CMD_SUC_BOOT_VERSION_OUT msgresponse */
20474
+#define    MC_CMD_SUC_BOOT_VERSION_OUT_LEN 4
20475
+/* The SUC boot version */
20476
+#define       MC_CMD_SUC_BOOT_VERSION_OUT_VERSION_OFST 0
20477
+#define       MC_CMD_SUC_BOOT_VERSION_OUT_VERSION_LEN 4
20478
+
20479
+
20480
+/***********************************/
20481
+/* MC_CMD_GET_RX_PREFIX_ID
20482
+ * This command is part of the mechanism for configuring the format of the RX
20483
+ * packet prefix. It takes as input a bitmask of the fields the host would like
20484
+ * to be in the prefix. If the hardware supports RX prefixes with that
20485
+ * combination of fields, then this command returns a list of prefix-ids,
20486
+ * opaque identifiers suitable for use in the RX_PREFIX_ID field of a
20487
+ * MC_CMD_INIT_RXQ_V5_IN message. If the combination of fields is not
20488
+ * supported, returns ENOTSUP. If the firmware can't create any new prefix-ids
20489
+ * due to resource constraints, returns ENOSPC.
20490
+ */
20491
+#define MC_CMD_GET_RX_PREFIX_ID 0x13b
20492
+#undef MC_CMD_0x13b_PRIVILEGE_CTG
20493
+
20494
+#define MC_CMD_0x13b_PRIVILEGE_CTG SRIOV_CTG_GENERAL
20495
+
20496
+/* MC_CMD_GET_RX_PREFIX_ID_IN msgrequest */
20497
+#define    MC_CMD_GET_RX_PREFIX_ID_IN_LEN 8
20498
+/* Field bitmask. */
20499
+#define       MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_OFST 0
20500
+#define       MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LEN 8
20501
+#define       MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_OFST 0
20502
+#define       MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_OFST 4
20503
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_OFST 0
20504
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_LBN 0
20505
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_WIDTH 1
20506
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_VALID_OFST 0
20507
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_VALID_LBN 1
20508
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_VALID_WIDTH 1
20509
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_USER_FLAG_OFST 0
20510
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_USER_FLAG_LBN 2
20511
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_USER_FLAG_WIDTH 1
20512
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_CLASS_OFST 0
20513
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_CLASS_LBN 3
20514
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_CLASS_WIDTH 1
20515
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_PARTIAL_TSTAMP_OFST 0
20516
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_PARTIAL_TSTAMP_LBN 4
20517
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_PARTIAL_TSTAMP_WIDTH 1
20518
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_OFST 0
20519
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_LBN 5
20520
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_WIDTH 1
20521
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_USER_MARK_OFST 0
20522
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_USER_MARK_LBN 6
20523
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_USER_MARK_WIDTH 1
20524
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_VPORT_OFST 0
20525
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_VPORT_LBN 7
20526
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_VPORT_WIDTH 1
20527
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_CSUM_FRAME_OFST 0
20528
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_CSUM_FRAME_LBN 8
20529
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_CSUM_FRAME_WIDTH 1
20530
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIP_TCI_OFST 0
20531
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIP_TCI_LBN 9
20532
+#define        MC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIP_TCI_WIDTH 1
20533
+
20534
+/* MC_CMD_GET_RX_PREFIX_ID_OUT msgresponse */
20535
+#define    MC_CMD_GET_RX_PREFIX_ID_OUT_LENMIN 8
20536
+#define    MC_CMD_GET_RX_PREFIX_ID_OUT_LENMAX 252
20537
+#define    MC_CMD_GET_RX_PREFIX_ID_OUT_LENMAX_MCDI2 1020
20538
+#define    MC_CMD_GET_RX_PREFIX_ID_OUT_LEN(num) (4+4*(num))
20539
+#define    MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_NUM(len) (((len)-4)/4)
20540
+/* Number of prefix-ids returned */
20541
+#define       MC_CMD_GET_RX_PREFIX_ID_OUT_NUM_RX_PREFIX_IDS_OFST 0
20542
+#define       MC_CMD_GET_RX_PREFIX_ID_OUT_NUM_RX_PREFIX_IDS_LEN 4
20543
+/* Opaque prefix identifiers which can be passed into MC_CMD_INIT_RXQ_V5 or
20544
+ * MC_CMD_QUERY_PREFIX_ID
20545
+ */
20546
+#define       MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_OFST 4
20547
+#define       MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_LEN 4
20548
+#define       MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_MINNUM 1
20549
+#define       MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_MAXNUM 62
20550
+#define       MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_MAXNUM_MCDI2 254
20551
+
20552
+/* RX_PREFIX_FIELD_INFO structuredef: Information about a single RX prefix
20553
+ * field
20554
+ */
20555
+#define    RX_PREFIX_FIELD_INFO_LEN 4
20556
+/* The offset of the field from the start of the prefix, in bits */
20557
+#define       RX_PREFIX_FIELD_INFO_OFFSET_BITS_OFST 0
20558
+#define       RX_PREFIX_FIELD_INFO_OFFSET_BITS_LEN 2
20559
+#define       RX_PREFIX_FIELD_INFO_OFFSET_BITS_LBN 0
20560
+#define       RX_PREFIX_FIELD_INFO_OFFSET_BITS_WIDTH 16
20561
+/* The width of the field, in bits */
20562
+#define       RX_PREFIX_FIELD_INFO_WIDTH_BITS_OFST 2
20563
+#define       RX_PREFIX_FIELD_INFO_WIDTH_BITS_LEN 1
20564
+#define       RX_PREFIX_FIELD_INFO_WIDTH_BITS_LBN 16
20565
+#define       RX_PREFIX_FIELD_INFO_WIDTH_BITS_WIDTH 8
20566
+/* The type of the field. These enum values are in the same order as the fields
20567
+ * in the MC_CMD_GET_RX_PREFIX_ID_IN bitmask
20568
+ */
20569
+#define       RX_PREFIX_FIELD_INFO_TYPE_OFST 3
20570
+#define       RX_PREFIX_FIELD_INFO_TYPE_LEN 1
20571
+#define          RX_PREFIX_FIELD_INFO_LENGTH 0x0 /* enum */
20572
+#define          RX_PREFIX_FIELD_INFO_RSS_HASH_VALID 0x1 /* enum */
20573
+#define          RX_PREFIX_FIELD_INFO_USER_FLAG 0x2 /* enum */
20574
+#define          RX_PREFIX_FIELD_INFO_CLASS 0x3 /* enum */
20575
+#define          RX_PREFIX_FIELD_INFO_PARTIAL_TSTAMP 0x4 /* enum */
20576
+#define          RX_PREFIX_FIELD_INFO_RSS_HASH 0x5 /* enum */
20577
+#define          RX_PREFIX_FIELD_INFO_USER_MARK 0x6 /* enum */
20578
+#define          RX_PREFIX_FIELD_INFO_INGRESS_VPORT 0x7 /* enum */
20579
+#define          RX_PREFIX_FIELD_INFO_CSUM_FRAME 0x8 /* enum */
20580
+#define          RX_PREFIX_FIELD_INFO_VLAN_STRIP_TCI 0x9 /* enum */
20581
+#define       RX_PREFIX_FIELD_INFO_TYPE_LBN 24
20582
+#define       RX_PREFIX_FIELD_INFO_TYPE_WIDTH 8
20583
+
20584
+/* RX_PREFIX_FIXED_RESPONSE structuredef: Information about an RX prefix in
20585
+ * which every field has a fixed offset and width
20586
+ */
20587
+#define    RX_PREFIX_FIXED_RESPONSE_LENMIN 4
20588
+#define    RX_PREFIX_FIXED_RESPONSE_LENMAX 252
20589
+#define    RX_PREFIX_FIXED_RESPONSE_LENMAX_MCDI2 1020
20590
+#define    RX_PREFIX_FIXED_RESPONSE_LEN(num) (4+4*(num))
20591
+#define    RX_PREFIX_FIXED_RESPONSE_FIELDS_NUM(len) (((len)-4)/4)
20592
+/* Length of the RX prefix in bytes */
20593
+#define       RX_PREFIX_FIXED_RESPONSE_PREFIX_LENGTH_BYTES_OFST 0
20594
+#define       RX_PREFIX_FIXED_RESPONSE_PREFIX_LENGTH_BYTES_LEN 1
20595
+#define       RX_PREFIX_FIXED_RESPONSE_PREFIX_LENGTH_BYTES_LBN 0
20596
+#define       RX_PREFIX_FIXED_RESPONSE_PREFIX_LENGTH_BYTES_WIDTH 8
20597
+/* Number of fields present in the prefix */
20598
+#define       RX_PREFIX_FIXED_RESPONSE_FIELD_COUNT_OFST 1
20599
+#define       RX_PREFIX_FIXED_RESPONSE_FIELD_COUNT_LEN 1
20600
+#define       RX_PREFIX_FIXED_RESPONSE_FIELD_COUNT_LBN 8
20601
+#define       RX_PREFIX_FIXED_RESPONSE_FIELD_COUNT_WIDTH 8
20602
+#define       RX_PREFIX_FIXED_RESPONSE_RESERVED_OFST 2
20603
+#define       RX_PREFIX_FIXED_RESPONSE_RESERVED_LEN 2
20604
+#define       RX_PREFIX_FIXED_RESPONSE_RESERVED_LBN 16
20605
+#define       RX_PREFIX_FIXED_RESPONSE_RESERVED_WIDTH 16
20606
+/* Array of RX_PREFIX_FIELD_INFO structures, of length FIELD_COUNT */
20607
+#define       RX_PREFIX_FIXED_RESPONSE_FIELDS_OFST 4
20608
+#define       RX_PREFIX_FIXED_RESPONSE_FIELDS_LEN 4
20609
+#define       RX_PREFIX_FIXED_RESPONSE_FIELDS_MINNUM 0
20610
+#define       RX_PREFIX_FIXED_RESPONSE_FIELDS_MAXNUM 62
20611
+#define       RX_PREFIX_FIXED_RESPONSE_FIELDS_MAXNUM_MCDI2 254
20612
+#define       RX_PREFIX_FIXED_RESPONSE_FIELDS_LBN 32
20613
+#define       RX_PREFIX_FIXED_RESPONSE_FIELDS_WIDTH 32
20614
+
20615
+
20616
+/***********************************/
20617
+/* MC_CMD_QUERY_RX_PREFIX_ID
20618
+ * This command takes an RX prefix id (obtained from MC_CMD_GET_RX_PREFIX_ID)
20619
+ * and returns a description of the RX prefix of packets delievered to an RXQ
20620
+ * created with that prefix id
20621
+ */
20622
+#define MC_CMD_QUERY_RX_PREFIX_ID 0x13c
20623
+#undef MC_CMD_0x13c_PRIVILEGE_CTG
20624
+
20625
+#define MC_CMD_0x13c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
20626
+
20627
+/* MC_CMD_QUERY_RX_PREFIX_ID_IN msgrequest */
20628
+#define    MC_CMD_QUERY_RX_PREFIX_ID_IN_LEN 4
20629
+/* Prefix id to query */
20630
+#define       MC_CMD_QUERY_RX_PREFIX_ID_IN_RX_PREFIX_ID_OFST 0
20631
+#define       MC_CMD_QUERY_RX_PREFIX_ID_IN_RX_PREFIX_ID_LEN 4
20632
+
20633
+/* MC_CMD_QUERY_RX_PREFIX_ID_OUT msgresponse */
20634
+#define    MC_CMD_QUERY_RX_PREFIX_ID_OUT_LENMIN 4
20635
+#define    MC_CMD_QUERY_RX_PREFIX_ID_OUT_LENMAX 252
20636
+#define    MC_CMD_QUERY_RX_PREFIX_ID_OUT_LENMAX_MCDI2 1020
20637
+#define    MC_CMD_QUERY_RX_PREFIX_ID_OUT_LEN(num) (4+1*(num))
20638
+#define    MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_NUM(len) (((len)-4)/1)
20639
+/* An enum describing the structure of this response. */
20640
+#define       MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_TYPE_OFST 0
20641
+#define       MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_TYPE_LEN 1
20642
+/* enum: The response is of format RX_PREFIX_FIXED_RESPONSE */
20643
+#define          MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_TYPE_FIXED 0x0
20644
+#define       MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESERVED_OFST 1
20645
+#define       MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESERVED_LEN 3
20646
+/* The response. Its format is as defined by the RESPONSE_TYPE value */
20647
+#define       MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_OFST 4
20648
+#define       MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_LEN 1
20649
+#define       MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_MINNUM 0
20650
+#define       MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_MAXNUM 248
20651
+#define       MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_MAXNUM_MCDI2 1016
20652
+
20653
+
20654
+/***********************************/
20655
+/* MC_CMD_BUNDLE
20656
+ * A command to perform various bundle-related operations on insecure cards.
20657
+ */
20658
+#define MC_CMD_BUNDLE 0x13d
20659
+#undef MC_CMD_0x13d_PRIVILEGE_CTG
20660
+
20661
+#define MC_CMD_0x13d_PRIVILEGE_CTG SRIOV_CTG_INSECURE
20662
+
20663
+/* MC_CMD_BUNDLE_IN msgrequest */
20664
+#define    MC_CMD_BUNDLE_IN_LEN 4
20665
+/* Sub-command code */
20666
+#define       MC_CMD_BUNDLE_IN_OP_OFST 0
20667
+#define       MC_CMD_BUNDLE_IN_OP_LEN 4
20668
+/* enum: Get the current host access mode set on component partitions. */
20669
+#define          MC_CMD_BUNDLE_IN_OP_COMPONENT_ACCESS_GET 0x0
20670
+/* enum: Set the host access mode set on component partitions. */
20671
+#define          MC_CMD_BUNDLE_IN_OP_COMPONENT_ACCESS_SET 0x1
20672
+
20673
+/* MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_IN msgrequest: Retrieve the current
20674
+ * access mode on component partitions such as MC_FIRMWARE, SUC_FIRMWARE and
20675
+ * EXPANSION_UEFI. This command only works on engineering (insecure) cards. On
20676
+ * secure adapters, this command returns MC_CMD_ERR_EPERM.
20677
+ */
20678
+#define    MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_IN_LEN 4
20679
+/* Sub-command code. Must be OP_COMPONENT_ACCESS_GET. */
20680
+#define       MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_IN_OP_OFST 0
20681
+#define       MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_IN_OP_LEN 4
20682
+
20683
+/* MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT msgresponse: Returns the access
20684
+ * control mode.
20685
+ */
20686
+#define    MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT_LEN 4
20687
+/* Access mode of component partitions. */
20688
+#define       MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT_ACCESS_MODE_OFST 0
20689
+#define       MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT_ACCESS_MODE_LEN 4
20690
+/* enum: Component partitions are read-only from the host. */
20691
+#define          MC_CMD_BUNDLE_COMPONENTS_READ_ONLY 0x0
20692
+/* enum: Component partitions can read read-from written-to by the host. */
20693
+#define          MC_CMD_BUNDLE_COMPONENTS_READ_WRITE 0x1
20694
+
20695
+/* MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN msgrequest: The component
20696
+ * partitions such as MC_FIRMWARE, SUC_FIRMWARE, EXPANSION_UEFI are set as
20697
+ * read-only on firmware built with bundle support. This command marks these
20698
+ * partitions as read/writeable. The access status set by this command does not
20699
+ * persist across MC reboots. This command only works on engineering (insecure)
20700
+ * cards. On secure adapters, this command returns MC_CMD_ERR_EPERM.
20701
+ */
20702
+#define    MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_LEN 8
20703
+/* Sub-command code. Must be OP_COMPONENT_ACCESS_SET. */
20704
+#define       MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_OP_OFST 0
20705
+#define       MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_OP_LEN 4
20706
+/* Access mode of component partitions. */
20707
+#define       MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_ACCESS_MODE_OFST 4
20708
+#define       MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_ACCESS_MODE_LEN 4
20709
+/*            Enum values, see field(s): */
20710
+/*               MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT/ACCESS_MODE */
20711
+
20712
+/* MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_OUT msgresponse */
20713
+#define    MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_OUT_LEN 0
20714
+
20715
+
20716
+/***********************************/
20717
+/* MC_CMD_GET_VPD
20718
+ * Read all VPD starting from a given address
20719
+ */
20720
+#define MC_CMD_GET_VPD 0x165
20721
+#undef MC_CMD_0x165_PRIVILEGE_CTG
20722
+
20723
+#define MC_CMD_0x165_PRIVILEGE_CTG SRIOV_CTG_GENERAL
20724
+
20725
+/* MC_CMD_GET_VPD_IN msgresponse */
20726
+#define    MC_CMD_GET_VPD_IN_LEN 4
20727
+/* VPD address to start from. In case VPD is longer than MCDI buffer
20728
+ * (unlikely), user can make multiple calls with different starting addresses.
20729
+ */
20730
+#define       MC_CMD_GET_VPD_IN_ADDR_OFST 0
20731
+#define       MC_CMD_GET_VPD_IN_ADDR_LEN 4
20732
+
20733
+/* MC_CMD_GET_VPD_OUT msgresponse */
20734
+#define    MC_CMD_GET_VPD_OUT_LENMIN 0
20735
+#define    MC_CMD_GET_VPD_OUT_LENMAX 252
20736
+#define    MC_CMD_GET_VPD_OUT_LENMAX_MCDI2 1020
20737
+#define    MC_CMD_GET_VPD_OUT_LEN(num) (0+1*(num))
20738
+#define    MC_CMD_GET_VPD_OUT_DATA_NUM(len) (((len)-0)/1)
20739
+/* VPD data returned. */
20740
+#define       MC_CMD_GET_VPD_OUT_DATA_OFST 0
20741
+#define       MC_CMD_GET_VPD_OUT_DATA_LEN 1
20742
+#define       MC_CMD_GET_VPD_OUT_DATA_MINNUM 0
20743
+#define       MC_CMD_GET_VPD_OUT_DATA_MAXNUM 252
20744
+#define       MC_CMD_GET_VPD_OUT_DATA_MAXNUM_MCDI2 1020
20745
+
20746
+
20747
+/***********************************/
20748
+/* MC_CMD_GET_NCSI_INFO
20749
+ * Provide information about the NC-SI stack
20750
+ */
20751
+#define MC_CMD_GET_NCSI_INFO 0x167
20752
+#undef MC_CMD_0x167_PRIVILEGE_CTG
20753
+
20754
+#define MC_CMD_0x167_PRIVILEGE_CTG SRIOV_CTG_GENERAL
20755
+
20756
+/* MC_CMD_GET_NCSI_INFO_IN msgrequest */
20757
+#define    MC_CMD_GET_NCSI_INFO_IN_LEN 8
20758
+/* Operation to be performed */
20759
+#define       MC_CMD_GET_NCSI_INFO_IN_OP_OFST 0
20760
+#define       MC_CMD_GET_NCSI_INFO_IN_OP_LEN 4
20761
+/* enum: Information on the link settings. */
20762
+#define          MC_CMD_GET_NCSI_INFO_IN_OP_LINK 0x0
20763
+/* enum: Statistics associated with the channel */
20764
+#define          MC_CMD_GET_NCSI_INFO_IN_OP_STATISTICS 0x1
20765
+/* The NC-SI channel on which the operation is to be performed */
20766
+#define       MC_CMD_GET_NCSI_INFO_IN_CHANNEL_OFST 4
20767
+#define       MC_CMD_GET_NCSI_INFO_IN_CHANNEL_LEN 4
20768
+
20769
+/* MC_CMD_GET_NCSI_INFO_LINK_OUT msgresponse */
20770
+#define    MC_CMD_GET_NCSI_INFO_LINK_OUT_LEN 12
20771
+/* Settings as received from BMC. */
20772
+#define       MC_CMD_GET_NCSI_INFO_LINK_OUT_SETTINGS_OFST 0
20773
+#define       MC_CMD_GET_NCSI_INFO_LINK_OUT_SETTINGS_LEN 4
20774
+/* Advertised capabilities applied to channel. */
20775
+#define       MC_CMD_GET_NCSI_INFO_LINK_OUT_ADV_CAP_OFST 4
20776
+#define       MC_CMD_GET_NCSI_INFO_LINK_OUT_ADV_CAP_LEN 4
20777
+/* General status */
20778
+#define       MC_CMD_GET_NCSI_INFO_LINK_OUT_STATUS_OFST 8
20779
+#define       MC_CMD_GET_NCSI_INFO_LINK_OUT_STATUS_LEN 4
20780
+#define        MC_CMD_GET_NCSI_INFO_LINK_OUT_STATE_OFST 8
20781
+#define        MC_CMD_GET_NCSI_INFO_LINK_OUT_STATE_LBN 0
20782
+#define        MC_CMD_GET_NCSI_INFO_LINK_OUT_STATE_WIDTH 2
20783
+#define        MC_CMD_GET_NCSI_INFO_LINK_OUT_ENABLE_OFST 8
20784
+#define        MC_CMD_GET_NCSI_INFO_LINK_OUT_ENABLE_LBN 2
20785
+#define        MC_CMD_GET_NCSI_INFO_LINK_OUT_ENABLE_WIDTH 1
20786
+#define        MC_CMD_GET_NCSI_INFO_LINK_OUT_NETWORK_TX_OFST 8
20787
+#define        MC_CMD_GET_NCSI_INFO_LINK_OUT_NETWORK_TX_LBN 3
20788
+#define        MC_CMD_GET_NCSI_INFO_LINK_OUT_NETWORK_TX_WIDTH 1
20789
+#define        MC_CMD_GET_NCSI_INFO_LINK_OUT_ATTACHED_OFST 8
20790
+#define        MC_CMD_GET_NCSI_INFO_LINK_OUT_ATTACHED_LBN 4
20791
+#define        MC_CMD_GET_NCSI_INFO_LINK_OUT_ATTACHED_WIDTH 1
20792
+
20793
+/* MC_CMD_GET_NCSI_INFO_STATISTICS_OUT msgresponse */
20794
+#define    MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_LEN 28
20795
+/* The number of NC-SI commands received. */
20796
+#define       MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMDS_RX_OFST 0
20797
+#define       MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMDS_RX_LEN 4
20798
+/* The number of NC-SI commands dropped. */
20799
+#define       MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_PKTS_DROPPED_OFST 4
20800
+#define       MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_PKTS_DROPPED_LEN 4
20801
+/* The number of invalid NC-SI commands received. */
20802
+#define       MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMD_TYPE_ERRS_OFST 8
20803
+#define       MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMD_TYPE_ERRS_LEN 4
20804
+/* The number of checksum errors seen. */
20805
+#define       MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMD_CSUM_ERRS_OFST 12
20806
+#define       MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMD_CSUM_ERRS_LEN 4
20807
+/* The number of NC-SI requests received. */
20808
+#define       MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_RX_PKTS_OFST 16
20809
+#define       MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_RX_PKTS_LEN 4
20810
+/* The number of NC-SI responses sent (includes AENs) */
20811
+#define       MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_TX_PKTS_OFST 20
20812
+#define       MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_TX_PKTS_LEN 4
20813
+/* The number of NC-SI AENs sent */
20814
+#define       MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_AENS_SENT_OFST 24
20815
+#define       MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_AENS_SENT_LEN 4
20816
+
20817
+
20818
+/* CLOCK_INFO structuredef: Information about a single hardware clock */
20819
+#define    CLOCK_INFO_LEN 28
20820
+/* Enumeration that uniquely identifies the clock */
20821
+#define       CLOCK_INFO_CLOCK_ID_OFST 0
20822
+#define       CLOCK_INFO_CLOCK_ID_LEN 2
20823
+/* enum: The Riverhead CMC (card MC) */
20824
+#define          CLOCK_INFO_CLOCK_CMC 0x0
20825
+/* enum: The Riverhead NMC (network MC) */
20826
+#define          CLOCK_INFO_CLOCK_NMC 0x1
20827
+/* enum: The Riverhead SDNET slice main logic */
20828
+#define          CLOCK_INFO_CLOCK_SDNET 0x2
20829
+/* enum: The Riverhead SDNET LUT */
20830
+#define          CLOCK_INFO_CLOCK_SDNET_LUT 0x3
20831
+/* enum: The Riverhead SDNET control logic */
20832
+#define          CLOCK_INFO_CLOCK_SDNET_CTRL 0x4
20833
+/* enum: The Riverhead Streaming SubSystem */
20834
+#define          CLOCK_INFO_CLOCK_SSS 0x5
20835
+/* enum: The Riverhead network MAC and associated CSR registers */
20836
+#define          CLOCK_INFO_CLOCK_MAC 0x6
20837
+#define       CLOCK_INFO_CLOCK_ID_LBN 0
20838
+#define       CLOCK_INFO_CLOCK_ID_WIDTH 16
20839
+/* Assorted flags */
20840
+#define       CLOCK_INFO_FLAGS_OFST 2
20841
+#define       CLOCK_INFO_FLAGS_LEN 2
20842
+#define        CLOCK_INFO_SETTABLE_OFST 2
20843
+#define        CLOCK_INFO_SETTABLE_LBN 0
20844
+#define        CLOCK_INFO_SETTABLE_WIDTH 1
20845
+#define       CLOCK_INFO_FLAGS_LBN 16
20846
+#define       CLOCK_INFO_FLAGS_WIDTH 16
20847
+/* The frequency in HZ */
20848
+#define       CLOCK_INFO_FREQUENCY_OFST 4
20849
+#define       CLOCK_INFO_FREQUENCY_LEN 8
20850
+#define       CLOCK_INFO_FREQUENCY_LO_OFST 4
20851
+#define       CLOCK_INFO_FREQUENCY_HI_OFST 8
20852
+#define       CLOCK_INFO_FREQUENCY_LBN 32
20853
+#define       CLOCK_INFO_FREQUENCY_WIDTH 64
20854
+/* Human-readable ASCII name for clock, with NUL termination */
20855
+#define       CLOCK_INFO_NAME_OFST 12
20856
+#define       CLOCK_INFO_NAME_LEN 1
20857
+#define       CLOCK_INFO_NAME_NUM 16
20858
+#define       CLOCK_INFO_NAME_LBN 96
20859
+#define       CLOCK_INFO_NAME_WIDTH 8
20860
+
20861
+
20862
+/***********************************/
20863
+/* MC_CMD_GET_CLOCKS_INFO
20864
+ * Get information about the device clocks
20865
+ */
20866
+#define MC_CMD_GET_CLOCKS_INFO 0x166
20867
+#undef MC_CMD_0x166_PRIVILEGE_CTG
20868
+
20869
+#define MC_CMD_0x166_PRIVILEGE_CTG SRIOV_CTG_GENERAL
20870
+
20871
+/* MC_CMD_GET_CLOCKS_INFO_IN msgrequest */
20872
+#define    MC_CMD_GET_CLOCKS_INFO_IN_LEN 0
20873
+
20874
+/* MC_CMD_GET_CLOCKS_INFO_OUT msgresponse */
20875
+#define    MC_CMD_GET_CLOCKS_INFO_OUT_LENMIN 0
20876
+#define    MC_CMD_GET_CLOCKS_INFO_OUT_LENMAX 252
20877
+#define    MC_CMD_GET_CLOCKS_INFO_OUT_LENMAX_MCDI2 1008
20878
+#define    MC_CMD_GET_CLOCKS_INFO_OUT_LEN(num) (0+28*(num))
20879
+#define    MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_NUM(len) (((len)-0)/28)
20880
+/* An array of CLOCK_INFO structures. */
20881
+#define       MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_OFST 0
20882
+#define       MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_LEN 28
20883
+#define       MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_MINNUM 0
20884
+#define       MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_MAXNUM 9
20885
+#define       MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_MAXNUM_MCDI2 36
20886
+
20887
+
20888
+/***********************************/
20889
+/* MC_CMD_VNIC_ENCAP_RULE_ADD
20890
+ * Add a rule for detecting encapsulations in the VNIC stage. Currently this only affects checksum validation in VNIC RX - on TX the send descriptor explicitly specifies encapsulation. These rules are per-VNIC, i.e. only apply to the current driver. If a rule matches, then the packet is considered to have the corresponding encapsulation type, and the inner packet is parsed. It is up to the driver to ensure that overlapping rules are not inserted. (If a packet would match multiple rules, a random one of them will be used.) A rule with the exact same match criteria may not be inserted twice (EALREADY). Only a limited number MATCH_FLAGS values are supported, use MC_CMD_GET_PARSER_DISP_INFO with OP OP_GET_SUPPORTED_VNIC_ENCAP_RULE_MATCHES to get a list of supported combinations. Each driver may only have a limited set of active rules - returns ENOSPC if the caller's table is full.
20891
+ */
20892
+#define MC_CMD_VNIC_ENCAP_RULE_ADD 0x16d
20893
+#undef MC_CMD_0x16d_PRIVILEGE_CTG
20894
+
20895
+#define MC_CMD_0x16d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
20896
+
20897
+/* MC_CMD_VNIC_ENCAP_RULE_ADD_IN msgrequest */
20898
+#define    MC_CMD_VNIC_ENCAP_RULE_ADD_IN_LEN 36
20899
+/* Set to MAE_MPORT_SELECTOR_ASSIGNED. In the future this may be relaxed. */
20900
+#define       MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MPORT_SELECTOR_OFST 0
20901
+#define       MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MPORT_SELECTOR_LEN 4
20902
+/* Any non-zero bits other than the ones named below or an unsupported
20903
+ * combination will cause the NIC to return EOPNOTSUPP. In the future more
20904
+ * flags may be added.
20905
+ */
20906
+#define       MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_FLAGS_OFST 4
20907
+#define       MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_FLAGS_LEN 4
20908
+#define        MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_OFST 4
20909
+#define        MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_LBN 0
20910
+#define        MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_WIDTH 1
20911
+#define        MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_OUTER_VLAN_OFST 4
20912
+#define        MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_OUTER_VLAN_LBN 1
20913
+#define        MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_OUTER_VLAN_WIDTH 1
20914
+#define        MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_IP_OFST 4
20915
+#define        MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_IP_LBN 2
20916
+#define        MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_IP_WIDTH 1
20917
+#define        MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_IP_PROTO_OFST 4
20918
+#define        MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_IP_PROTO_LBN 3
20919
+#define        MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_IP_PROTO_WIDTH 1
20920
+#define        MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_OFST 4
20921
+#define        MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_LBN 4
20922
+#define        MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_WIDTH 1
20923
+/* Only if MATCH_ETHER_TYPE is set. Ethertype value as bytes in network order.
20924
+ * Currently only IPv4 (0x0800) and IPv6 (0x86DD) ethertypes may be used.
20925
+ */
20926
+#define       MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ETHER_TYPE_OFST 8
20927
+#define       MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ETHER_TYPE_LEN 2
20928
+/* Only if MATCH_OUTER_VLAN is set. VID value as bytes in network order.
20929
+ * (Deprecated)
20930
+ */
20931
+#define       MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_LBN 80
20932
+#define       MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_WIDTH 12
20933
+/* Only if MATCH_OUTER_VLAN is set. Aligned wrapper for OUTER_VLAN_VID. */
20934
+#define       MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_WORD_OFST 10
20935
+#define       MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_WORD_LEN 2
20936
+#define        MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_VID_OFST 10
20937
+#define        MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_VID_LBN 0
20938
+#define        MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_VID_WIDTH 12
20939
+/* Only if MATCH_DST_IP is set. IP address as bytes in network order. In the
20940
+ * case of IPv4, the IP should be in the first 4 bytes and all other bytes
20941
+ * should be zero.
20942
+ */
20943
+#define       MC_CMD_VNIC_ENCAP_RULE_ADD_IN_DST_IP_OFST 12
20944
+#define       MC_CMD_VNIC_ENCAP_RULE_ADD_IN_DST_IP_LEN 16
20945
+/* Only if MATCH_IP_PROTO is set. Currently only UDP proto (17) may be used. */
20946
+#define       MC_CMD_VNIC_ENCAP_RULE_ADD_IN_IP_PROTO_OFST 28
20947
+#define       MC_CMD_VNIC_ENCAP_RULE_ADD_IN_IP_PROTO_LEN 1
20948
+/* Actions that should be applied to packets match the rule. */
20949
+#define       MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ACTION_FLAGS_OFST 29
20950
+#define       MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ACTION_FLAGS_LEN 1
20951
+#define        MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STRIP_OUTER_VLAN_OFST 29
20952
+#define        MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STRIP_OUTER_VLAN_LBN 0
20953
+#define        MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STRIP_OUTER_VLAN_WIDTH 1
20954
+/* Only if MATCH_DST_PORT is set. Port number as bytes in network order. */
20955
+#define       MC_CMD_VNIC_ENCAP_RULE_ADD_IN_DST_PORT_OFST 30
20956
+#define       MC_CMD_VNIC_ENCAP_RULE_ADD_IN_DST_PORT_LEN 2
20957
+/* Resulting encapsulation type, as per MAE_MCDI_ENCAP_TYPE enumeration. */
20958
+#define       MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ENCAP_TYPE_OFST 32
20959
+#define       MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ENCAP_TYPE_LEN 4
20960
+
20961
+/* MC_CMD_VNIC_ENCAP_RULE_ADD_OUT msgresponse */
20962
+#define    MC_CMD_VNIC_ENCAP_RULE_ADD_OUT_LEN 4
20963
+/* Handle to inserted rule. Used for removing the rule. */
20964
+#define       MC_CMD_VNIC_ENCAP_RULE_ADD_OUT_HANDLE_OFST 0
20965
+#define       MC_CMD_VNIC_ENCAP_RULE_ADD_OUT_HANDLE_LEN 4
20966
+
20967
+
20968
+/***********************************/
20969
+/* MC_CMD_VNIC_ENCAP_RULE_REMOVE
20970
+ * Remove a VNIC encapsulation rule. Packets which would have previously matched the rule will then be considered as unencapsulated. Returns EALREADY if the input HANDLE doesn't correspond to an existing rule.
20971
+ */
20972
+#define MC_CMD_VNIC_ENCAP_RULE_REMOVE 0x16e
20973
+#undef MC_CMD_0x16e_PRIVILEGE_CTG
20974
+
20975
+#define MC_CMD_0x16e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
20976
+
20977
+/* MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN msgrequest */
20978
+#define    MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_LEN 4
20979
+/* Handle which was returned by MC_CMD_VNIC_ENCAP_RULE_ADD. */
20980
+#define       MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_HANDLE_OFST 0
20981
+#define       MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_HANDLE_LEN 4
20982
+
20983
+/* MC_CMD_VNIC_ENCAP_RULE_REMOVE_OUT msgresponse */
20984
+#define    MC_CMD_VNIC_ENCAP_RULE_REMOVE_OUT_LEN 0
20985
+
20986
+/* FUNCTION_PERSONALITY structuredef: The meanings of the personalities are
20987
+ * defined in SF-120734-TC with more information in SF-122717-TC.
20988
+ */
20989
+#define    FUNCTION_PERSONALITY_LEN 4
20990
+#define       FUNCTION_PERSONALITY_ID_OFST 0
20991
+#define       FUNCTION_PERSONALITY_ID_LEN 4
20992
+/* enum: Function has no assigned personality */
20993
+#define          FUNCTION_PERSONALITY_NULL 0x0
20994
+/* enum: Function has an EF100-style function control window and VI windows
20995
+ * with both EF100 and vDPA doorbells.
20996
+ */
20997
+#define          FUNCTION_PERSONALITY_EF100 0x1
20998
+/* enum: Function has virtio net device configuration registers and doorbells
20999
+ * for virtio queue pairs.
21000
+ */
21001
+#define          FUNCTION_PERSONALITY_VIRTIO_NET 0x2
21002
+/* enum: Function has virtio block device configuration registers and a
21003
+ * doorbell for a single virtqueue.
21004
+ */
21005
+#define          FUNCTION_PERSONALITY_VIRTIO_BLK 0x3
21006
+/* enum: Function is a Xilinx acceleration device - management function */
21007
+#define          FUNCTION_PERSONALITY_ACCEL_MGMT 0x4
21008
+/* enum: Function is a Xilinx acceleration device - user function */
21009
+#define          FUNCTION_PERSONALITY_ACCEL_USR 0x5
21010
+#define       FUNCTION_PERSONALITY_ID_LBN 0
21011
+#define       FUNCTION_PERSONALITY_ID_WIDTH 32
21012
+
21013
+
21014
+/***********************************/
21015
+/* MC_CMD_VIRTIO_GET_FEATURES
21016
+ * Get a list of the virtio features supported by the device.
21017
+ */
21018
+#define MC_CMD_VIRTIO_GET_FEATURES 0x168
21019
+#undef MC_CMD_0x168_PRIVILEGE_CTG
21020
+
21021
+#define MC_CMD_0x168_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21022
+
21023
+/* MC_CMD_VIRTIO_GET_FEATURES_IN msgrequest */
21024
+#define    MC_CMD_VIRTIO_GET_FEATURES_IN_LEN 4
21025
+/* Type of device to get features for. Matches the device id as defined by the
21026
+ * virtio spec.
21027
+ */
21028
+#define       MC_CMD_VIRTIO_GET_FEATURES_IN_DEVICE_ID_OFST 0
21029
+#define       MC_CMD_VIRTIO_GET_FEATURES_IN_DEVICE_ID_LEN 4
21030
+/* enum: Reserved. Do not use. */
21031
+#define          MC_CMD_VIRTIO_GET_FEATURES_IN_RESERVED 0x0
21032
+/* enum: Net device. */
21033
+#define          MC_CMD_VIRTIO_GET_FEATURES_IN_NET 0x1
21034
+/* enum: Block device. */
21035
+#define          MC_CMD_VIRTIO_GET_FEATURES_IN_BLOCK 0x2
21036
+
21037
+/* MC_CMD_VIRTIO_GET_FEATURES_OUT msgresponse */
21038
+#define    MC_CMD_VIRTIO_GET_FEATURES_OUT_LEN 8
21039
+/* Features supported by the device. The result is a bitfield in the format of
21040
+ * the feature bits of the specified device type as defined in the virtIO 1.1
21041
+ * specification ( https://docs.oasis-
21042
+ * open.org/virtio/virtio/v1.1/csprd01/virtio-v1.1-csprd01.pdf )
21043
+ */
21044
+#define       MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_OFST 0
21045
+#define       MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LEN 8
21046
+#define       MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_OFST 0
21047
+#define       MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_OFST 4
21048
+
21049
+
21050
+/***********************************/
21051
+/* MC_CMD_VIRTIO_TEST_FEATURES
21052
+ * Query whether a given set of features is supported. Fails with ENOSUP if the
21053
+ * driver requests a feature the device doesn't support. Fails with EINVAL if
21054
+ * the driver fails to request a feature which the device requires.
21055
+ */
21056
+#define MC_CMD_VIRTIO_TEST_FEATURES 0x169
21057
+#undef MC_CMD_0x169_PRIVILEGE_CTG
21058
+
21059
+#define MC_CMD_0x169_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21060
+
21061
+/* MC_CMD_VIRTIO_TEST_FEATURES_IN msgrequest */
21062
+#define    MC_CMD_VIRTIO_TEST_FEATURES_IN_LEN 16
21063
+/* Type of device to test features for. Matches the device id as defined by the
21064
+ * virtio spec.
21065
+ */
21066
+#define       MC_CMD_VIRTIO_TEST_FEATURES_IN_DEVICE_ID_OFST 0
21067
+#define       MC_CMD_VIRTIO_TEST_FEATURES_IN_DEVICE_ID_LEN 4
21068
+/*            Enum values, see field(s): */
21069
+/*               MC_CMD_VIRTIO_GET_FEATURES/MC_CMD_VIRTIO_GET_FEATURES_IN/DEVICE_ID */
21070
+#define       MC_CMD_VIRTIO_TEST_FEATURES_IN_RESERVED_OFST 4
21071
+#define       MC_CMD_VIRTIO_TEST_FEATURES_IN_RESERVED_LEN 4
21072
+/* Features requested. Same format as the returned value from
21073
+ * MC_CMD_VIRTIO_GET_FEATURES.
21074
+ */
21075
+#define       MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_OFST 8
21076
+#define       MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LEN 8
21077
+#define       MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_OFST 8
21078
+#define       MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_OFST 12
21079
+
21080
+/* MC_CMD_VIRTIO_TEST_FEATURES_OUT msgresponse */
21081
+#define    MC_CMD_VIRTIO_TEST_FEATURES_OUT_LEN 0
21082
+
21083
+
21084
+/***********************************/
21085
+/* MC_CMD_VIRTIO_INIT_QUEUE
21086
+ * Create a virtio virtqueue. Fails with EALREADY if the queue already exists.
21087
+ * Fails with ENOSUP if a feature is requested that isn't supported. Fails with
21088
+ * EINVAL if a required feature isn't requested, or any other parameter is
21089
+ * invalid.
21090
+ */
21091
+#define MC_CMD_VIRTIO_INIT_QUEUE 0x16a
21092
+#undef MC_CMD_0x16a_PRIVILEGE_CTG
21093
+
21094
+#define MC_CMD_0x16a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21095
+
21096
+/* MC_CMD_VIRTIO_INIT_QUEUE_REQ msgrequest */
21097
+#define    MC_CMD_VIRTIO_INIT_QUEUE_REQ_LEN 68
21098
+/* Type of virtqueue to create. A network rxq and a txq can exist at the same
21099
+ * time on a single VI.
21100
+ */
21101
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_QUEUE_TYPE_OFST 0
21102
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_QUEUE_TYPE_LEN 1
21103
+/* enum: A network device receive queue */
21104
+#define          MC_CMD_VIRTIO_INIT_QUEUE_REQ_NET_RXQ 0x0
21105
+/* enum: A network device transmit queue */
21106
+#define          MC_CMD_VIRTIO_INIT_QUEUE_REQ_NET_TXQ 0x1
21107
+/* enum: A block device request queue */
21108
+#define          MC_CMD_VIRTIO_INIT_QUEUE_REQ_BLOCK 0x2
21109
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_RESERVED_OFST 1
21110
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_RESERVED_LEN 1
21111
+/* If the calling function is a PF and this field is not VF_NULL, create the
21112
+ * queue on the specified child VF instead of on the PF.
21113
+ */
21114
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_TARGET_VF_OFST 2
21115
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_TARGET_VF_LEN 2
21116
+/* enum: No VF, create queue on the PF. */
21117
+#define          MC_CMD_VIRTIO_INIT_QUEUE_REQ_VF_NULL 0xffff
21118
+/* Desired instance. This is the function-local index of the associated VI, not
21119
+ * the virtqueue number as counted by the virtqueue spec.
21120
+ */
21121
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_INSTANCE_OFST 4
21122
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_INSTANCE_LEN 4
21123
+/* Queue size, in entries. Must be a power of two. */
21124
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_SIZE_OFST 8
21125
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_SIZE_LEN 4
21126
+/* Flags */
21127
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_FLAGS_OFST 12
21128
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_FLAGS_LEN 4
21129
+#define        MC_CMD_VIRTIO_INIT_QUEUE_REQ_USE_PASID_OFST 12
21130
+#define        MC_CMD_VIRTIO_INIT_QUEUE_REQ_USE_PASID_LBN 0
21131
+#define        MC_CMD_VIRTIO_INIT_QUEUE_REQ_USE_PASID_WIDTH 1
21132
+/* Address of the descriptor table in the virtqueue. */
21133
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_OFST 16
21134
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LEN 8
21135
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_OFST 16
21136
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_OFST 20
21137
+/* Address of the available ring in the virtqueue. */
21138
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_OFST 24
21139
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LEN 8
21140
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_OFST 24
21141
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_OFST 28
21142
+/* Address of the used ring in the virtqueue. */
21143
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_OFST 32
21144
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LEN 8
21145
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_OFST 32
21146
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_OFST 36
21147
+/* PASID to use on PCIe transactions involving this queue. Ignored if the
21148
+ * USE_PASID flag is not set.
21149
+ */
21150
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_PASID_OFST 40
21151
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_PASID_LEN 4
21152
+/* Which MSIX vector to use for this virtqueue, or NO_VECTOR if MSIX should not
21153
+ * be used.
21154
+ */
21155
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_MSIX_VECTOR_OFST 44
21156
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_MSIX_VECTOR_LEN 2
21157
+/* enum: Do not enable interrupts for this virtqueue */
21158
+#define          MC_CMD_VIRTIO_INIT_QUEUE_REQ_NO_VECTOR 0xffff
21159
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_RESERVED2_OFST 46
21160
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_RESERVED2_LEN 2
21161
+/* Virtio features to apply to this queue. Same format as the in the virtio
21162
+ * spec and in the return from MC_CMD_VIRTIO_GET_FEATURES. Must be a subset of
21163
+ * the features returned from MC_CMD_VIRTIO_GET_FEATURES. Features are per-
21164
+ * queue because with vDPA multiple queues on the same function can be passed
21165
+ * through to different virtual hosts as independent devices.
21166
+ */
21167
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_OFST 48
21168
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LEN 8
21169
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_OFST 48
21170
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_OFST 52
21171
+/*            Enum values, see field(s): */
21172
+/*               MC_CMD_VIRTIO_GET_FEATURES/MC_CMD_VIRTIO_GET_FEATURES_OUT/FEATURES */
21173
+/* The inital producer index for this queue's used ring. If this queue is being
21174
+ * created to be migrated into, this should be the FINAL_PIDX value returned by
21175
+ * MC_CMD_VIRTIO_FINI_QUEUE of the queue being migrated from. Otherwise, it
21176
+ * should be zero.
21177
+ */
21178
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_PIDX_OFST 56
21179
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_PIDX_LEN 4
21180
+/* The inital consumer index for this queue's available ring. If this queue is
21181
+ * being created to be migrated into, this should be the FINAL_CIDX value
21182
+ * returned by MC_CMD_VIRTIO_FINI_QUEUE of the queue being migrated from.
21183
+ * Otherwise, it should be zero.
21184
+ */
21185
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_CIDX_OFST 60
21186
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_CIDX_LEN 4
21187
+/* A MAE_MPORT_SELECTOR defining which mport this queue should be associated
21188
+ * with. Use MAE_MPORT_SELECTOR_ASSIGNED to request the default mport for the
21189
+ * function this queue is being created on.
21190
+ */
21191
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_MPORT_SELECTOR_OFST 64
21192
+#define       MC_CMD_VIRTIO_INIT_QUEUE_REQ_MPORT_SELECTOR_LEN 4
21193
+
21194
+/* MC_CMD_VIRTIO_INIT_QUEUE_RESP msgresponse */
21195
+#define    MC_CMD_VIRTIO_INIT_QUEUE_RESP_LEN 0
21196
+
21197
+
21198
+/***********************************/
21199
+/* MC_CMD_VIRTIO_FINI_QUEUE
21200
+ * Destroy a virtio virtqueue
21201
+ */
21202
+#define MC_CMD_VIRTIO_FINI_QUEUE 0x16b
21203
+#undef MC_CMD_0x16b_PRIVILEGE_CTG
21204
+
21205
+#define MC_CMD_0x16b_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21206
+
21207
+/* MC_CMD_VIRTIO_FINI_QUEUE_REQ msgrequest */
21208
+#define    MC_CMD_VIRTIO_FINI_QUEUE_REQ_LEN 8
21209
+/* Type of virtqueue to destroy. */
21210
+#define       MC_CMD_VIRTIO_FINI_QUEUE_REQ_QUEUE_TYPE_OFST 0
21211
+#define       MC_CMD_VIRTIO_FINI_QUEUE_REQ_QUEUE_TYPE_LEN 1
21212
+/*            Enum values, see field(s): */
21213
+/*               MC_CMD_VIRTIO_INIT_QUEUE/MC_CMD_VIRTIO_INIT_QUEUE_REQ/QUEUE_TYPE */
21214
+#define       MC_CMD_VIRTIO_FINI_QUEUE_REQ_RESERVED_OFST 1
21215
+#define       MC_CMD_VIRTIO_FINI_QUEUE_REQ_RESERVED_LEN 1
21216
+/* If the calling function is a PF and this field is not VF_NULL, destroy the
21217
+ * queue on the specified child VF instead of on the PF.
21218
+ */
21219
+#define       MC_CMD_VIRTIO_FINI_QUEUE_REQ_TARGET_VF_OFST 2
21220
+#define       MC_CMD_VIRTIO_FINI_QUEUE_REQ_TARGET_VF_LEN 2
21221
+/* enum: No VF, destroy the queue on the PF. */
21222
+#define          MC_CMD_VIRTIO_FINI_QUEUE_REQ_VF_NULL 0xffff
21223
+/* Instance to destroy */
21224
+#define       MC_CMD_VIRTIO_FINI_QUEUE_REQ_INSTANCE_OFST 4
21225
+#define       MC_CMD_VIRTIO_FINI_QUEUE_REQ_INSTANCE_LEN 4
21226
+
21227
+/* MC_CMD_VIRTIO_FINI_QUEUE_RESP msgresponse */
21228
+#define    MC_CMD_VIRTIO_FINI_QUEUE_RESP_LEN 8
21229
+/* The producer index of the used ring when the queue was stopped. */
21230
+#define       MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_PIDX_OFST 0
21231
+#define       MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_PIDX_LEN 4
21232
+/* The consumer index of the available ring when the queue was stopped. */
21233
+#define       MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_CIDX_OFST 4
21234
+#define       MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_CIDX_LEN 4
21235
+
21236
+
21237
+/***********************************/
21238
+/* MC_CMD_VIRTIO_GET_DOORBELL_OFFSET
21239
+ * Get the offset in the BAR of the doorbells for a VI. Doesn't require the
21240
+ * queue(s) to be allocated.
21241
+ */
21242
+#define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET 0x16c
21243
+#undef MC_CMD_0x16c_PRIVILEGE_CTG
21244
+
21245
+#define MC_CMD_0x16c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21246
+
21247
+/* MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ msgrequest */
21248
+#define    MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_LEN 8
21249
+/* Type of device to get information for. Matches the device id as defined by
21250
+ * the virtio spec.
21251
+ */
21252
+#define       MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_DEVICE_ID_OFST 0
21253
+#define       MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_DEVICE_ID_LEN 1
21254
+/*            Enum values, see field(s): */
21255
+/*               MC_CMD_VIRTIO_GET_FEATURES/MC_CMD_VIRTIO_GET_FEATURES_IN/DEVICE_ID */
21256
+#define       MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_RESERVED_OFST 1
21257
+#define       MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_RESERVED_LEN 1
21258
+/* If the calling function is a PF and this field is not VF_NULL, query the VI
21259
+ * on the specified child VF instead of on the PF.
21260
+ */
21261
+#define       MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_TARGET_VF_OFST 2
21262
+#define       MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_TARGET_VF_LEN 2
21263
+/* enum: No VF, query the PF. */
21264
+#define          MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_VF_NULL 0xffff
21265
+/* VI instance to query */
21266
+#define       MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_INSTANCE_OFST 4
21267
+#define       MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_INSTANCE_LEN 4
21268
+
21269
+/* MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP msgresponse */
21270
+#define    MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_LEN 8
21271
+/* Offset of RX doorbell in BAR */
21272
+#define       MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_RX_DBL_OFFSET_OFST 0
21273
+#define       MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_RX_DBL_OFFSET_LEN 4
21274
+/* Offset of TX doorbell in BAR */
21275
+#define       MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_TX_DBL_OFFSET_OFST 4
21276
+#define       MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_TX_DBL_OFFSET_LEN 4
21277
+
21278
+/* MC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP msgresponse */
21279
+#define    MC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP_LEN 4
21280
+/* Offset of request doorbell in BAR */
21281
+#define       MC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP_DBL_OFFSET_OFST 0
21282
+#define       MC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP_DBL_OFFSET_LEN 4
21283
+
21284
+/* PCIE_FUNCTION structuredef: Structure representing a PCIe function ID
21285
+ * (interface/PF/VF tuple)
21286
+ */
21287
+#define    PCIE_FUNCTION_LEN 8
21288
+/* PCIe PF function number */
21289
+#define       PCIE_FUNCTION_PF_OFST 0
21290
+#define       PCIE_FUNCTION_PF_LEN 2
21291
+/* enum: Wildcard value representing any available function (e.g in resource
21292
+ * allocation requests)
21293
+ */
21294
+#define          PCIE_FUNCTION_PF_ANY 0xfffe
21295
+/* enum: Value representing invalid (null) function */
21296
+#define          PCIE_FUNCTION_PF_NULL 0xffff
21297
+#define       PCIE_FUNCTION_PF_LBN 0
21298
+#define       PCIE_FUNCTION_PF_WIDTH 16
21299
+/* PCIe VF Function number (PF relative) */
21300
+#define       PCIE_FUNCTION_VF_OFST 2
21301
+#define       PCIE_FUNCTION_VF_LEN 2
21302
+/* enum: Wildcard value representing any available function (e.g in resource
21303
+ * allocation requests)
21304
+ */
21305
+#define          PCIE_FUNCTION_VF_ANY 0xfffe
21306
+/* enum: Function is a PF (when PF != PF_NULL) or invalid function (when PF ==
21307
+ * PF_NULL)
21308
+ */
21309
+#define          PCIE_FUNCTION_VF_NULL 0xffff
21310
+#define       PCIE_FUNCTION_VF_LBN 16
21311
+#define       PCIE_FUNCTION_VF_WIDTH 16
21312
+/* PCIe interface of the function */
21313
+#define       PCIE_FUNCTION_INTF_OFST 4
21314
+#define       PCIE_FUNCTION_INTF_LEN 4
21315
+/* enum: Host PCIe interface */
21316
+#define          PCIE_FUNCTION_INTF_HOST 0x0
21317
+/* enum: Application Processor interface */
21318
+#define          PCIE_FUNCTION_INTF_AP 0x1
21319
+#define       PCIE_FUNCTION_INTF_LBN 32
21320
+#define       PCIE_FUNCTION_INTF_WIDTH 32
21321
+
21322
+
21323
+/***********************************/
21324
+/* MC_CMD_DESC_PROXY_FUNC_CREATE
21325
+ * Descriptor proxy functions are abstract devices that forward all request
21326
+ * submitted to the host PCIe function (descriptors submitted to Virtio or
21327
+ * EF100 queues) to be handled on another function (most commonly on the
21328
+ * embedded Application Processor), via EF100 descriptor proxy, memory-to-
21329
+ * memory and descriptor-to-completion mechanisms. Primary user is Virtio-blk
21330
+ * subsystem, see SF-122927-TC. This function allocates a new descriptor proxy
21331
+ * function on the host and assigns a user-defined label. The actual function
21332
+ * configuration is not persisted until the caller configures it with
21333
+ * MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN and commits with
21334
+ * MC_CMD_DESC_PROXY_FUNC_COMMIT_IN.
21335
+ */
21336
+#define MC_CMD_DESC_PROXY_FUNC_CREATE 0x172
21337
+#undef MC_CMD_0x172_PRIVILEGE_CTG
21338
+
21339
+#define MC_CMD_0x172_PRIVILEGE_CTG SRIOV_CTG_ADMIN
21340
+
21341
+/* MC_CMD_DESC_PROXY_FUNC_CREATE_IN msgrequest */
21342
+#define    MC_CMD_DESC_PROXY_FUNC_CREATE_IN_LEN 52
21343
+/* PCIe Function ID to allocate (as struct PCIE_FUNCTION). Set to
21344
+ * {PF_ANY,VF_ANY,interface} for "any available function" Set to
21345
+ * {PF_ANY,VF_NULL,interface} for "any available PF"
21346
+ */
21347
+#define       MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_OFST 0
21348
+#define       MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LEN 8
21349
+#define       MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_OFST 0
21350
+#define       MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_OFST 4
21351
+/* The personality to set. The meanings of the personalities are defined in
21352
+ * SF-120734-TC with more information in SF-122717-TC. At present, we only
21353
+ * support proxying for VIRTIO_BLK
21354
+ */
21355
+#define       MC_CMD_DESC_PROXY_FUNC_CREATE_IN_PERSONALITY_OFST 8
21356
+#define       MC_CMD_DESC_PROXY_FUNC_CREATE_IN_PERSONALITY_LEN 4
21357
+/*            Enum values, see field(s): */
21358
+/*               FUNCTION_PERSONALITY/ID */
21359
+/* User-defined label (zero-terminated ASCII string) to uniquely identify the
21360
+ * function
21361
+ */
21362
+#define       MC_CMD_DESC_PROXY_FUNC_CREATE_IN_LABEL_OFST 12
21363
+#define       MC_CMD_DESC_PROXY_FUNC_CREATE_IN_LABEL_LEN 40
21364
+
21365
+/* MC_CMD_DESC_PROXY_FUNC_CREATE_OUT msgresponse */
21366
+#define    MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_LEN 12
21367
+/* Handle to the descriptor proxy function */
21368
+#define       MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_HANDLE_OFST 0
21369
+#define       MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_HANDLE_LEN 4
21370
+/* Allocated function ID (as struct PCIE_FUNCTION) */
21371
+#define       MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_OFST 4
21372
+#define       MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LEN 8
21373
+#define       MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_OFST 4
21374
+#define       MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_HI_OFST 8
21375
+
21376
+
21377
+/***********************************/
21378
+/* MC_CMD_DESC_PROXY_FUNC_DESTROY
21379
+ * Remove an existing descriptor proxy function. Underlying function
21380
+ * personality and configuration reverts back to factory default. Function
21381
+ * configuration is committed immediately to specified store and any function
21382
+ * ownership is released.
21383
+ */
21384
+#define MC_CMD_DESC_PROXY_FUNC_DESTROY 0x173
21385
+#undef MC_CMD_0x173_PRIVILEGE_CTG
21386
+
21387
+#define MC_CMD_0x173_PRIVILEGE_CTG SRIOV_CTG_ADMIN
21388
+
21389
+/* MC_CMD_DESC_PROXY_FUNC_DESTROY_IN msgrequest */
21390
+#define    MC_CMD_DESC_PROXY_FUNC_DESTROY_IN_LEN 44
21391
+/* User-defined label (zero-terminated ASCII string) to uniquely identify the
21392
+ * function
21393
+ */
21394
+#define       MC_CMD_DESC_PROXY_FUNC_DESTROY_IN_LABEL_OFST 0
21395
+#define       MC_CMD_DESC_PROXY_FUNC_DESTROY_IN_LABEL_LEN 40
21396
+/* Store from which to remove function configuration */
21397
+#define       MC_CMD_DESC_PROXY_FUNC_DESTROY_IN_STORE_OFST 40
21398
+#define       MC_CMD_DESC_PROXY_FUNC_DESTROY_IN_STORE_LEN 4
21399
+/*            Enum values, see field(s): */
21400
+/*               MC_CMD_DESC_PROXY_FUNC_COMMIT/MC_CMD_DESC_PROXY_FUNC_COMMIT_IN/STORE */
21401
+
21402
+/* MC_CMD_DESC_PROXY_FUNC_DESTROY_OUT msgresponse */
21403
+#define    MC_CMD_DESC_PROXY_FUNC_DESTROY_OUT_LEN 0
21404
+
21405
+/* VIRTIO_BLK_CONFIG structuredef: Virtio block device configuration. See
21406
+ * Virtio specification v1.1, Sections 5.2.3 and 6 for definition of feature
21407
+ * bits. See Virtio specification v1.1, Section 5.2.4 (struct
21408
+ * virtio_blk_config) for definition of remaining configuration fields
21409
+ */
21410
+#define    VIRTIO_BLK_CONFIG_LEN 68
21411
+/* Virtio block device features to advertise, per Virtio 1.1, 5.2.3 and 6 */
21412
+#define       VIRTIO_BLK_CONFIG_FEATURES_OFST 0
21413
+#define       VIRTIO_BLK_CONFIG_FEATURES_LEN 8
21414
+#define       VIRTIO_BLK_CONFIG_FEATURES_LO_OFST 0
21415
+#define       VIRTIO_BLK_CONFIG_FEATURES_HI_OFST 4
21416
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_OFST 0
21417
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_LBN 0
21418
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_WIDTH 1
21419
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SIZE_MAX_OFST 0
21420
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SIZE_MAX_LBN 1
21421
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SIZE_MAX_WIDTH 1
21422
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SEG_MAX_OFST 0
21423
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SEG_MAX_LBN 2
21424
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SEG_MAX_WIDTH 1
21425
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_GEOMETRY_OFST 0
21426
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_GEOMETRY_LBN 4
21427
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_GEOMETRY_WIDTH 1
21428
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_RO_OFST 0
21429
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_RO_LBN 5
21430
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_RO_WIDTH 1
21431
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BLK_SIZE_OFST 0
21432
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BLK_SIZE_LBN 6
21433
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BLK_SIZE_WIDTH 1
21434
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SCSI_OFST 0
21435
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SCSI_LBN 7
21436
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SCSI_WIDTH 1
21437
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_FLUSH_OFST 0
21438
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_FLUSH_LBN 9
21439
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_FLUSH_WIDTH 1
21440
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_TOPOLOGY_OFST 0
21441
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_TOPOLOGY_LBN 10
21442
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_TOPOLOGY_WIDTH 1
21443
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_CONFIG_WCE_OFST 0
21444
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_CONFIG_WCE_LBN 11
21445
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_CONFIG_WCE_WIDTH 1
21446
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_MQ_OFST 0
21447
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_MQ_LBN 12
21448
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_MQ_WIDTH 1
21449
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_DISCARD_OFST 0
21450
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_DISCARD_LBN 13
21451
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_DISCARD_WIDTH 1
21452
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_WRITE_ZEROES_OFST 0
21453
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_WRITE_ZEROES_LBN 14
21454
+#define        VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_WRITE_ZEROES_WIDTH 1
21455
+#define        VIRTIO_BLK_CONFIG_VIRTIO_F_RING_INDIRECT_DESC_OFST 0
21456
+#define        VIRTIO_BLK_CONFIG_VIRTIO_F_RING_INDIRECT_DESC_LBN 28
21457
+#define        VIRTIO_BLK_CONFIG_VIRTIO_F_RING_INDIRECT_DESC_WIDTH 1
21458
+#define        VIRTIO_BLK_CONFIG_VIRTIO_F_RING_EVENT_IDX_OFST 0
21459
+#define        VIRTIO_BLK_CONFIG_VIRTIO_F_RING_EVENT_IDX_LBN 29
21460
+#define        VIRTIO_BLK_CONFIG_VIRTIO_F_RING_EVENT_IDX_WIDTH 1
21461
+#define        VIRTIO_BLK_CONFIG_VIRTIO_F_VERSION_1_OFST 0
21462
+#define        VIRTIO_BLK_CONFIG_VIRTIO_F_VERSION_1_LBN 32
21463
+#define        VIRTIO_BLK_CONFIG_VIRTIO_F_VERSION_1_WIDTH 1
21464
+#define        VIRTIO_BLK_CONFIG_VIRTIO_F_ACCESS_PLATFORM_OFST 0
21465
+#define        VIRTIO_BLK_CONFIG_VIRTIO_F_ACCESS_PLATFORM_LBN 33
21466
+#define        VIRTIO_BLK_CONFIG_VIRTIO_F_ACCESS_PLATFORM_WIDTH 1
21467
+#define        VIRTIO_BLK_CONFIG_VIRTIO_F_RING_PACKED_OFST 0
21468
+#define        VIRTIO_BLK_CONFIG_VIRTIO_F_RING_PACKED_LBN 34
21469
+#define        VIRTIO_BLK_CONFIG_VIRTIO_F_RING_PACKED_WIDTH 1
21470
+#define        VIRTIO_BLK_CONFIG_VIRTIO_F_IN_ORDER_OFST 0
21471
+#define        VIRTIO_BLK_CONFIG_VIRTIO_F_IN_ORDER_LBN 35
21472
+#define        VIRTIO_BLK_CONFIG_VIRTIO_F_IN_ORDER_WIDTH 1
21473
+#define        VIRTIO_BLK_CONFIG_VIRTIO_F_ORDER_PLATFORM_OFST 0
21474
+#define        VIRTIO_BLK_CONFIG_VIRTIO_F_ORDER_PLATFORM_LBN 36
21475
+#define        VIRTIO_BLK_CONFIG_VIRTIO_F_ORDER_PLATFORM_WIDTH 1
21476
+#define        VIRTIO_BLK_CONFIG_VIRTIO_F_SR_IOV_OFST 0
21477
+#define        VIRTIO_BLK_CONFIG_VIRTIO_F_SR_IOV_LBN 37
21478
+#define        VIRTIO_BLK_CONFIG_VIRTIO_F_SR_IOV_WIDTH 1
21479
+#define        VIRTIO_BLK_CONFIG_VIRTIO_F_NOTIFICATION_DATA_OFST 0
21480
+#define        VIRTIO_BLK_CONFIG_VIRTIO_F_NOTIFICATION_DATA_LBN 38
21481
+#define        VIRTIO_BLK_CONFIG_VIRTIO_F_NOTIFICATION_DATA_WIDTH 1
21482
+#define       VIRTIO_BLK_CONFIG_FEATURES_LBN 0
21483
+#define       VIRTIO_BLK_CONFIG_FEATURES_WIDTH 64
21484
+/* The capacity of the device (expressed in 512-byte sectors) */
21485
+#define       VIRTIO_BLK_CONFIG_CAPACITY_OFST 8
21486
+#define       VIRTIO_BLK_CONFIG_CAPACITY_LEN 8
21487
+#define       VIRTIO_BLK_CONFIG_CAPACITY_LO_OFST 8
21488
+#define       VIRTIO_BLK_CONFIG_CAPACITY_HI_OFST 12
21489
+#define       VIRTIO_BLK_CONFIG_CAPACITY_LBN 64
21490
+#define       VIRTIO_BLK_CONFIG_CAPACITY_WIDTH 64
21491
+/* Maximum size of any single segment. Only valid when VIRTIO_BLK_F_SIZE_MAX is
21492
+ * set.
21493
+ */
21494
+#define       VIRTIO_BLK_CONFIG_SIZE_MAX_OFST 16
21495
+#define       VIRTIO_BLK_CONFIG_SIZE_MAX_LEN 4
21496
+#define       VIRTIO_BLK_CONFIG_SIZE_MAX_LBN 128
21497
+#define       VIRTIO_BLK_CONFIG_SIZE_MAX_WIDTH 32
21498
+/* Maximum number of segments in a request. Only valid when
21499
+ * VIRTIO_BLK_F_SEG_MAX is set.
21500
+ */
21501
+#define       VIRTIO_BLK_CONFIG_SEG_MAX_OFST 20
21502
+#define       VIRTIO_BLK_CONFIG_SEG_MAX_LEN 4
21503
+#define       VIRTIO_BLK_CONFIG_SEG_MAX_LBN 160
21504
+#define       VIRTIO_BLK_CONFIG_SEG_MAX_WIDTH 32
21505
+/* Disk-style geometry - cylinders. Only valid when VIRTIO_BLK_F_GEOMETRY is
21506
+ * set.
21507
+ */
21508
+#define       VIRTIO_BLK_CONFIG_CYLINDERS_OFST 24
21509
+#define       VIRTIO_BLK_CONFIG_CYLINDERS_LEN 2
21510
+#define       VIRTIO_BLK_CONFIG_CYLINDERS_LBN 192
21511
+#define       VIRTIO_BLK_CONFIG_CYLINDERS_WIDTH 16
21512
+/* Disk-style geometry - heads. Only valid when VIRTIO_BLK_F_GEOMETRY is set.
21513
+ */
21514
+#define       VIRTIO_BLK_CONFIG_HEADS_OFST 26
21515
+#define       VIRTIO_BLK_CONFIG_HEADS_LEN 1
21516
+#define       VIRTIO_BLK_CONFIG_HEADS_LBN 208
21517
+#define       VIRTIO_BLK_CONFIG_HEADS_WIDTH 8
21518
+/* Disk-style geometry - sectors. Only valid when VIRTIO_BLK_F_GEOMETRY is set.
21519
+ */
21520
+#define       VIRTIO_BLK_CONFIG_SECTORS_OFST 27
21521
+#define       VIRTIO_BLK_CONFIG_SECTORS_LEN 1
21522
+#define       VIRTIO_BLK_CONFIG_SECTORS_LBN 216
21523
+#define       VIRTIO_BLK_CONFIG_SECTORS_WIDTH 8
21524
+/* Block size of disk. Only valid when VIRTIO_BLK_F_BLK_SIZE is set. */
21525
+#define       VIRTIO_BLK_CONFIG_BLK_SIZE_OFST 28
21526
+#define       VIRTIO_BLK_CONFIG_BLK_SIZE_LEN 4
21527
+#define       VIRTIO_BLK_CONFIG_BLK_SIZE_LBN 224
21528
+#define       VIRTIO_BLK_CONFIG_BLK_SIZE_WIDTH 32
21529
+/* Block topology - number of logical blocks per physical block (log2). Only
21530
+ * valid when VIRTIO_BLK_F_TOPOLOGY is set.
21531
+ */
21532
+#define       VIRTIO_BLK_CONFIG_PHYSICAL_BLOCK_EXP_OFST 32
21533
+#define       VIRTIO_BLK_CONFIG_PHYSICAL_BLOCK_EXP_LEN 1
21534
+#define       VIRTIO_BLK_CONFIG_PHYSICAL_BLOCK_EXP_LBN 256
21535
+#define       VIRTIO_BLK_CONFIG_PHYSICAL_BLOCK_EXP_WIDTH 8
21536
+/* Block topology - offset of first aligned logical block. Only valid when
21537
+ * VIRTIO_BLK_F_TOPOLOGY is set.
21538
+ */
21539
+#define       VIRTIO_BLK_CONFIG_ALIGNMENT_OFFSET_OFST 33
21540
+#define       VIRTIO_BLK_CONFIG_ALIGNMENT_OFFSET_LEN 1
21541
+#define       VIRTIO_BLK_CONFIG_ALIGNMENT_OFFSET_LBN 264
21542
+#define       VIRTIO_BLK_CONFIG_ALIGNMENT_OFFSET_WIDTH 8
21543
+/* Block topology - suggested minimum I/O size in blocks. Only valid when
21544
+ * VIRTIO_BLK_F_TOPOLOGY is set.
21545
+ */
21546
+#define       VIRTIO_BLK_CONFIG_MIN_IO_SIZE_OFST 34
21547
+#define       VIRTIO_BLK_CONFIG_MIN_IO_SIZE_LEN 2
21548
+#define       VIRTIO_BLK_CONFIG_MIN_IO_SIZE_LBN 272
21549
+#define       VIRTIO_BLK_CONFIG_MIN_IO_SIZE_WIDTH 16
21550
+/* Block topology - optimal (suggested maximum) I/O size in blocks. Only valid
21551
+ * when VIRTIO_BLK_F_TOPOLOGY is set.
21552
+ */
21553
+#define       VIRTIO_BLK_CONFIG_OPT_IO_SIZE_OFST 36
21554
+#define       VIRTIO_BLK_CONFIG_OPT_IO_SIZE_LEN 4
21555
+#define       VIRTIO_BLK_CONFIG_OPT_IO_SIZE_LBN 288
21556
+#define       VIRTIO_BLK_CONFIG_OPT_IO_SIZE_WIDTH 32
21557
+/* Unused, set to zero. Note that virtio_blk_config.writeback is volatile and
21558
+ * not carried in config data.
21559
+ */
21560
+#define       VIRTIO_BLK_CONFIG_UNUSED0_OFST 40
21561
+#define       VIRTIO_BLK_CONFIG_UNUSED0_LEN 2
21562
+#define       VIRTIO_BLK_CONFIG_UNUSED0_LBN 320
21563
+#define       VIRTIO_BLK_CONFIG_UNUSED0_WIDTH 16
21564
+/* Number of queues. Only valid if the VIRTIO_BLK_F_MQ feature is negotiated.
21565
+ */
21566
+#define       VIRTIO_BLK_CONFIG_NUM_QUEUES_OFST 42
21567
+#define       VIRTIO_BLK_CONFIG_NUM_QUEUES_LEN 2
21568
+#define       VIRTIO_BLK_CONFIG_NUM_QUEUES_LBN 336
21569
+#define       VIRTIO_BLK_CONFIG_NUM_QUEUES_WIDTH 16
21570
+/* Maximum discard sectors size, in 512-byte units. Only valid if
21571
+ * VIRTIO_BLK_F_DISCARD is set.
21572
+ */
21573
+#define       VIRTIO_BLK_CONFIG_MAX_DISCARD_SECTORS_OFST 44
21574
+#define       VIRTIO_BLK_CONFIG_MAX_DISCARD_SECTORS_LEN 4
21575
+#define       VIRTIO_BLK_CONFIG_MAX_DISCARD_SECTORS_LBN 352
21576
+#define       VIRTIO_BLK_CONFIG_MAX_DISCARD_SECTORS_WIDTH 32
21577
+/* Maximum discard segment number. Only valid if VIRTIO_BLK_F_DISCARD is set.
21578
+ */
21579
+#define       VIRTIO_BLK_CONFIG_MAX_DISCARD_SEG_OFST 48
21580
+#define       VIRTIO_BLK_CONFIG_MAX_DISCARD_SEG_LEN 4
21581
+#define       VIRTIO_BLK_CONFIG_MAX_DISCARD_SEG_LBN 384
21582
+#define       VIRTIO_BLK_CONFIG_MAX_DISCARD_SEG_WIDTH 32
21583
+/* Discard sector alignment, in 512-byte units. Only valid if
21584
+ * VIRTIO_BLK_F_DISCARD is set.
21585
+ */
21586
+#define       VIRTIO_BLK_CONFIG_DISCARD_SECTOR_ALIGNMENT_OFST 52
21587
+#define       VIRTIO_BLK_CONFIG_DISCARD_SECTOR_ALIGNMENT_LEN 4
21588
+#define       VIRTIO_BLK_CONFIG_DISCARD_SECTOR_ALIGNMENT_LBN 416
21589
+#define       VIRTIO_BLK_CONFIG_DISCARD_SECTOR_ALIGNMENT_WIDTH 32
21590
+/* Maximum write zeroes sectors size, in 512-byte units. Only valid if
21591
+ * VIRTIO_BLK_F_WRITE_ZEROES is set.
21592
+ */
21593
+#define       VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SECTORS_OFST 56
21594
+#define       VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SECTORS_LEN 4
21595
+#define       VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SECTORS_LBN 448
21596
+#define       VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SECTORS_WIDTH 32
21597
+/* Maximum write zeroes segment number. Only valid if VIRTIO_BLK_F_WRITE_ZEROES
21598
+ * is set.
21599
+ */
21600
+#define       VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SEG_OFST 60
21601
+#define       VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SEG_LEN 4
21602
+#define       VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SEG_LBN 480
21603
+#define       VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SEG_WIDTH 32
21604
+/* Write zeroes request can result in deallocating one or more sectors. Only
21605
+ * valid if VIRTIO_BLK_F_WRITE_ZEROES is set.
21606
+ */
21607
+#define       VIRTIO_BLK_CONFIG_WRITE_ZEROES_MAY_UNMAP_OFST 64
21608
+#define       VIRTIO_BLK_CONFIG_WRITE_ZEROES_MAY_UNMAP_LEN 1
21609
+#define       VIRTIO_BLK_CONFIG_WRITE_ZEROES_MAY_UNMAP_LBN 512
21610
+#define       VIRTIO_BLK_CONFIG_WRITE_ZEROES_MAY_UNMAP_WIDTH 8
21611
+/* Unused, set to zero. */
21612
+#define       VIRTIO_BLK_CONFIG_UNUSED1_OFST 65
21613
+#define       VIRTIO_BLK_CONFIG_UNUSED1_LEN 3
21614
+#define       VIRTIO_BLK_CONFIG_UNUSED1_LBN 520
21615
+#define       VIRTIO_BLK_CONFIG_UNUSED1_WIDTH 24
21616
+
21617
+
21618
+/***********************************/
21619
+/* MC_CMD_DESC_PROXY_FUNC_CONFIG_SET
21620
+ * Set configuration for an existing descriptor proxy function. Configuration
21621
+ * data must match function personality. The actual function configuration is
21622
+ * not persisted until the caller commits with MC_CMD_DESC_PROXY_FUNC_COMMIT_IN
21623
+ */
21624
+#define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET 0x174
21625
+#undef MC_CMD_0x174_PRIVILEGE_CTG
21626
+
21627
+#define MC_CMD_0x174_PRIVILEGE_CTG SRIOV_CTG_ADMIN
21628
+
21629
+/* MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN msgrequest */
21630
+#define    MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_LENMIN 20
21631
+#define    MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_LENMAX 252
21632
+#define    MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_LENMAX_MCDI2 1020
21633
+#define    MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_LEN(num) (20+1*(num))
21634
+#define    MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_NUM(len) (((len)-20)/1)
21635
+/* Handle to descriptor proxy function (as returned by
21636
+ * MC_CMD_DESC_PROXY_FUNC_OPEN)
21637
+ */
21638
+#define       MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_HANDLE_OFST 0
21639
+#define       MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_HANDLE_LEN 4
21640
+/* Reserved for future extension, set to zero. */
21641
+#define       MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_RESERVED_OFST 4
21642
+#define       MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_RESERVED_LEN 16
21643
+/* Configuration data. Format of configuration data is determined implicitly
21644
+ * from function personality referred to by HANDLE. Currently, only supported
21645
+ * format is VIRTIO_BLK_CONFIG.
21646
+ */
21647
+#define       MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_OFST 20
21648
+#define       MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_LEN 1
21649
+#define       MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_MINNUM 0
21650
+#define       MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_MAXNUM 232
21651
+#define       MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_MAXNUM_MCDI2 1000
21652
+
21653
+/* MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_OUT msgresponse */
21654
+#define    MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_OUT_LEN 0
21655
+
21656
+
21657
+/***********************************/
21658
+/* MC_CMD_DESC_PROXY_FUNC_COMMIT
21659
+ * Commit function configuration to non-volatile or volatile store. Once
21660
+ * configuration is applied to hardware (which may happen immediately or on
21661
+ * next function/device reset) a DESC_PROXY_FUNC_CONFIG_SET MCDI event will be
21662
+ * delivered to callers MCDI event queue.
21663
+ */
21664
+#define MC_CMD_DESC_PROXY_FUNC_COMMIT 0x175
21665
+#undef MC_CMD_0x175_PRIVILEGE_CTG
21666
+
21667
+#define MC_CMD_0x175_PRIVILEGE_CTG SRIOV_CTG_ADMIN
21668
+
21669
+/* MC_CMD_DESC_PROXY_FUNC_COMMIT_IN msgrequest */
21670
+#define    MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_LEN 8
21671
+/* Handle to descriptor proxy function (as returned by
21672
+ * MC_CMD_DESC_PROXY_FUNC_OPEN)
21673
+ */
21674
+#define       MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_HANDLE_OFST 0
21675
+#define       MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_HANDLE_LEN 4
21676
+#define       MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_STORE_OFST 4
21677
+#define       MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_STORE_LEN 4
21678
+/* enum: Store into non-volatile (dynamic) config */
21679
+#define          MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_NON_VOLATILE 0x0
21680
+/* enum: Store into volatile (ephemeral) config */
21681
+#define          MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_VOLATILE 0x1
21682
+
21683
+/* MC_CMD_DESC_PROXY_FUNC_COMMIT_OUT msgresponse */
21684
+#define    MC_CMD_DESC_PROXY_FUNC_COMMIT_OUT_LEN 4
21685
+/* Generation count to be delivered in an event once configuration becomes live
21686
+ */
21687
+#define       MC_CMD_DESC_PROXY_FUNC_COMMIT_OUT_CONFIG_GENERATION_OFST 0
21688
+#define       MC_CMD_DESC_PROXY_FUNC_COMMIT_OUT_CONFIG_GENERATION_LEN 4
21689
+
21690
+
21691
+/***********************************/
21692
+/* MC_CMD_DESC_PROXY_FUNC_OPEN
21693
+ * Retrieve a handle for an existing descriptor proxy function. Returns an
21694
+ * integer handle, valid until function is deallocated, MC rebooted or power-
21695
+ * cycle. Returns ENODEV if no function with given label exists.
21696
+ */
21697
+#define MC_CMD_DESC_PROXY_FUNC_OPEN 0x176
21698
+#undef MC_CMD_0x176_PRIVILEGE_CTG
21699
+
21700
+#define MC_CMD_0x176_PRIVILEGE_CTG SRIOV_CTG_ADMIN
21701
+
21702
+/* MC_CMD_DESC_PROXY_FUNC_OPEN_IN msgrequest */
21703
+#define    MC_CMD_DESC_PROXY_FUNC_OPEN_IN_LEN 40
21704
+/* User-defined label (zero-terminated ASCII string) to uniquely identify the
21705
+ * function
21706
+ */
21707
+#define       MC_CMD_DESC_PROXY_FUNC_OPEN_IN_LABEL_OFST 0
21708
+#define       MC_CMD_DESC_PROXY_FUNC_OPEN_IN_LABEL_LEN 40
21709
+
21710
+/* MC_CMD_DESC_PROXY_FUNC_OPEN_OUT msgresponse */
21711
+#define    MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_LENMIN 40
21712
+#define    MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_LENMAX 252
21713
+#define    MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_LENMAX_MCDI2 1020
21714
+#define    MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_LEN(num) (40+1*(num))
21715
+#define    MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_NUM(len) (((len)-40)/1)
21716
+/* Handle to the descriptor proxy function */
21717
+#define       MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_HANDLE_OFST 0
21718
+#define       MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_HANDLE_LEN 4
21719
+/* PCIe Function ID (as struct PCIE_FUNCTION) */
21720
+#define       MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_OFST 4
21721
+#define       MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LEN 8
21722
+#define       MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_OFST 4
21723
+#define       MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_HI_OFST 8
21724
+/* Function personality */
21725
+#define       MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_PERSONALITY_OFST 12
21726
+#define       MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_PERSONALITY_LEN 4
21727
+/*            Enum values, see field(s): */
21728
+/*               FUNCTION_PERSONALITY/ID */
21729
+/* Function configuration state */
21730
+#define       MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_STATUS_OFST 16
21731
+#define       MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_STATUS_LEN 4
21732
+/* enum: Function configuration is visible to the host (live) */
21733
+#define          MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_LIVE 0x0
21734
+/* enum: Function configuration is pending reset */
21735
+#define          MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_PENDING 0x1
21736
+/* Generation count to be delivered in an event once the configuration becomes
21737
+ * live (if status is "pending")
21738
+ */
21739
+#define       MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_GENERATION_OFST 20
21740
+#define       MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_GENERATION_LEN 4
21741
+/* Reserved for future extension, set to zero. */
21742
+#define       MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_RESERVED_OFST 24
21743
+#define       MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_RESERVED_LEN 16
21744
+/* Configuration data corresponding to function personality. Currently, only
21745
+ * supported format is VIRTIO_BLK_CONFIG
21746
+ */
21747
+#define       MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_OFST 40
21748
+#define       MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_LEN 1
21749
+#define       MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_MINNUM 0
21750
+#define       MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_MAXNUM 212
21751
+#define       MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_MAXNUM_MCDI2 980
21752
+
21753
+
21754
+/***********************************/
21755
+/* MC_CMD_DESC_PROXY_FUNC_CLOSE
21756
+ * Releases a handle for an open descriptor proxy function. If proxying was
21757
+ * enabled on the device, the caller is expected to gracefully stop it using
21758
+ * MC_CMD_DESC_PROXY_FUNC_DISABLE prior to calling this function. Closing an
21759
+ * active device without disabling proxying will result in forced close, which
21760
+ * will put the device into a failed state and signal the host driver of the
21761
+ * error (for virtio, DEVICE_NEEDS_RESET flag would be set on the host side)
21762
+ */
21763
+#define MC_CMD_DESC_PROXY_FUNC_CLOSE 0x1a1
21764
+#undef MC_CMD_0x1a1_PRIVILEGE_CTG
21765
+
21766
+#define MC_CMD_0x1a1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
21767
+
21768
+/* MC_CMD_DESC_PROXY_FUNC_CLOSE_IN msgrequest */
21769
+#define    MC_CMD_DESC_PROXY_FUNC_CLOSE_IN_LEN 4
21770
+/* Handle to the descriptor proxy function */
21771
+#define       MC_CMD_DESC_PROXY_FUNC_CLOSE_IN_HANDLE_OFST 0
21772
+#define       MC_CMD_DESC_PROXY_FUNC_CLOSE_IN_HANDLE_LEN 4
21773
+
21774
+/* MC_CMD_DESC_PROXY_FUNC_CLOSE_OUT msgresponse */
21775
+#define    MC_CMD_DESC_PROXY_FUNC_CLOSE_OUT_LEN 0
21776
+
21777
+/* DESC_PROXY_FUNC_MAP structuredef */
21778
+#define    DESC_PROXY_FUNC_MAP_LEN 52
21779
+/* PCIe function ID (as struct PCIE_FUNCTION) */
21780
+#define       DESC_PROXY_FUNC_MAP_FUNC_OFST 0
21781
+#define       DESC_PROXY_FUNC_MAP_FUNC_LEN 8
21782
+#define       DESC_PROXY_FUNC_MAP_FUNC_LO_OFST 0
21783
+#define       DESC_PROXY_FUNC_MAP_FUNC_HI_OFST 4
21784
+#define       DESC_PROXY_FUNC_MAP_FUNC_LBN 0
21785
+#define       DESC_PROXY_FUNC_MAP_FUNC_WIDTH 64
21786
+/* Function personality */
21787
+#define       DESC_PROXY_FUNC_MAP_PERSONALITY_OFST 8
21788
+#define       DESC_PROXY_FUNC_MAP_PERSONALITY_LEN 4
21789
+/*            Enum values, see field(s): */
21790
+/*               FUNCTION_PERSONALITY/ID */
21791
+#define       DESC_PROXY_FUNC_MAP_PERSONALITY_LBN 64
21792
+#define       DESC_PROXY_FUNC_MAP_PERSONALITY_WIDTH 32
21793
+/* User-defined label (zero-terminated ASCII string) to uniquely identify the
21794
+ * function
21795
+ */
21796
+#define       DESC_PROXY_FUNC_MAP_LABEL_OFST 12
21797
+#define       DESC_PROXY_FUNC_MAP_LABEL_LEN 40
21798
+#define       DESC_PROXY_FUNC_MAP_LABEL_LBN 96
21799
+#define       DESC_PROXY_FUNC_MAP_LABEL_WIDTH 320
21800
+
21801
+
21802
+/***********************************/
21803
+/* MC_CMD_DESC_PROXY_FUNC_ENUM
21804
+ * Enumerate existing descriptor proxy functions
21805
+ */
21806
+#define MC_CMD_DESC_PROXY_FUNC_ENUM 0x177
21807
+#undef MC_CMD_0x177_PRIVILEGE_CTG
21808
+
21809
+#define MC_CMD_0x177_PRIVILEGE_CTG SRIOV_CTG_ADMIN
21810
+
21811
+/* MC_CMD_DESC_PROXY_FUNC_ENUM_IN msgrequest */
21812
+#define    MC_CMD_DESC_PROXY_FUNC_ENUM_IN_LEN 4
21813
+/* Starting index, set to 0 on first request. See
21814
+ * MC_CMD_DESC_PROXY_FUNC_ENUM_OUT/FLAGS.
21815
+ */
21816
+#define       MC_CMD_DESC_PROXY_FUNC_ENUM_IN_START_IDX_OFST 0
21817
+#define       MC_CMD_DESC_PROXY_FUNC_ENUM_IN_START_IDX_LEN 4
21818
+
21819
+/* MC_CMD_DESC_PROXY_FUNC_ENUM_OUT msgresponse */
21820
+#define    MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_LENMIN 4
21821
+#define    MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_LENMAX 212
21822
+#define    MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_LENMAX_MCDI2 992
21823
+#define    MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_LEN(num) (4+52*(num))
21824
+#define    MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_NUM(len) (((len)-4)/52)
21825
+#define       MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FLAGS_OFST 0
21826
+#define       MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FLAGS_LEN 4
21827
+#define        MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_MORE_DATA_OFST 0
21828
+#define        MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_MORE_DATA_LBN 0
21829
+#define        MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_MORE_DATA_WIDTH 1
21830
+/* Function map, as array of DESC_PROXY_FUNC_MAP */
21831
+#define       MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_OFST 4
21832
+#define       MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_LEN 52
21833
+#define       MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_MINNUM 0
21834
+#define       MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_MAXNUM 4
21835
+#define       MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_MAXNUM_MCDI2 19
21836
+
21837
+
21838
+/***********************************/
21839
+/* MC_CMD_DESC_PROXY_FUNC_ENABLE
21840
+ * Enable descriptor proxying for function into target event queue. Returns VI
21841
+ * allocation info for the proxy source function, so that the caller can map
21842
+ * absolute VI IDs from descriptor proxy events back to the originating
21843
+ * function.
21844
+ */
21845
+#define MC_CMD_DESC_PROXY_FUNC_ENABLE 0x178
21846
+#undef MC_CMD_0x178_PRIVILEGE_CTG
21847
+
21848
+#define MC_CMD_0x178_PRIVILEGE_CTG SRIOV_CTG_ADMIN
21849
+
21850
+/* MC_CMD_DESC_PROXY_FUNC_ENABLE_IN msgrequest */
21851
+#define    MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_LEN 8
21852
+/* Handle to descriptor proxy function (as returned by
21853
+ * MC_CMD_DESC_PROXY_FUNC_OPEN)
21854
+ */
21855
+#define       MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_HANDLE_OFST 0
21856
+#define       MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_HANDLE_LEN 4
21857
+/* Descriptor proxy sink queue (caller function relative). Must be extended
21858
+ * width event queue
21859
+ */
21860
+#define       MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_TARGET_EVQ_OFST 4
21861
+#define       MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_TARGET_EVQ_LEN 4
21862
+
21863
+/* MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT msgresponse */
21864
+#define    MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_LEN 8
21865
+/* The number of VIs allocated on the function */
21866
+#define       MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_COUNT_OFST 0
21867
+#define       MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_COUNT_LEN 4
21868
+/* The base absolute VI number allocated to the function. */
21869
+#define       MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_BASE_OFST 4
21870
+#define       MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_BASE_LEN 4
21871
+
21872
+
21873
+/***********************************/
21874
+/* MC_CMD_DESC_PROXY_FUNC_DISABLE
21875
+ * Disable descriptor proxying for function
21876
+ */
21877
+#define MC_CMD_DESC_PROXY_FUNC_DISABLE 0x179
21878
+#undef MC_CMD_0x179_PRIVILEGE_CTG
21879
+
21880
+#define MC_CMD_0x179_PRIVILEGE_CTG SRIOV_CTG_ADMIN
21881
+
21882
+/* MC_CMD_DESC_PROXY_FUNC_DISABLE_IN msgrequest */
21883
+#define    MC_CMD_DESC_PROXY_FUNC_DISABLE_IN_LEN 4
21884
+/* Handle to descriptor proxy function (as returned by
21885
+ * MC_CMD_DESC_PROXY_FUNC_OPEN)
21886
+ */
21887
+#define       MC_CMD_DESC_PROXY_FUNC_DISABLE_IN_HANDLE_OFST 0
21888
+#define       MC_CMD_DESC_PROXY_FUNC_DISABLE_IN_HANDLE_LEN 4
21889
+
21890
+/* MC_CMD_DESC_PROXY_FUNC_DISABLE_OUT msgresponse */
21891
+#define    MC_CMD_DESC_PROXY_FUNC_DISABLE_OUT_LEN 0
21892
+
21893
+
21894
+/***********************************/
21895
+/* MC_CMD_GET_ADDR_SPC_ID
21896
+ * Get Address space identifier for use in mem2mem descriptors for a given
21897
+ * target. See SF-120734-TC for details on ADDR_SPC_IDs and mem2mem
21898
+ * descriptors.
21899
+ */
21900
+#define MC_CMD_GET_ADDR_SPC_ID 0x1a0
21901
+#undef MC_CMD_0x1a0_PRIVILEGE_CTG
21902
+
21903
+#define MC_CMD_0x1a0_PRIVILEGE_CTG SRIOV_CTG_ADMIN
21904
+
21905
+/* MC_CMD_GET_ADDR_SPC_ID_IN msgrequest */
21906
+#define    MC_CMD_GET_ADDR_SPC_ID_IN_LEN 16
21907
+/* Resource type to get ADDR_SPC_ID for */
21908
+#define       MC_CMD_GET_ADDR_SPC_ID_IN_TYPE_OFST 0
21909
+#define       MC_CMD_GET_ADDR_SPC_ID_IN_TYPE_LEN 4
21910
+/* enum: Address space ID for host/AP memory DMA over the same interface this
21911
+ * MCDI was called on
21912
+ */
21913
+#define          MC_CMD_GET_ADDR_SPC_ID_IN_SELF 0x0
21914
+/* enum: Address space ID for host/AP memory DMA via PCI interface and function
21915
+ * specified by FUNC
21916
+ */
21917
+#define          MC_CMD_GET_ADDR_SPC_ID_IN_PCI_FUNC 0x1
21918
+/* enum: Address space ID for host/AP memory DMA via PCI interface and function
21919
+ * specified by FUNC with PASID value specified by PASID
21920
+ */
21921
+#define          MC_CMD_GET_ADDR_SPC_ID_IN_PCI_FUNC_PASID 0x2
21922
+/* enum: Address space ID for host/AP memory DMA via PCI interface and function
21923
+ * specified by FUNC with PASID value of relative VI specified by VI
21924
+ */
21925
+#define          MC_CMD_GET_ADDR_SPC_ID_IN_REL_VI 0x3
21926
+/* enum: Address space ID for host/AP memory DMA via PCI interface, function
21927
+ * and PASID value of absolute VI specified by VI
21928
+ */
21929
+#define          MC_CMD_GET_ADDR_SPC_ID_IN_ABS_VI 0x4
21930
+/* enum: Address space ID for host memory DMA via PCI interface and function of
21931
+ * descriptor proxy function specified by HANDLE
21932
+ */
21933
+#define          MC_CMD_GET_ADDR_SPC_ID_IN_DESC_PROXY_HANDLE 0x5
21934
+/* enum: Address space ID for DMA to/from MC memory */
21935
+#define          MC_CMD_GET_ADDR_SPC_ID_IN_MC_MEM 0x6
21936
+/* enum: Address space ID for DMA to/from other SmartNIC memory (on-chip, DDR)
21937
+ */
21938
+#define          MC_CMD_GET_ADDR_SPC_ID_IN_NIC_MEM 0x7
21939
+/* PCIe Function ID (as struct PCIE_FUNCTION). Only valid if TYPE is PCI_FUNC,
21940
+ * PCI_FUNC_PASID or REL_VI.
21941
+ */
21942
+#define       MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_OFST 4
21943
+#define       MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LEN 8
21944
+#define       MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_OFST 4
21945
+#define       MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_HI_OFST 8
21946
+/* PASID value. Only valid if TYPE is PCI_FUNC_PASID. */
21947
+#define       MC_CMD_GET_ADDR_SPC_ID_IN_PASID_OFST 12
21948
+#define       MC_CMD_GET_ADDR_SPC_ID_IN_PASID_LEN 4
21949
+/* Relative or absolute VI number. Only valid if TYPE is REL_VI or ABS_VI */
21950
+#define       MC_CMD_GET_ADDR_SPC_ID_IN_VI_OFST 12
21951
+#define       MC_CMD_GET_ADDR_SPC_ID_IN_VI_LEN 4
21952
+/* Descriptor proxy function handle. Only valid if TYPE is DESC_PROXY_HANDLE.
21953
+ */
21954
+#define       MC_CMD_GET_ADDR_SPC_ID_IN_HANDLE_OFST 4
21955
+#define       MC_CMD_GET_ADDR_SPC_ID_IN_HANDLE_LEN 4
21956
+
21957
+/* MC_CMD_GET_ADDR_SPC_ID_OUT msgresponse */
21958
+#define    MC_CMD_GET_ADDR_SPC_ID_OUT_LEN 8
21959
+/* Address Space ID for the requested target. Only the lower 36 bits are valid
21960
+ * in the current SmartNIC implementation.
21961
+ */
21962
+#define       MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_OFST 0
21963
+#define       MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LEN 8
21964
+#define       MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_OFST 0
21965
+#define       MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_OFST 4
21966
+
21967
+
1515821968 #endif /* MCDI_PCOL_H */