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2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da 
 kernel/drivers/net/ethernet/qlogic/qed/qed_dcbx.c
....@@ -1,33 +1,7 @@
1
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
12 /* QLogic qed NIC Driver
23  * Copyright (c) 2015-2017  QLogic Corporation
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- *
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- * This software is available to you under a choice of one of two
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- * licenses.  You may choose to be licensed under the terms of the GNU
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- * General Public License (GPL) Version 2, available from the file
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- * COPYING in the main directory of this source tree, or the
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- * OpenIB.org BSD license below:
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- *
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- *     Redistribution and use in source and binary forms, with or
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- *     without modification, are permitted provided that the following
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- *     conditions are met:
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- *
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- *      - Redistributions of source code must retain the above
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- *        copyright notice, this list of conditions and the following
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- *        disclaimer.
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- *
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- *      - Redistributions in binary form must reproduce the above
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- *        copyright notice, this list of conditions and the following
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- *        disclaimer in the documentation and /or other materials
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- *        provided with the distribution.
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- *
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- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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- * SOFTWARE.
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+ * Copyright (c) 2019-2020 Marvell International Ltd.
315  */
326 
337 #include <linux/types.h>
....@@ -204,9 +178,7 @@
204178 	else
205179 		p_data->arr[type].update = DONT_UPDATE_DCB_DSCP;
206180 
207
-	/* Do not add vlan tag 0 when DCB is enabled and port in UFP/OV mode */
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-	if ((test_bit(QED_MF_8021Q_TAGGING, &p_hwfn->cdev->mf_bits) ||
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-	     test_bit(QED_MF_8021AD_TAGGING, &p_hwfn->cdev->mf_bits)))
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+	if (test_bit(QED_MF_DONT_ADD_VLAN0_TAG, &p_hwfn->cdev->mf_bits))
210182 		p_data->arr[type].dont_add_vlan0 = true;
211183 
212184 	/* QM reconf data */
....@@ -262,8 +234,9 @@
262234 		*type = DCBX_PROTOCOL_ROCE_V2;
263235 	} else {
264236 		*type = DCBX_MAX_PROTOCOL_TYPE;
265
-		DP_ERR(p_hwfn, "No action required, App TLV entry = 0x%x\n",
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-		       app_prio_bitmap);
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+		DP_VERBOSE(p_hwfn, QED_MSG_DCB,
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+			   "No action required, App TLV entry = 0x%x\n",
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+			   app_prio_bitmap);
267240 		return false;
268241 	}
269242 
....@@ -574,7 +547,8 @@
574547 		      struct dcbx_ets_feature *p_ets,
575548 		      struct qed_dcbx_params *p_params)
576549 {
577
-	u32 bw_map[2], tsa_map[2], pri_map;
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+	__be32 bw_map[2], tsa_map[2];
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+	u32 pri_map;
578552 	int i;
579553 
580554 	p_params->ets_willing = QED_MFW_GET_FIELD(p_ets->flags,
....@@ -600,11 +574,10 @@
600574 	/* 8 bit tsa and bw data corresponding to each of the 8 TC's are
601575 	 * encoded in a type u32 array of size 2.
602576 	 */
603
-	bw_map[0] = be32_to_cpu(p_ets->tc_bw_tbl[0]);
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-	bw_map[1] = be32_to_cpu(p_ets->tc_bw_tbl[1]);
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-	tsa_map[0] = be32_to_cpu(p_ets->tc_tsa_tbl[0]);
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-	tsa_map[1] = be32_to_cpu(p_ets->tc_tsa_tbl[1]);
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+	cpu_to_be32_array(bw_map, p_ets->tc_bw_tbl, 2);
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+	cpu_to_be32_array(tsa_map, p_ets->tc_tsa_tbl, 2);
607579 	pri_map = p_ets->pri_tc_tbl[0];
580
+
608581 	for (i = 0; i < QED_MAX_PFC_PRIORITIES; i++) {
609582 		p_params->ets_tc_bw_tbl[i] = ((u8 *)bw_map)[i];
610583 		p_params->ets_tc_tsa_tbl[i] = ((u8 *)tsa_map)[i];
....@@ -1081,7 +1054,7 @@
10811054 		      struct dcbx_ets_feature *p_ets,
10821055 		      struct qed_dcbx_params *p_params)
10831056 {
1084
-	u8 *bw_map, *tsa_map;
1057
+	__be32 bw_map[2], tsa_map[2];
10851058 	u32 val;
10861059 	int i;
10871060 
....@@ -1103,22 +1076,21 @@
11031076 	p_ets->flags &= ~DCBX_ETS_MAX_TCS_MASK;
11041077 	p_ets->flags |= (u32)p_params->max_ets_tc << DCBX_ETS_MAX_TCS_SHIFT;
11051078 
1106
-	bw_map = (u8 *)&p_ets->tc_bw_tbl[0];
1107
-	tsa_map = (u8 *)&p_ets->tc_tsa_tbl[0];
11081079 	p_ets->pri_tc_tbl[0] = 0;
1080
+
11091081 	for (i = 0; i < QED_MAX_PFC_PRIORITIES; i++) {
1110
-		bw_map[i] = p_params->ets_tc_bw_tbl[i];
1111
-		tsa_map[i] = p_params->ets_tc_tsa_tbl[i];
1082
+		((u8 *)bw_map)[i] = p_params->ets_tc_bw_tbl[i];
1083
+		((u8 *)tsa_map)[i] = p_params->ets_tc_tsa_tbl[i];
1084
+
11121085 		/* Copy the priority value to the corresponding 4 bits in the
11131086 		 * traffic class table.
11141087 		 */
11151088 		val = (((u32)p_params->ets_pri_tc_tbl[i]) << ((7 - i) * 4));
11161089 		p_ets->pri_tc_tbl[0] |= val;
11171090 	}
1118
-	for (i = 0; i < 2; i++) {
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-		p_ets->tc_bw_tbl[i] = cpu_to_be32(p_ets->tc_bw_tbl[i]);
1120
-		p_ets->tc_tsa_tbl[i] = cpu_to_be32(p_ets->tc_tsa_tbl[i]);
1121
-	}
1091
+
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+	be32_to_cpu_array(p_ets->tc_bw_tbl, bw_map, 2);
1093
+	be32_to_cpu_array(p_ets->tc_tsa_tbl, tsa_map, 2);
11221094 }
11231095 
11241096 static void