forked from ~ljy/RK356X_SDK_RELEASE
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2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da 
 kernel/drivers/net/ethernet/mellanox/mlxsw/i2c.c
....@@ -14,14 +14,17 @@
1414 #include "cmd.h"
1515 #include "core.h"
1616 #include "i2c.h"
17
+#include "resources.h"
1718 
1819 #define MLXSW_I2C_CIR2_BASE		0x72000
1920 #define MLXSW_I2C_CIR_STATUS_OFF	0x18
2021 #define MLXSW_I2C_CIR2_OFF_STATUS	(MLXSW_I2C_CIR2_BASE + \
2122 					 MLXSW_I2C_CIR_STATUS_OFF)
2223 #define MLXSW_I2C_OPMOD_SHIFT		12
24
+#define MLXSW_I2C_EVENT_BIT_SHIFT	22
2325 #define MLXSW_I2C_GO_BIT_SHIFT		23
2426 #define MLXSW_I2C_CIR_CTRL_STATUS_SHIFT	24
27
+#define MLXSW_I2C_EVENT_BIT		BIT(MLXSW_I2C_EVENT_BIT_SHIFT)
2528 #define MLXSW_I2C_GO_BIT		BIT(MLXSW_I2C_GO_BIT_SHIFT)
2629 #define MLXSW_I2C_GO_OPMODE		BIT(MLXSW_I2C_OPMOD_SHIFT)
2730 #define MLXSW_I2C_SET_IMM_CMD		(MLXSW_I2C_GO_OPMODE | \
....@@ -33,20 +36,25 @@
3336 #define MLXSW_I2C_TLV_HDR_SIZE		0x10
3437 #define MLXSW_I2C_ADDR_WIDTH		4
3538 #define MLXSW_I2C_PUSH_CMD_SIZE		(MLXSW_I2C_ADDR_WIDTH + 4)
39
+#define MLXSW_I2C_SET_EVENT_CMD		(MLXSW_I2C_EVENT_BIT)
40
+#define MLXSW_I2C_PUSH_EVENT_CMD	(MLXSW_I2C_GO_BIT | \
41
+					 MLXSW_I2C_SET_EVENT_CMD)
3642 #define MLXSW_I2C_READ_SEMA_SIZE	4
3743 #define MLXSW_I2C_PREP_SIZE		(MLXSW_I2C_ADDR_WIDTH + 28)
3844 #define MLXSW_I2C_MBOX_SIZE		20
3945 #define MLXSW_I2C_MBOX_OUT_PARAM_OFF	12
40
-#define MLXSW_I2C_MAX_BUFF_SIZE		32
4146 #define MLXSW_I2C_MBOX_OFFSET_BITS	20
4247 #define MLXSW_I2C_MBOX_SIZE_BITS	12
4348 #define MLXSW_I2C_ADDR_BUF_SIZE		4
44
-#define MLXSW_I2C_BLK_MAX		32
49
+#define MLXSW_I2C_BLK_DEF		32
50
+#define MLXSW_I2C_BLK_MAX		100
4551 #define MLXSW_I2C_RETRY			5
4652 #define MLXSW_I2C_TIMEOUT_MSECS		5000
53
+#define MLXSW_I2C_MAX_DATA_SIZE		256
4754 
4855 /**
4956  * struct mlxsw_i2c - device private data:
57
+ * @cmd: command attributes;
5058  * @cmd.mb_size_in: input mailbox size;
5159  * @cmd.mb_off_in: input mailbox offset in register space;
5260  * @cmd.mb_size_out: output mailbox size;
....@@ -55,6 +63,7 @@
5563  * @dev: I2C device;
5664  * @core: switch core pointer;
5765  * @bus_info: bus info block;
66
+ * @block_size: maximum block size allowed to pass to under layer;
5867  */
5968 struct mlxsw_i2c {
6069 	struct {
....@@ -67,6 +76,7 @@
6776 	struct device *dev;
6877 	struct mlxsw_core *core;
6978 	struct mlxsw_bus_info bus_info;
79
+	u16 block_size;
7080 };
7181 
7282 #define MLXSW_I2C_READ_MSG(_client, _addr_buf, _buf, _len) {	\
....@@ -167,7 +177,7 @@
167177 	return err > 0 ? 0 : err;
168178 }
169179 
170
-/* Routine posts a command to ASIC though mail box. */
180
+/* Routine posts a command to ASIC through mail box. */
171181 static int mlxsw_i2c_write_cmd(struct i2c_client *client,
172182 			       struct mlxsw_i2c *mlxsw_i2c,
173183 			       int immediate)
....@@ -213,6 +223,66 @@
213223 	return 0;
214224 }
215225 
226
+/* Routine posts initialization command to ASIC through mail box. */
227
+static int
228
+mlxsw_i2c_write_init_cmd(struct i2c_client *client,
229
+			 struct mlxsw_i2c *mlxsw_i2c, u16 opcode, u32 in_mod)
230
+{
231
+	__be32 push_cmd_buf[MLXSW_I2C_PUSH_CMD_SIZE / 4] = {
232
+		0, cpu_to_be32(MLXSW_I2C_PUSH_EVENT_CMD)
233
+	};
234
+	__be32 prep_cmd_buf[MLXSW_I2C_PREP_SIZE / 4] = {
235
+		0, 0, 0, 0, 0, 0,
236
+		cpu_to_be32(client->adapter->nr & 0xffff),
237
+		cpu_to_be32(MLXSW_I2C_SET_EVENT_CMD)
238
+	};
239
+	struct i2c_msg push_cmd =
240
+		MLXSW_I2C_WRITE_MSG(client, push_cmd_buf,
241
+				    MLXSW_I2C_PUSH_CMD_SIZE);
242
+	struct i2c_msg prep_cmd =
243
+		MLXSW_I2C_WRITE_MSG(client, prep_cmd_buf, MLXSW_I2C_PREP_SIZE);
244
+	u8 status;
245
+	int err;
246
+
247
+	push_cmd_buf[1] = cpu_to_be32(MLXSW_I2C_PUSH_EVENT_CMD | opcode);
248
+	prep_cmd_buf[3] = cpu_to_be32(in_mod);
249
+	prep_cmd_buf[7] = cpu_to_be32(MLXSW_I2C_GO_BIT | opcode);
250
+	mlxsw_i2c_set_slave_addr((u8 *)prep_cmd_buf,
251
+				 MLXSW_I2C_CIR2_BASE);
252
+	mlxsw_i2c_set_slave_addr((u8 *)push_cmd_buf,
253
+				 MLXSW_I2C_CIR2_OFF_STATUS);
254
+
255
+	/* Prepare Command Interface Register for transaction */
256
+	err = i2c_transfer(client->adapter, &prep_cmd, 1);
257
+	if (err < 0)
258
+		return err;
259
+	else if (err != 1)
260
+		return -EIO;
261
+
262
+	/* Write out Command Interface Register GO bit to push transaction */
263
+	err = i2c_transfer(client->adapter, &push_cmd, 1);
264
+	if (err < 0)
265
+		return err;
266
+	else if (err != 1)
267
+		return -EIO;
268
+
269
+	/* Wait until go bit is cleared. */
270
+	err = mlxsw_i2c_wait_go_bit(client, mlxsw_i2c, &status);
271
+	if (err) {
272
+		dev_err(&client->dev, "HW semaphore is not released");
273
+		return err;
274
+	}
275
+
276
+	/* Validate transaction completion status. */
277
+	if (status) {
278
+		dev_err(&client->dev, "Bad transaction completion status %x\n",
279
+			status);
280
+		return -EIO;
281
+	}
282
+
283
+	return 0;
284
+}
285
+
216286 /* Routine obtains mail box offsets from ASIC register space. */
217287 static int mlxsw_i2c_get_mbox(struct i2c_client *client,
218288 			      struct mlxsw_i2c *mlxsw_i2c)
....@@ -248,20 +318,26 @@
248318 	struct i2c_client *client = to_i2c_client(dev);
249319 	struct mlxsw_i2c *mlxsw_i2c = i2c_get_clientdata(client);
250320 	unsigned long timeout = msecs_to_jiffies(MLXSW_I2C_TIMEOUT_MSECS);
251
-	u8 tran_buf[MLXSW_I2C_MAX_BUFF_SIZE + MLXSW_I2C_ADDR_BUF_SIZE];
252321 	int off = mlxsw_i2c->cmd.mb_off_in, chunk_size, i, j;
253322 	unsigned long end;
323
+	u8 *tran_buf;
254324 	struct i2c_msg write_tran =
255
-		MLXSW_I2C_WRITE_MSG(client, tran_buf, MLXSW_I2C_PUSH_CMD_SIZE);
325
+		MLXSW_I2C_WRITE_MSG(client, NULL, MLXSW_I2C_PUSH_CMD_SIZE);
256326 	int err;
257327 
328
+	tran_buf = kmalloc(mlxsw_i2c->block_size + MLXSW_I2C_ADDR_BUF_SIZE,
329
+			   GFP_KERNEL);
330
+	if (!tran_buf)
331
+		return -ENOMEM;
332
+
333
+	write_tran.buf = tran_buf;
258334 	for (i = 0; i < num; i++) {
259
-		chunk_size = (in_mbox_size > MLXSW_I2C_BLK_MAX) ?
260
-			     MLXSW_I2C_BLK_MAX : in_mbox_size;
335
+		chunk_size = (in_mbox_size > mlxsw_i2c->block_size) ?
336
+			     mlxsw_i2c->block_size : in_mbox_size;
261337 		write_tran.len = MLXSW_I2C_ADDR_WIDTH + chunk_size;
262338 		mlxsw_i2c_set_slave_addr(tran_buf, off);
263339 		memcpy(&tran_buf[MLXSW_I2C_ADDR_BUF_SIZE], in_mbox +
264
-		       MLXSW_I2C_BLK_MAX * i, chunk_size);
340
+		       mlxsw_i2c->block_size * i, chunk_size);
265341 
266342 		j = 0;
267343 		end = jiffies + timeout;
....@@ -275,9 +351,10 @@
275351 			 (j++ < MLXSW_I2C_RETRY));
276352 
277353 		if (err != 1) {
278
-			if (!err)
354
+			if (!err) {
279355 				err = -EIO;
280
-			return err;
356
+				goto mlxsw_i2c_write_exit;
357
+			}
281358 		}
282359 
283360 		off += chunk_size;
....@@ -288,30 +365,33 @@
288365 	err = mlxsw_i2c_write_cmd(client, mlxsw_i2c, 0);
289366 	if (err) {
290367 		dev_err(&client->dev, "Could not start transaction");
291
-		return -EIO;
368
+		err = -EIO;
369
+		goto mlxsw_i2c_write_exit;
292370 	}
293371 
294372 	/* Wait until go bit is cleared. */
295373 	err = mlxsw_i2c_wait_go_bit(client, mlxsw_i2c, p_status);
296374 	if (err) {
297375 		dev_err(&client->dev, "HW semaphore is not released");
298
-		return err;
376
+		goto mlxsw_i2c_write_exit;
299377 	}
300378 
301379 	/* Validate transaction completion status. */
302380 	if (*p_status) {
303381 		dev_err(&client->dev, "Bad transaction completion status %x\n",
304382 			*p_status);
305
-		return -EIO;
383
+		err = -EIO;
306384 	}
307385 
308
-	return 0;
386
+mlxsw_i2c_write_exit:
387
+	kfree(tran_buf);
388
+	return err;
309389 }
310390 
311391 /* Routine executes I2C command. */
312392 static int
313
-mlxsw_i2c_cmd(struct device *dev, size_t in_mbox_size, u8 *in_mbox,
314
-	      size_t out_mbox_size, u8 *out_mbox, u8 *status)
393
+mlxsw_i2c_cmd(struct device *dev, u16 opcode, u32 in_mod, size_t in_mbox_size,
394
+	      u8 *in_mbox, size_t out_mbox_size, u8 *out_mbox, u8 *status)
315395 {
316396 	struct i2c_client *client = to_i2c_client(dev);
317397 	struct mlxsw_i2c *mlxsw_i2c = i2c_get_clientdata(client);
....@@ -326,31 +406,47 @@
326406 
327407 	WARN_ON(in_mbox_size % sizeof(u32) || out_mbox_size % sizeof(u32));
328408 
329
-	reg_size = mlxsw_i2c_get_reg_size(in_mbox);
330
-	num = reg_size / MLXSW_I2C_BLK_MAX;
331
-	if (reg_size % MLXSW_I2C_BLK_MAX)
332
-		num++;
409
+	if (in_mbox) {
410
+		reg_size = mlxsw_i2c_get_reg_size(in_mbox);
411
+		num = reg_size / mlxsw_i2c->block_size;
412
+		if (reg_size % mlxsw_i2c->block_size)
413
+			num++;
333414 
334
-	if (mutex_lock_interruptible(&mlxsw_i2c->cmd.lock) < 0) {
335
-		dev_err(&client->dev, "Could not acquire lock");
336
-		return -EINVAL;
337
-	}
415
+		if (mutex_lock_interruptible(&mlxsw_i2c->cmd.lock) < 0) {
416
+			dev_err(&client->dev, "Could not acquire lock");
417
+			return -EINVAL;
418
+		}
338419 
339
-	err = mlxsw_i2c_write(dev, reg_size, in_mbox, num, status);
340
-	if (err)
341
-		goto cmd_fail;
420
+		err = mlxsw_i2c_write(dev, reg_size, in_mbox, num, status);
421
+		if (err)
422
+			goto cmd_fail;
342423 
343
-	/* No out mailbox is case of write transaction. */
344
-	if (!out_mbox) {
345
-		mutex_unlock(&mlxsw_i2c->cmd.lock);
346
-		return 0;
424
+		/* No out mailbox is case of write transaction. */
425
+		if (!out_mbox) {
426
+			mutex_unlock(&mlxsw_i2c->cmd.lock);
427
+			return 0;
428
+		}
429
+	} else {
430
+		/* No input mailbox is case of initialization query command. */
431
+		reg_size = MLXSW_I2C_MAX_DATA_SIZE;
432
+		num = DIV_ROUND_UP(reg_size, mlxsw_i2c->block_size);
433
+
434
+		if (mutex_lock_interruptible(&mlxsw_i2c->cmd.lock) < 0) {
435
+			dev_err(&client->dev, "Could not acquire lock");
436
+			return -EINVAL;
437
+		}
438
+
439
+		err = mlxsw_i2c_write_init_cmd(client, mlxsw_i2c, opcode,
440
+					       in_mod);
441
+		if (err)
442
+			goto cmd_fail;
347443 	}
348444 
349445 	/* Send read transaction to get output mailbox content. */
350446 	read_tran[1].buf = out_mbox;
351447 	for (i = 0; i < num; i++) {
352
-		chunk_size = (reg_size > MLXSW_I2C_BLK_MAX) ?
353
-			     MLXSW_I2C_BLK_MAX : reg_size;
448
+		chunk_size = (reg_size > mlxsw_i2c->block_size) ?
449
+			     mlxsw_i2c->block_size : reg_size;
354450 		read_tran[1].len = chunk_size;
355451 		mlxsw_i2c_set_slave_addr(tran_buf, off);
356452 
....@@ -395,8 +491,8 @@
395491 {
396492 	struct mlxsw_i2c *mlxsw_i2c = bus_priv;
397493 
398
-	return mlxsw_i2c_cmd(mlxsw_i2c->dev, in_mbox_size, in_mbox,
399
-			     out_mbox_size, out_mbox, status);
494
+	return mlxsw_i2c_cmd(mlxsw_i2c->dev, opcode, in_mod, in_mbox_size,
495
+			     in_mbox, out_mbox_size, out_mbox, status);
400496 }
401497 
402498 static bool mlxsw_i2c_skb_transmit_busy(void *bus_priv,
....@@ -414,13 +510,34 @@
414510 static int
415511 mlxsw_i2c_init(void *bus_priv, struct mlxsw_core *mlxsw_core,
416512 	       const struct mlxsw_config_profile *profile,
417
-	       struct mlxsw_res *resources)
513
+	       struct mlxsw_res *res)
418514 {
419515 	struct mlxsw_i2c *mlxsw_i2c = bus_priv;
516
+	char *mbox;
517
+	int err;
420518 
421519 	mlxsw_i2c->core = mlxsw_core;
422520 
423
-	return 0;
521
+	mbox = mlxsw_cmd_mbox_alloc();
522
+	if (!mbox)
523
+		return -ENOMEM;
524
+
525
+	err = mlxsw_cmd_query_fw(mlxsw_core, mbox);
526
+	if (err)
527
+		goto mbox_put;
528
+
529
+	mlxsw_i2c->bus_info.fw_rev.major =
530
+		mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox);
531
+	mlxsw_i2c->bus_info.fw_rev.minor =
532
+		mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox);
533
+	mlxsw_i2c->bus_info.fw_rev.subminor =
534
+		mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox);
535
+
536
+	err = mlxsw_core_resources_query(mlxsw_core, mbox, res);
537
+
538
+mbox_put:
539
+	mlxsw_cmd_mbox_free(mbox);
540
+	return err;
424541 }
425542 
426543 static void mlxsw_i2c_fini(void *bus_priv)
....@@ -442,6 +559,7 @@
442559 static int mlxsw_i2c_probe(struct i2c_client *client,
443560 			   const struct i2c_device_id *id)
444561 {
562
+	const struct i2c_adapter_quirks *quirks = client->adapter->quirks;
445563 	struct mlxsw_i2c *mlxsw_i2c;
446564 	u8 status;
447565 	int err;
....@@ -449,6 +567,22 @@
449567 	mlxsw_i2c = devm_kzalloc(&client->dev, sizeof(*mlxsw_i2c), GFP_KERNEL);
450568 	if (!mlxsw_i2c)
451569 		return -ENOMEM;
570
+
571
+	if (quirks) {
572
+		if ((quirks->max_read_len &&
573
+		     quirks->max_read_len < MLXSW_I2C_BLK_DEF) ||
574
+		    (quirks->max_write_len &&
575
+		     quirks->max_write_len < MLXSW_I2C_BLK_DEF)) {
576
+			dev_err(&client->dev, "Insufficient transaction buffer length\n");
577
+			return -EOPNOTSUPP;
578
+		}
579
+
580
+		mlxsw_i2c->block_size = min_t(u16, MLXSW_I2C_BLK_MAX,
581
+					      min_t(u16, quirks->max_read_len,
582
+						    quirks->max_write_len));
583
+	} else {
584
+		mlxsw_i2c->block_size = MLXSW_I2C_BLK_DEF;
585
+	}
452586 
453587 	i2c_set_clientdata(client, mlxsw_i2c);
454588 	mutex_init(&mlxsw_i2c->cmd.lock);
....@@ -503,11 +637,12 @@
503637 	mlxsw_i2c->bus_info.device_kind = id->name;
504638 	mlxsw_i2c->bus_info.device_name = client->name;
505639 	mlxsw_i2c->bus_info.dev = &client->dev;
640
+	mlxsw_i2c->bus_info.low_frequency = true;
506641 	mlxsw_i2c->dev = &client->dev;
507642 
508643 	err = mlxsw_core_bus_device_register(&mlxsw_i2c->bus_info,
509644 					     &mlxsw_i2c_bus, mlxsw_i2c, false,
510
-					     NULL);
645
+					     NULL, NULL);
511646 	if (err) {
512647 		dev_err(&client->dev, "Fail to register core bus\n");
513648 		return err;
....@@ -516,6 +651,7 @@
516651 	return 0;
517652 
518653 errout:
654
+	mutex_destroy(&mlxsw_i2c->cmd.lock);
519655 	i2c_set_clientdata(client, NULL);
520656 
521657 	return err;