.. | .. |
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210 | 210 | * @hw: pointer to the HW structure. |
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211 | 211 | * @module_pointer: module pointer location in words from the NVM beginning |
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212 | 212 | * @offset: offset in words from module start |
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213 | | - * @words: number of words to write |
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214 | | - * @data: buffer with words to write to the Shadow RAM |
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| 213 | + * @words: number of words to read |
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| 214 | + * @data: buffer with words to read to the Shadow RAM |
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215 | 215 | * @last_command: tells the AdminQ that this is the last command |
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216 | 216 | * |
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217 | | - * Writes a 16 bit words buffer to the Shadow RAM using the admin command. |
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| 217 | + * Reads a 16 bit words buffer to the Shadow RAM using the admin command. |
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218 | 218 | **/ |
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219 | 219 | static i40e_status i40e_read_nvm_aq(struct i40e_hw *hw, |
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220 | 220 | u8 module_pointer, u32 offset, |
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.. | .. |
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234 | 234 | */ |
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235 | 235 | if ((offset + words) > hw->nvm.sr_size) |
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236 | 236 | i40e_debug(hw, I40E_DEBUG_NVM, |
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237 | | - "NVM write error: offset %d beyond Shadow RAM limit %d\n", |
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| 237 | + "NVM read error: offset %d beyond Shadow RAM limit %d\n", |
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238 | 238 | (offset + words), hw->nvm.sr_size); |
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239 | 239 | else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS) |
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240 | | - /* We can write only up to 4KB (one sector), in one AQ write */ |
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| 240 | + /* We can read only up to 4KB (one sector), in one AQ write */ |
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241 | 241 | i40e_debug(hw, I40E_DEBUG_NVM, |
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242 | | - "NVM write fail error: tried to write %d words, limit is %d.\n", |
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| 242 | + "NVM read fail error: tried to read %d words, limit is %d.\n", |
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243 | 243 | words, I40E_SR_SECTOR_SIZE_IN_WORDS); |
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244 | 244 | else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS) |
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245 | 245 | != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS)) |
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246 | | - /* A single write cannot spread over two sectors */ |
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| 246 | + /* A single read cannot spread over two sectors */ |
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247 | 247 | i40e_debug(hw, I40E_DEBUG_NVM, |
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248 | | - "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n", |
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| 248 | + "NVM read error: cannot spread over two sectors in a single read offset=%d words=%d\n", |
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249 | 249 | offset, words); |
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250 | 250 | else |
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251 | 251 | ret_code = i40e_aq_read_nvm(hw, module_pointer, |
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.. | .. |
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319 | 319 | i40e_release_nvm(hw); |
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320 | 320 | |
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321 | 321 | return ret_code; |
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| 322 | +} |
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| 323 | + |
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| 324 | +/** |
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| 325 | + * i40e_read_nvm_module_data - Reads NVM Buffer to specified memory location |
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| 326 | + * @hw: Pointer to the HW structure |
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| 327 | + * @module_ptr: Pointer to module in words with respect to NVM beginning |
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| 328 | + * @module_offset: Offset in words from module start |
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| 329 | + * @data_offset: Offset in words from reading data area start |
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| 330 | + * @words_data_size: Words to read from NVM |
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| 331 | + * @data_ptr: Pointer to memory location where resulting buffer will be stored |
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| 332 | + **/ |
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| 333 | +enum i40e_status_code i40e_read_nvm_module_data(struct i40e_hw *hw, |
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| 334 | + u8 module_ptr, |
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| 335 | + u16 module_offset, |
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| 336 | + u16 data_offset, |
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| 337 | + u16 words_data_size, |
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| 338 | + u16 *data_ptr) |
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| 339 | +{ |
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| 340 | + i40e_status status; |
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| 341 | + u16 specific_ptr = 0; |
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| 342 | + u16 ptr_value = 0; |
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| 343 | + u32 offset = 0; |
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| 344 | + |
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| 345 | + if (module_ptr != 0) { |
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| 346 | + status = i40e_read_nvm_word(hw, module_ptr, &ptr_value); |
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| 347 | + if (status) { |
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| 348 | + i40e_debug(hw, I40E_DEBUG_ALL, |
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| 349 | + "Reading nvm word failed.Error code: %d.\n", |
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| 350 | + status); |
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| 351 | + return I40E_ERR_NVM; |
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| 352 | + } |
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| 353 | + } |
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| 354 | +#define I40E_NVM_INVALID_PTR_VAL 0x7FFF |
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| 355 | +#define I40E_NVM_INVALID_VAL 0xFFFF |
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| 356 | + |
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| 357 | + /* Pointer not initialized */ |
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| 358 | + if (ptr_value == I40E_NVM_INVALID_PTR_VAL || |
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| 359 | + ptr_value == I40E_NVM_INVALID_VAL) { |
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| 360 | + i40e_debug(hw, I40E_DEBUG_ALL, "Pointer not initialized.\n"); |
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| 361 | + return I40E_ERR_BAD_PTR; |
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| 362 | + } |
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| 363 | + |
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| 364 | + /* Check whether the module is in SR mapped area or outside */ |
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| 365 | + if (ptr_value & I40E_PTR_TYPE) { |
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| 366 | + /* Pointer points outside of the Shared RAM mapped area */ |
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| 367 | + i40e_debug(hw, I40E_DEBUG_ALL, |
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| 368 | + "Reading nvm data failed. Pointer points outside of the Shared RAM mapped area.\n"); |
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| 369 | + |
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| 370 | + return I40E_ERR_PARAM; |
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| 371 | + } else { |
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| 372 | + /* Read from the Shadow RAM */ |
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| 373 | + |
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| 374 | + status = i40e_read_nvm_word(hw, ptr_value + module_offset, |
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| 375 | + &specific_ptr); |
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| 376 | + if (status) { |
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| 377 | + i40e_debug(hw, I40E_DEBUG_ALL, |
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| 378 | + "Reading nvm word failed.Error code: %d.\n", |
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| 379 | + status); |
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| 380 | + return I40E_ERR_NVM; |
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| 381 | + } |
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| 382 | + |
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| 383 | + offset = ptr_value + module_offset + specific_ptr + |
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| 384 | + data_offset; |
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| 385 | + |
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| 386 | + status = i40e_read_nvm_buffer(hw, offset, &words_data_size, |
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| 387 | + data_ptr); |
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| 388 | + if (status) { |
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| 389 | + i40e_debug(hw, I40E_DEBUG_ALL, |
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| 390 | + "Reading nvm buffer failed.Error code: %d.\n", |
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| 391 | + status); |
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| 392 | + } |
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| 393 | + } |
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| 394 | + |
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| 395 | + return status; |
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322 | 396 | } |
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323 | 397 | |
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324 | 398 | /** |
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.. | .. |
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427 | 501 | return i40e_read_nvm_buffer_aq(hw, offset, words, data); |
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428 | 502 | |
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429 | 503 | return i40e_read_nvm_buffer_srctl(hw, offset, words, data); |
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| 504 | +} |
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| 505 | + |
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| 506 | +/** |
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| 507 | + * i40e_read_nvm_buffer - Reads Shadow RAM buffer and acquire lock if necessary |
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| 508 | + * @hw: pointer to the HW structure |
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| 509 | + * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). |
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| 510 | + * @words: (in) number of words to read; (out) number of words actually read |
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| 511 | + * @data: words read from the Shadow RAM |
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| 512 | + * |
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| 513 | + * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd() |
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| 514 | + * method. The buffer read is preceded by the NVM ownership take |
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| 515 | + * and followed by the release. |
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| 516 | + **/ |
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| 517 | +i40e_status i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset, |
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| 518 | + u16 *words, u16 *data) |
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| 519 | +{ |
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| 520 | + i40e_status ret_code = 0; |
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| 521 | + |
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| 522 | + if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) { |
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| 523 | + ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); |
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| 524 | + if (!ret_code) { |
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| 525 | + ret_code = i40e_read_nvm_buffer_aq(hw, offset, words, |
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| 526 | + data); |
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| 527 | + i40e_release_nvm(hw); |
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| 528 | + } |
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| 529 | + } else { |
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| 530 | + ret_code = i40e_read_nvm_buffer_srctl(hw, offset, words, data); |
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| 531 | + } |
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| 532 | + |
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| 533 | + return ret_code; |
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430 | 534 | } |
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431 | 535 | |
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432 | 536 | /** |
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.. | .. |
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578 | 682 | __le16 le_sum; |
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579 | 683 | |
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580 | 684 | ret_code = i40e_calc_nvm_checksum(hw, &checksum); |
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581 | | - if (!ret_code) { |
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582 | | - le_sum = cpu_to_le16(checksum); |
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| 685 | + le_sum = cpu_to_le16(checksum); |
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| 686 | + if (!ret_code) |
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583 | 687 | ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD, |
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584 | 688 | 1, &le_sum, true); |
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585 | | - } |
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586 | 689 | |
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587 | 690 | return ret_code; |
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588 | 691 | } |
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