add wifi6 8852be driver

hc

2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da

 kernel/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
..
..
@@ -8,6 +8,7 @@
8
8
 #include "hnae3.h"
9
9
 
10
10
 #define HCLGEVF_CMDQ_TX_TIMEOUT		30000
11
+#define HCLGEVF_CMDQ_CLEAR_WAIT_TIME	200
11
12
 #define HCLGEVF_CMDQ_RX_INVLD_B		0
12
13
 #define HCLGEVF_CMDQ_RX_OUTVLD_B	1
13
14
 
..
..
@@ -46,9 +47,17 @@
46
47
 
47
48
 enum hclgevf_cmd_return_status {
48
49
 	HCLGEVF_CMD_EXEC_SUCCESS	= 0,
49
-	HCLGEVF_CMD_NO_AUTH	= 1,
50
-	HCLGEVF_CMD_NOT_EXEC	= 2,
51
-	HCLGEVF_CMD_QUEUE_FULL	= 3,
50
+	HCLGEVF_CMD_NO_AUTH		= 1,
51
+	HCLGEVF_CMD_NOT_SUPPORTED	= 2,
52
+	HCLGEVF_CMD_QUEUE_FULL		= 3,
53
+	HCLGEVF_CMD_NEXT_ERR		= 4,
54
+	HCLGEVF_CMD_UNEXE_ERR		= 5,
55
+	HCLGEVF_CMD_PARA_ERR		= 6,
56
+	HCLGEVF_CMD_RESULT_ERR		= 7,
57
+	HCLGEVF_CMD_TIMEOUT		= 8,
58
+	HCLGEVF_CMD_HILINK_ERR		= 9,
59
+	HCLGEVF_CMD_QUEUE_ILLEGAL	= 10,
60
+	HCLGEVF_CMD_INVALID		= 11,
52
61
 };
53
62
 
54
63
 enum hclgevf_cmd_status {
..
..
@@ -83,12 +92,17 @@
83
92
 	/* Generic command */
84
93
 	HCLGEVF_OPC_QUERY_FW_VER	= 0x0001,
85
94
 	HCLGEVF_OPC_QUERY_VF_RSRC	= 0x0024,
95
+	HCLGEVF_OPC_QUERY_DEV_SPECS	= 0x0050,
96
+
86
97
 	/* TQP command */
87
98
 	HCLGEVF_OPC_QUERY_TX_STATUS	= 0x0B03,
88
99
 	HCLGEVF_OPC_QUERY_RX_STATUS	= 0x0B13,
89
100
 	HCLGEVF_OPC_CFG_COM_TQP_QUEUE	= 0x0B20,
101
+	/* GRO command */
102
+	HCLGEVF_OPC_GRO_GENERIC_CONFIG  = 0x0C10,
90
103
 	/* RSS cmd */
91
104
 	HCLGEVF_OPC_RSS_GENERIC_CONFIG	= 0x0D01,
105
+	HCLGEVF_OPC_RSS_INPUT_TUPLE     = 0x0D02,
92
106
 	HCLGEVF_OPC_RSS_INDIR_TABLE	= 0x0D07,
93
107
 	HCLGEVF_OPC_RSS_TC_MODE		= 0x0D08,
94
108
 	/* Mailbox cmd */
..
..
@@ -130,9 +144,26 @@
130
144
 	u8 resv;
131
145
 };
132
146
 
147
+enum HCLGEVF_CAP_BITS {
148
+	HCLGEVF_CAP_UDP_GSO_B,
149
+	HCLGEVF_CAP_QB_B,
150
+	HCLGEVF_CAP_FD_FORWARD_TC_B,
151
+	HCLGEVF_CAP_PTP_B,
152
+	HCLGEVF_CAP_INT_QL_B,
153
+	HCLGEVF_CAP_SIMPLE_BD_B,
154
+	HCLGEVF_CAP_TX_PUSH_B,
155
+	HCLGEVF_CAP_PHY_IMP_B,
156
+	HCLGEVF_CAP_TQP_TXRX_INDEP_B,
157
+	HCLGEVF_CAP_HW_PAD_B,
158
+	HCLGEVF_CAP_STASH_B,
159
+};
160
+
161
+#define HCLGEVF_QUERY_CAP_LENGTH		3
133
162
 struct hclgevf_query_version_cmd {
134
163
 	__le32 firmware;
135
-	__le32 firmware_rsv[5];
164
+	__le32 hardware;
165
+	__le32 rsv;
166
+	__le32 caps[HCLGEVF_QUERY_CAP_LENGTH]; /* capabilities of device */
136
167
 };
137
168
 
138
169
 #define HCLGEVF_MSIX_OFT_ROCEE_S       0
..
..
@@ -148,7 +179,14 @@
148
179
 	__le16 rsv[7];
149
180
 };
150
181
 
151
-#define HCLGEVF_RSS_HASH_KEY_OFFSET	4
182
+#define HCLGEVF_GRO_EN_B               0
183
+struct hclgevf_cfg_gro_status_cmd {
184
+	u8 gro_en;
185
+	u8 rsv[23];
186
+};
187
+
188
+#define HCLGEVF_RSS_DEFAULT_OUTPORT_B	4
189
+#define HCLGEVF_RSS_HASH_KEY_OFFSET_B	4
152
190
 #define HCLGEVF_RSS_HASH_KEY_NUM	16
153
191
 struct hclgevf_rss_config_cmd {
154
192
 	u8 hash_config;
..
..
@@ -159,11 +197,11 @@
159
197
 struct hclgevf_rss_input_tuple_cmd {
160
198
 	u8 ipv4_tcp_en;
161
199
 	u8 ipv4_udp_en;
162
-	u8 ipv4_stcp_en;
200
+	u8 ipv4_sctp_en;
163
201
 	u8 ipv4_fragment_en;
164
202
 	u8 ipv6_tcp_en;
165
203
 	u8 ipv6_udp_en;
166
-	u8 ipv6_stcp_en;
204
+	u8 ipv6_sctp_en;
167
205
 	u8 ipv6_fragment_en;
168
206
 	u8 rsv[16];
169
207
 };
..
..
@@ -226,11 +264,27 @@
226
264
 #define HCLGEVF_NIC_CRQ_DEPTH_REG	0x27020
227
265
 #define HCLGEVF_NIC_CRQ_TAIL_REG	0x27024
228
266
 #define HCLGEVF_NIC_CRQ_HEAD_REG	0x27028
229
-#define HCLGEVF_NIC_CMQ_EN_B		16
230
-#define HCLGEVF_NIC_CMQ_ENABLE		BIT(HCLGEVF_NIC_CMQ_EN_B)
267
+
268
+/* this bit indicates that the driver is ready for hardware reset */
269
+#define HCLGEVF_NIC_SW_RST_RDY_B	16
270
+#define HCLGEVF_NIC_SW_RST_RDY		BIT(HCLGEVF_NIC_SW_RST_RDY_B)
271
+
231
272
 #define HCLGEVF_NIC_CMQ_DESC_NUM	1024
232
273
 #define HCLGEVF_NIC_CMQ_DESC_NUM_S	3
233
274
 #define HCLGEVF_NIC_CMDQ_INT_SRC_REG	0x27100
275
+
276
+#define HCLGEVF_QUERY_DEV_SPECS_BD_NUM		4
277
+
278
+struct hclgevf_dev_specs_0_cmd {
279
+	__le32 rsv0;
280
+	__le32 mac_entry_num;
281
+	__le32 mng_entry_num;
282
+	__le16 rss_ind_tbl_size;
283
+	__le16 rss_key_size;
284
+	__le16 int_ql_max;
285
+	u8 max_non_tso_bd_num;
286
+	u8 rsv1[5];
287
+};
234
288
 
235
289
 static inline void hclgevf_write_reg(void __iomem *base, u32 reg, u32 value)
236
290
 {
..
..
@@ -254,6 +308,7 @@
254
308
 
255
309
 int hclgevf_cmd_init(struct hclgevf_dev *hdev);
256
310
 void hclgevf_cmd_uninit(struct hclgevf_dev *hdev);
311
+int hclgevf_cmd_queue_init(struct hclgevf_dev *hdev);
257
312
 
258
313
 int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclgevf_desc *desc, int num);
259
314
 void hclgevf_cmd_setup_basic_desc(struct hclgevf_desc *desc,