add wifi6 8852be driver

hc

2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da

 kernel/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c
..
..
@@ -3,18 +3,11 @@
3
3
 
4
4
 #include <linux/etherdevice.h>
5
5
 #include <linux/kernel.h>
6
+#include <linux/marvell_phy.h>
6
7
 
7
8
 #include "hclge_cmd.h"
8
9
 #include "hclge_main.h"
9
10
 #include "hclge_mdio.h"
10
-
11
-#define HCLGE_PHY_SUPPORTED_FEATURES	(SUPPORTED_Autoneg | \
12
-					 SUPPORTED_TP | \
13
-					 SUPPORTED_Pause | \
14
-					 SUPPORTED_Asym_Pause | \
15
-					 PHY_10BT_FEATURES | \
16
-					 PHY_100BT_FEATURES | \
17
-					 PHY_1000BT_FEATURES)
18
11
 
19
12
 enum hclge_mdio_c22_op_seq {
20
13
 	HCLGE_MDIO_C22_WRITE = 1,
..
..
@@ -62,9 +55,9 @@
62
55
 	mdio_cmd = (struct hclge_mdio_cfg_cmd *)desc.data;
63
56
 
64
57
 	hnae3_set_field(mdio_cmd->phyid, HCLGE_MDIO_PHYID_M,
65
-			HCLGE_MDIO_PHYID_S, phyid);
58
+			HCLGE_MDIO_PHYID_S, (u32)phyid);
66
59
 	hnae3_set_field(mdio_cmd->phyad, HCLGE_MDIO_PHYREG_M,
67
-			HCLGE_MDIO_PHYREG_S, regnum);
60
+			HCLGE_MDIO_PHYREG_S, (u32)regnum);
68
61
 
69
62
 	hnae3_set_bit(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_START_B, 1);
70
63
 	hnae3_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_ST_M,
..
..
@@ -100,9 +93,9 @@
100
93
 	mdio_cmd = (struct hclge_mdio_cfg_cmd *)desc.data;
101
94
 
102
95
 	hnae3_set_field(mdio_cmd->phyid, HCLGE_MDIO_PHYID_M,
103
-			HCLGE_MDIO_PHYID_S, phyid);
96
+			HCLGE_MDIO_PHYID_S, (u32)phyid);
104
97
 	hnae3_set_field(mdio_cmd->phyad, HCLGE_MDIO_PHYREG_M,
105
-			HCLGE_MDIO_PHYREG_S, regnum);
98
+			HCLGE_MDIO_PHYREG_S, (u32)regnum);
106
99
 
107
100
 	hnae3_set_bit(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_START_B, 1);
108
101
 	hnae3_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_ST_M,
..
..
@@ -129,13 +122,19 @@
129
122
 
130
123
 int hclge_mac_mdio_config(struct hclge_dev *hdev)
131
124
 {
125
+#define PHY_INEXISTENT	255
126
+
132
127
 	struct hclge_mac *mac = &hdev->hw.mac;
133
128
 	struct phy_device *phydev;
134
129
 	struct mii_bus *mdio_bus;
135
130
 	int ret;
136
131
 
137
-	if (hdev->hw.mac.phy_addr >= PHY_MAX_ADDR) {
138
-		dev_err(&hdev->pdev->dev, "phy_addr(%d) is too large.\n",
132
+	if (hdev->hw.mac.phy_addr == PHY_INEXISTENT) {
133
+		dev_info(&hdev->pdev->dev,
134
+			 "no phy device is connected to mdio bus\n");
135
+		return 0;
136
+	} else if (hdev->hw.mac.phy_addr >= PHY_MAX_ADDR) {
137
+		dev_err(&hdev->pdev->dev, "phy_addr(%u) is too large.\n",
139
138
 			hdev->hw.mac.phy_addr);
140
139
 		return -EINVAL;
141
140
 	}
..
..
@@ -156,7 +155,7 @@
156
155
 	ret = mdiobus_register(mdio_bus);
157
156
 	if (ret) {
158
157
 		dev_err(mdio_bus->parent,
159
-			"Failed to register MDIO bus ret = %#x\n", ret);
158
+			"failed to register MDIO bus, ret = %d\n", ret);
160
159
 		return ret;
161
160
 	}
162
161
 
..
..
@@ -181,6 +180,10 @@
181
180
 	int duplex, speed;
182
181
 	int ret;
183
182
 
183
+	/* When phy link down, do nothing */
184
+	if (netdev->phydev->link == 0)
185
+		return;
186
+
184
187
 	speed = netdev->phydev->speed;
185
188
 	duplex = netdev->phydev->duplex;
186
189
 
..
..
@@ -193,16 +196,21 @@
193
196
 		netdev_err(netdev, "failed to configure flow control.\n");
194
197
 }
195
198
 
196
-int hclge_mac_connect_phy(struct hclge_dev *hdev)
199
+int hclge_mac_connect_phy(struct hnae3_handle *handle)
197
200
 {
201
+	struct hclge_vport *vport = hclge_get_vport(handle);
202
+	struct hclge_dev *hdev = vport->back;
198
203
 	struct net_device *netdev = hdev->vport[0].nic.netdev;
199
204
 	struct phy_device *phydev = hdev->hw.mac.phydev;
205
+	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
200
206
 	int ret;
201
207
 
202
208
 	if (!phydev)
203
209
 		return 0;
204
210
 
205
-	phydev->supported &= ~SUPPORTED_FIBRE;
211
+	linkmode_clear_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported);
212
+
213
+	phydev->dev_flags |= MARVELL_PHY_LED0_LINK_LED1_ACTIVE;
206
214
 
207
215
 	ret = phy_connect_direct(netdev, phydev,
208
216
 				 hclge_mac_adjust_link,
..
..
@@ -212,14 +220,26 @@
212
220
 		return ret;
213
221
 	}
214
222
 
215
-	phydev->supported &= HCLGE_PHY_SUPPORTED_FEATURES;
216
-	phydev->advertising = phydev->supported;
223
+	linkmode_copy(mask, hdev->hw.mac.supported);
224
+	linkmode_and(phydev->supported, phydev->supported, mask);
225
+	linkmode_copy(phydev->advertising, phydev->supported);
226
+
227
+	/* supported flag is Pause and Asym Pause, but default advertising
228
+	 * should be rx on, tx on, so need clear Asym Pause in advertising
229
+	 * flag
230
+	 */
231
+	linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
232
+			   phydev->advertising);
233
+
234
+	phy_attached_info(phydev);
217
235
 
218
236
 	return 0;
219
237
 }
220
238
 
221
-void hclge_mac_disconnect_phy(struct hclge_dev *hdev)
239
+void hclge_mac_disconnect_phy(struct hnae3_handle *handle)
222
240
 {
241
+	struct hclge_vport *vport = hclge_get_vport(handle);
242
+	struct hclge_dev *hdev = vport->back;
223
243
 	struct phy_device *phydev = hdev->hw.mac.phydev;
224
244
 
225
245
 	if (!phydev)