~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,4 +1,4 @@
1		-// SPDX-License-Identifier: GPL-2.0+
	1	+/* SPDX-License-Identifier: GPL-2.0+ */
2	2	// Copyright (c) 2016-2017 Hisilicon Limited.
3	3
4	4	#ifndef __HCLGE_MAIN_H
..	..	@@ -7,12 +7,18 @@
7	7	#include <linux/types.h>
8	8	#include <linux/phy.h>
9	9	#include <linux/if_vlan.h>
	10	+#include <linux/kfifo.h>
10	11
11	12	#include "hclge_cmd.h"
12	13	#include "hnae3.h"
13	14
14	15	#define HCLGE_MOD_VERSION "1.0"
15	16	#define HCLGE_DRIVER_NAME "hclge"
	17	+
	18	+#define HCLGE_MAX_PF_NUM 8
	19	+
	20	+#define HCLGE_RD_FIRST_STATS_NUM 2
	21	+#define HCLGE_RD_OTHER_STATS_NUM 4
16	22
17	23	#define HCLGE_INVALID_VPORT 0xffff
18	24
..	..	@@ -25,6 +31,62 @@
25	31
26	32	#define HCLGE_VECTOR_REG_OFFSET 0x4
27	33	#define HCLGE_VECTOR_VF_OFFSET 0x100000
	34	+
	35	+#define HCLGE_CMDQ_TX_ADDR_L_REG 0x27000
	36	+#define HCLGE_CMDQ_TX_ADDR_H_REG 0x27004
	37	+#define HCLGE_CMDQ_TX_DEPTH_REG 0x27008
	38	+#define HCLGE_CMDQ_TX_TAIL_REG 0x27010
	39	+#define HCLGE_CMDQ_TX_HEAD_REG 0x27014
	40	+#define HCLGE_CMDQ_RX_ADDR_L_REG 0x27018
	41	+#define HCLGE_CMDQ_RX_ADDR_H_REG 0x2701C
	42	+#define HCLGE_CMDQ_RX_DEPTH_REG 0x27020
	43	+#define HCLGE_CMDQ_RX_TAIL_REG 0x27024
	44	+#define HCLGE_CMDQ_RX_HEAD_REG 0x27028
	45	+#define HCLGE_CMDQ_INTR_SRC_REG 0x27100
	46	+#define HCLGE_CMDQ_INTR_STS_REG 0x27104
	47	+#define HCLGE_CMDQ_INTR_EN_REG 0x27108
	48	+#define HCLGE_CMDQ_INTR_GEN_REG 0x2710C
	49	+
	50	+/* bar registers for common func */
	51	+#define HCLGE_VECTOR0_OTER_EN_REG 0x20600
	52	+#define HCLGE_RAS_OTHER_STS_REG 0x20B00
	53	+#define HCLGE_FUNC_RESET_STS_REG 0x20C00
	54	+#define HCLGE_GRO_EN_REG 0x28000
	55	+
	56	+/* bar registers for rcb */
	57	+#define HCLGE_RING_RX_ADDR_L_REG 0x80000
	58	+#define HCLGE_RING_RX_ADDR_H_REG 0x80004
	59	+#define HCLGE_RING_RX_BD_NUM_REG 0x80008
	60	+#define HCLGE_RING_RX_BD_LENGTH_REG 0x8000C
	61	+#define HCLGE_RING_RX_MERGE_EN_REG 0x80014
	62	+#define HCLGE_RING_RX_TAIL_REG 0x80018
	63	+#define HCLGE_RING_RX_HEAD_REG 0x8001C
	64	+#define HCLGE_RING_RX_FBD_NUM_REG 0x80020
	65	+#define HCLGE_RING_RX_OFFSET_REG 0x80024
	66	+#define HCLGE_RING_RX_FBD_OFFSET_REG 0x80028
	67	+#define HCLGE_RING_RX_STASH_REG 0x80030
	68	+#define HCLGE_RING_RX_BD_ERR_REG 0x80034
	69	+#define HCLGE_RING_TX_ADDR_L_REG 0x80040
	70	+#define HCLGE_RING_TX_ADDR_H_REG 0x80044
	71	+#define HCLGE_RING_TX_BD_NUM_REG 0x80048
	72	+#define HCLGE_RING_TX_PRIORITY_REG 0x8004C
	73	+#define HCLGE_RING_TX_TC_REG 0x80050
	74	+#define HCLGE_RING_TX_MERGE_EN_REG 0x80054
	75	+#define HCLGE_RING_TX_TAIL_REG 0x80058
	76	+#define HCLGE_RING_TX_HEAD_REG 0x8005C
	77	+#define HCLGE_RING_TX_FBD_NUM_REG 0x80060
	78	+#define HCLGE_RING_TX_OFFSET_REG 0x80064
	79	+#define HCLGE_RING_TX_EBD_NUM_REG 0x80068
	80	+#define HCLGE_RING_TX_EBD_OFFSET_REG 0x80070
	81	+#define HCLGE_RING_TX_BD_ERR_REG 0x80074
	82	+#define HCLGE_RING_EN_REG 0x80090
	83	+
	84	+/* bar registers for tqp interrupt */
	85	+#define HCLGE_TQP_INTR_CTRL_REG 0x20000
	86	+#define HCLGE_TQP_INTR_GL0_REG 0x20100
	87	+#define HCLGE_TQP_INTR_GL1_REG 0x20200
	88	+#define HCLGE_TQP_INTR_GL2_REG 0x20300
	89	+#define HCLGE_TQP_INTR_RL_REG 0x20900
28	90
29	91	#define HCLGE_RSS_IND_TBL_SIZE 512
30	92	#define HCLGE_RSS_SET_BITMAP_MSK GENMASK(15, 0)
..	..	@@ -43,6 +105,8 @@
43	105	#define HCLGE_D_IP_BIT BIT(2)
44	106	#define HCLGE_S_IP_BIT BIT(3)
45	107	#define HCLGE_V_TAG_BIT BIT(4)
	108	+#define HCLGE_RSS_INPUT_TUPLE_SCTP_NO_PORT \
	109	+ (HCLGE_D_IP_BIT \| HCLGE_S_IP_BIT \| HCLGE_V_TAG_BIT)
46	110
47	111	#define HCLGE_RSS_TC_SIZE_0 1
48	112	#define HCLGE_RSS_TC_SIZE_1 2
..	..	@@ -53,9 +117,11 @@
53	117	#define HCLGE_RSS_TC_SIZE_6 64
54	118	#define HCLGE_RSS_TC_SIZE_7 128
55	119
56		-#define HCLGE_MTA_TBL_SIZE 4096
	120	+#define HCLGE_UMV_TBL_SIZE 3072
	121	+#define HCLGE_DEFAULT_UMV_SPACE_PER_PF \
	122	+ (HCLGE_UMV_TBL_SIZE / HCLGE_MAX_PF_NUM)
57	123
58		-#define HCLGE_TQP_RESET_TRY_TIMES 10
	124	+#define HCLGE_TQP_RESET_TRY_TIMES 200
59	125
60	126	#define HCLGE_PHY_PAGE_MDIX 0
61	127	#define HCLGE_PHY_PAGE_COPPER 0
..	..	@@ -75,16 +141,35 @@
75	141	#define HCLGE_PHY_MDIX_STATUS_B 6
76	142	#define HCLGE_PHY_SPEED_DUP_RESOLVE_B 11
77	143
	144	+#define HCLGE_GET_DFX_REG_TYPE_CNT 4
	145	+
78	146	/* Factor used to calculate offset and bitmap of VF num */
79	147	#define HCLGE_VF_NUM_PER_CMD 64
80		-#define HCLGE_VF_NUM_PER_BYTE 8
	148	+
	149	+enum HLCGE_PORT_TYPE {
	150	+ HOST_PORT,
	151	+ NETWORK_PORT
	152	+};
	153	+
	154	+#define PF_VPORT_ID 0
	155	+
	156	+#define HCLGE_PF_ID_S 0
	157	+#define HCLGE_PF_ID_M GENMASK(2, 0)
	158	+#define HCLGE_VF_ID_S 3
	159	+#define HCLGE_VF_ID_M GENMASK(10, 3)
	160	+#define HCLGE_PORT_TYPE_B 11
	161	+#define HCLGE_NETWORK_PORT_ID_S 0
	162	+#define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0)
81	163
82	164	/* Reset related Registers */
	165	+#define HCLGE_PF_OTHER_INT_REG 0x20600
83	166	#define HCLGE_MISC_RESET_STS_REG 0x20700
84	167	#define HCLGE_MISC_VECTOR_INT_STS 0x20800
85	168	#define HCLGE_GLOBAL_RESET_REG 0x20A00
86	169	#define HCLGE_GLOBAL_RESET_BIT 0
87	170	#define HCLGE_CORE_RESET_BIT 1
	171	+#define HCLGE_IMP_RESET_BIT 2
	172	+#define HCLGE_RESET_INT_M GENMASK(7, 5)
88	173	#define HCLGE_FUN_RST_ING 0x20C00
89	174	#define HCLGE_FUN_RST_ING_B 0
90	175
..	..	@@ -98,8 +183,12 @@
98	183	/* CMDQ register bits for RX event(=MBX event) */
99	184	#define HCLGE_VECTOR0_RX_CMDQ_INT_B 1
100	185
	186	+#define HCLGE_VECTOR0_IMP_RESET_INT_B 1
	187	+#define HCLGE_VECTOR0_IMP_CMDQ_ERR_B 4U
	188	+#define HCLGE_VECTOR0_IMP_RD_POISON_B 5U
	189	+
101	190	#define HCLGE_MAC_DEFAULT_FRAME \
102		- (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN + ETH_DATA_LEN)
	191	+ (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN)
103	192	#define HCLGE_MAC_MIN_FRAME 64
104	193	#define HCLGE_MAC_MAX_FRAME 9728
105	194
..	..	@@ -108,32 +197,43 @@
108	197	#define HCLGE_SUPPORT_25G_BIT BIT(2)
109	198	#define HCLGE_SUPPORT_50G_BIT BIT(3)
110	199	#define HCLGE_SUPPORT_100G_BIT BIT(4)
	200	+/* to be compatible with exsit board */
	201	+#define HCLGE_SUPPORT_40G_BIT BIT(5)
	202	+#define HCLGE_SUPPORT_100M_BIT BIT(6)
	203	+#define HCLGE_SUPPORT_10M_BIT BIT(7)
	204	+#define HCLGE_SUPPORT_200G_BIT BIT(8)
	205	+#define HCLGE_SUPPORT_GE \
	206	+ (HCLGE_SUPPORT_1G_BIT \| HCLGE_SUPPORT_100M_BIT \| HCLGE_SUPPORT_10M_BIT)
111	207
112	208	enum HCLGE_DEV_STATE {
113	209	HCLGE_STATE_REINITING,
114	210	HCLGE_STATE_DOWN,
115	211	HCLGE_STATE_DISABLED,
116	212	HCLGE_STATE_REMOVING,
	213	+ HCLGE_STATE_NIC_REGISTERED,
	214	+ HCLGE_STATE_ROCE_REGISTERED,
117	215	HCLGE_STATE_SERVICE_INITED,
118		- HCLGE_STATE_SERVICE_SCHED,
119	216	HCLGE_STATE_RST_SERVICE_SCHED,
120	217	HCLGE_STATE_RST_HANDLING,
121	218	HCLGE_STATE_MBX_SERVICE_SCHED,
122	219	HCLGE_STATE_MBX_HANDLING,
123	220	HCLGE_STATE_STATISTICS_UPDATING,
124	221	HCLGE_STATE_CMD_DISABLE,
	222	+ HCLGE_STATE_LINK_UPDATING,
	223	+ HCLGE_STATE_PROMISC_CHANGED,
	224	+ HCLGE_STATE_RST_FAIL,
125	225	HCLGE_STATE_MAX
126	226	};
127	227
128	228	enum hclge_evt_cause {
129	229	HCLGE_VECTOR0_EVENT_RST,
130	230	HCLGE_VECTOR0_EVENT_MBX,
	231	+ HCLGE_VECTOR0_EVENT_ERR,
131	232	HCLGE_VECTOR0_EVENT_OTHER,
132	233	};
133	234
134		-#define HCLGE_MPF_ENBALE 1
135		-
136	235	enum HCLGE_MAC_SPEED {
	236	+ HCLGE_MAC_SPEED_UNKNOWN = 0, /* unknown */
137	237	HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */
138	238	HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */
139	239	HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */
..	..	@@ -141,7 +241,8 @@
141	241	HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */
142	242	HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */
143	243	HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */
144		- HCLGE_MAC_SPEED_100G = 100000 /* 100000 Mbps = 100 Gbps */
	244	+ HCLGE_MAC_SPEED_100G = 100000, /* 100000 Mbps = 100 Gbps */
	245	+ HCLGE_MAC_SPEED_200G = 200000 /* 200000 Mbps = 200 Gbps */
145	246	};
146	247
147	248	enum HCLGE_MAC_DUPLEX {
..	..	@@ -149,22 +250,27 @@
149	250	HCLGE_MAC_FULL
150	251	};
151	252
152		-enum hclge_mta_dmac_sel_type {
153		- HCLGE_MAC_ADDR_47_36,
154		- HCLGE_MAC_ADDR_46_35,
155		- HCLGE_MAC_ADDR_45_34,
156		- HCLGE_MAC_ADDR_44_33,
157		-};
	253	+#define QUERY_SFP_SPEED 0
	254	+#define QUERY_ACTIVE_SPEED 1
158	255
159	256	struct hclge_mac {
	257	+ u8 mac_id;
160	258	u8 phy_addr;
161	259	u8 flag;
162		- u8 media_type;
	260	+ u8 media_type; /* port media type, e.g. fibre/copper/backplane */
163	261	u8 mac_addr[ETH_ALEN];
164	262	u8 autoneg;
165	263	u8 duplex;
	264	+ u8 support_autoneg;
	265	+ u8 speed_type; /* 0: sfp speed, 1: active speed */
166	266	u32 speed;
167		- int link; /* store the link status of mac & phy (if phy exit)*/
	267	+ u32 max_speed;
	268	+ u32 speed_ability; /* speed ability supported by current media */
	269	+ u32 module_type; /* sub media type, e.g. kr/cr/sr/lr */
	270	+ u32 fec_mode; /* active fec mode */
	271	+ u32 user_fec_mode;
	272	+ u32 fec_ability;
	273	+ int link; /* store the link status of mac & phy (if phy exists) */
168	274	struct phy_device *phydev;
169	275	struct mii_bus *mdio_bus;
170	276	phy_interface_t phy_if;
..	..	@@ -208,6 +314,16 @@
208	314	HCLGE_FC_DEFAULT
209	315	};
210	316
	317	+enum hclge_link_fail_code {
	318	+ HCLGE_LF_NORMAL,
	319	+ HCLGE_LF_REF_CLOCK_LOST,
	320	+ HCLGE_LF_XSFP_TX_DISABLE,
	321	+ HCLGE_LF_XSFP_ABSENT,
	322	+};
	323	+
	324	+#define HCLGE_LINK_STATUS_DOWN 0
	325	+#define HCLGE_LINK_STATUS_UP 1
	326	+
211	327	#define HCLGE_PG_NUM 4
212	328	#define HCLGE_SCH_MODE_SP 0
213	329	#define HCLGE_SCH_MODE_DWRR 1
..	..	@@ -237,7 +353,8 @@
237	353	u8 mac_addr[ETH_ALEN];
238	354	u8 default_speed;
239	355	u32 numa_node_map;
240		- u8 speed_ability;
	356	+ u16 speed_ability;
	357	+ u16 umv_space;
241	358	};
242	359
243	360	struct hclge_tm_info {
..	..	@@ -255,109 +372,6 @@
255	372	struct hclge_comm_stats_str {
256	373	char desc[ETH_GSTRING_LEN];
257	374	unsigned long offset;
258		-};
259		-
260		-/* all 64bit stats, opcode id: 0x0030 */
261		-struct hclge_64_bit_stats {
262		- /* query_igu_stat */
263		- u64 igu_rx_oversize_pkt;
264		- u64 igu_rx_undersize_pkt;
265		- u64 igu_rx_out_all_pkt;
266		- u64 igu_rx_uni_pkt;
267		- u64 igu_rx_multi_pkt;
268		- u64 igu_rx_broad_pkt;
269		- u64 rsv0;
270		-
271		- /* query_egu_stat */
272		- u64 egu_tx_out_all_pkt;
273		- u64 egu_tx_uni_pkt;
274		- u64 egu_tx_multi_pkt;
275		- u64 egu_tx_broad_pkt;
276		-
277		- /* ssu_ppp packet stats */
278		- u64 ssu_ppp_mac_key_num;
279		- u64 ssu_ppp_host_key_num;
280		- u64 ppp_ssu_mac_rlt_num;
281		- u64 ppp_ssu_host_rlt_num;
282		-
283		- /* ssu_tx_in_out_dfx_stats */
284		- u64 ssu_tx_in_num;
285		- u64 ssu_tx_out_num;
286		- /* ssu_rx_in_out_dfx_stats */
287		- u64 ssu_rx_in_num;
288		- u64 ssu_rx_out_num;
289		-};
290		-
291		-/* all 32bit stats, opcode id: 0x0031 */
292		-struct hclge_32_bit_stats {
293		- u64 igu_rx_err_pkt;
294		- u64 igu_rx_no_eof_pkt;
295		- u64 igu_rx_no_sof_pkt;
296		- u64 egu_tx_1588_pkt;
297		- u64 egu_tx_err_pkt;
298		- u64 ssu_full_drop_num;
299		- u64 ssu_part_drop_num;
300		- u64 ppp_key_drop_num;
301		- u64 ppp_rlt_drop_num;
302		- u64 ssu_key_drop_num;
303		- u64 pkt_curr_buf_cnt;
304		- u64 qcn_fb_rcv_cnt;
305		- u64 qcn_fb_drop_cnt;
306		- u64 qcn_fb_invaild_cnt;
307		- u64 rsv0;
308		- u64 rx_packet_tc0_in_cnt;
309		- u64 rx_packet_tc1_in_cnt;
310		- u64 rx_packet_tc2_in_cnt;
311		- u64 rx_packet_tc3_in_cnt;
312		- u64 rx_packet_tc4_in_cnt;
313		- u64 rx_packet_tc5_in_cnt;
314		- u64 rx_packet_tc6_in_cnt;
315		- u64 rx_packet_tc7_in_cnt;
316		- u64 rx_packet_tc0_out_cnt;
317		- u64 rx_packet_tc1_out_cnt;
318		- u64 rx_packet_tc2_out_cnt;
319		- u64 rx_packet_tc3_out_cnt;
320		- u64 rx_packet_tc4_out_cnt;
321		- u64 rx_packet_tc5_out_cnt;
322		- u64 rx_packet_tc6_out_cnt;
323		- u64 rx_packet_tc7_out_cnt;
324		-
325		- /* Tx packet level statistics */
326		- u64 tx_packet_tc0_in_cnt;
327		- u64 tx_packet_tc1_in_cnt;
328		- u64 tx_packet_tc2_in_cnt;
329		- u64 tx_packet_tc3_in_cnt;
330		- u64 tx_packet_tc4_in_cnt;
331		- u64 tx_packet_tc5_in_cnt;
332		- u64 tx_packet_tc6_in_cnt;
333		- u64 tx_packet_tc7_in_cnt;
334		- u64 tx_packet_tc0_out_cnt;
335		- u64 tx_packet_tc1_out_cnt;
336		- u64 tx_packet_tc2_out_cnt;
337		- u64 tx_packet_tc3_out_cnt;
338		- u64 tx_packet_tc4_out_cnt;
339		- u64 tx_packet_tc5_out_cnt;
340		- u64 tx_packet_tc6_out_cnt;
341		- u64 tx_packet_tc7_out_cnt;
342		-
343		- /* packet buffer statistics */
344		- u64 pkt_curr_buf_tc0_cnt;
345		- u64 pkt_curr_buf_tc1_cnt;
346		- u64 pkt_curr_buf_tc2_cnt;
347		- u64 pkt_curr_buf_tc3_cnt;
348		- u64 pkt_curr_buf_tc4_cnt;
349		- u64 pkt_curr_buf_tc5_cnt;
350		- u64 pkt_curr_buf_tc6_cnt;
351		- u64 pkt_curr_buf_tc7_cnt;
352		-
353		- u64 mb_uncopy_num;
354		- u64 lo_pri_unicast_rlt_drop_num;
355		- u64 hi_pri_multicast_rlt_drop_num;
356		- u64 lo_pri_multicast_rlt_drop_num;
357		- u64 rx_oq_drop_pkt_cnt;
358		- u64 tx_oq_drop_pkt_cnt;
359		- u64 nic_l2_err_drop_pkt_cnt;
360		- u64 roc_l2_err_drop_pkt_cnt;
361	375	};
362	376
363	377	/* mac stats ,opcode id: 0x0032 */
..	..	@@ -446,15 +460,13 @@
446	460	u64 mac_rx_fcs_err_pkt_num;
447	461	u64 mac_rx_send_app_good_pkt_num;
448	462	u64 mac_rx_send_app_bad_pkt_num;
	463	+ u64 mac_tx_pfc_pause_pkt_num;
	464	+ u64 mac_rx_pfc_pause_pkt_num;
	465	+ u64 mac_tx_ctrl_pkt_num;
	466	+ u64 mac_rx_ctrl_pkt_num;
449	467	};
450	468
451		-#define HCLGE_STATS_TIMER_INTERVAL (60 * 5)
452		-struct hclge_hw_stats {
453		- struct hclge_mac_stats mac_stats;
454		- struct hclge_64_bit_stats all_64_bit_stats;
455		- struct hclge_32_bit_stats all_32_bit_stats;
456		- u32 stats_timer;
457		-};
	469	+#define HCLGE_STATS_TIMER_INTERVAL 300UL
458	470
459	471	struct hclge_vlan_type_cfg {
460	472	u16 rx_ot_fst_vlan_type;
..	..	@@ -465,18 +477,266 @@
465	477	u16 tx_in_vlan_type;
466	478	};
467	479
	480	+enum HCLGE_FD_MODE {
	481	+ HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1,
	482	+ HCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2,
	483	+ HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1,
	484	+ HCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2,
	485	+};
	486	+
	487	+enum HCLGE_FD_KEY_TYPE {
	488	+ HCLGE_FD_KEY_BASE_ON_PTYPE,
	489	+ HCLGE_FD_KEY_BASE_ON_TUPLE,
	490	+};
	491	+
	492	+enum HCLGE_FD_STAGE {
	493	+ HCLGE_FD_STAGE_1,
	494	+ HCLGE_FD_STAGE_2,
	495	+ MAX_STAGE_NUM,
	496	+};
	497	+
	498	+/* OUTER_XXX indicates tuples in tunnel header of tunnel packet
	499	+ * INNER_XXX indicate tuples in tunneled header of tunnel packet or
	500	+ * tuples of non-tunnel packet
	501	+ */
	502	+enum HCLGE_FD_TUPLE {
	503	+ OUTER_DST_MAC,
	504	+ OUTER_SRC_MAC,
	505	+ OUTER_VLAN_TAG_FST,
	506	+ OUTER_VLAN_TAG_SEC,
	507	+ OUTER_ETH_TYPE,
	508	+ OUTER_L2_RSV,
	509	+ OUTER_IP_TOS,
	510	+ OUTER_IP_PROTO,
	511	+ OUTER_SRC_IP,
	512	+ OUTER_DST_IP,
	513	+ OUTER_L3_RSV,
	514	+ OUTER_SRC_PORT,
	515	+ OUTER_DST_PORT,
	516	+ OUTER_L4_RSV,
	517	+ OUTER_TUN_VNI,
	518	+ OUTER_TUN_FLOW_ID,
	519	+ INNER_DST_MAC,
	520	+ INNER_SRC_MAC,
	521	+ INNER_VLAN_TAG_FST,
	522	+ INNER_VLAN_TAG_SEC,
	523	+ INNER_ETH_TYPE,
	524	+ INNER_L2_RSV,
	525	+ INNER_IP_TOS,
	526	+ INNER_IP_PROTO,
	527	+ INNER_SRC_IP,
	528	+ INNER_DST_IP,
	529	+ INNER_L3_RSV,
	530	+ INNER_SRC_PORT,
	531	+ INNER_DST_PORT,
	532	+ INNER_L4_RSV,
	533	+ MAX_TUPLE,
	534	+};
	535	+
	536	+enum HCLGE_FD_META_DATA {
	537	+ PACKET_TYPE_ID,
	538	+ IP_FRAGEMENT,
	539	+ ROCE_TYPE,
	540	+ NEXT_KEY,
	541	+ VLAN_NUMBER,
	542	+ SRC_VPORT,
	543	+ DST_VPORT,
	544	+ TUNNEL_PACKET,
	545	+ MAX_META_DATA,
	546	+};
	547	+
	548	+struct key_info {
	549	+ u8 key_type;
	550	+ u8 key_length; /* use bit as unit */
	551	+};
	552	+
	553	+#define MAX_KEY_LENGTH 400
	554	+#define MAX_KEY_DWORDS DIV_ROUND_UP(MAX_KEY_LENGTH / 8, 4)
	555	+#define MAX_KEY_BYTES (MAX_KEY_DWORDS * 4)
	556	+#define MAX_META_DATA_LENGTH 32
	557	+
	558	+/* assigned by firmware, the real filter number for each pf may be less */
	559	+#define MAX_FD_FILTER_NUM 4096
	560	+#define HCLGE_ARFS_EXPIRE_INTERVAL 5UL
	561	+
	562	+enum HCLGE_FD_ACTIVE_RULE_TYPE {
	563	+ HCLGE_FD_RULE_NONE,
	564	+ HCLGE_FD_ARFS_ACTIVE,
	565	+ HCLGE_FD_EP_ACTIVE,
	566	+};
	567	+
	568	+enum HCLGE_FD_PACKET_TYPE {
	569	+ NIC_PACKET,
	570	+ ROCE_PACKET,
	571	+};
	572	+
	573	+enum HCLGE_FD_ACTION {
	574	+ HCLGE_FD_ACTION_ACCEPT_PACKET,
	575	+ HCLGE_FD_ACTION_DROP_PACKET,
	576	+};
	577	+
	578	+struct hclge_fd_key_cfg {
	579	+ u8 key_sel;
	580	+ u8 inner_sipv6_word_en;
	581	+ u8 inner_dipv6_word_en;
	582	+ u8 outer_sipv6_word_en;
	583	+ u8 outer_dipv6_word_en;
	584	+ u32 tuple_active;
	585	+ u32 meta_data_active;
	586	+};
	587	+
	588	+struct hclge_fd_cfg {
	589	+ u8 fd_mode;
	590	+ u16 max_key_length; /* use bit as unit */
	591	+ u32 rule_num[MAX_STAGE_NUM]; /* rule entry number */
	592	+ u16 cnt_num[MAX_STAGE_NUM]; /* rule hit counter number */
	593	+ struct hclge_fd_key_cfg key_cfg[MAX_STAGE_NUM];
	594	+};
	595	+
	596	+#define IPV4_INDEX 3
	597	+#define IPV6_SIZE 4
	598	+struct hclge_fd_rule_tuples {
	599	+ u8 src_mac[ETH_ALEN];
	600	+ u8 dst_mac[ETH_ALEN];
	601	+ /* Be compatible for ip address of both ipv4 and ipv6.
	602	+ * For ipv4 address, we store it in src/dst_ip[3].
	603	+ */
	604	+ u32 src_ip[IPV6_SIZE];
	605	+ u32 dst_ip[IPV6_SIZE];
	606	+ u16 src_port;
	607	+ u16 dst_port;
	608	+ u16 vlan_tag1;
	609	+ u16 ether_proto;
	610	+ u8 ip_tos;
	611	+ u8 ip_proto;
	612	+};
	613	+
	614	+struct hclge_fd_rule {
	615	+ struct hlist_node rule_node;
	616	+ struct hclge_fd_rule_tuples tuples;
	617	+ struct hclge_fd_rule_tuples tuples_mask;
	618	+ u32 unused_tuple;
	619	+ u32 flow_type;
	620	+ u8 action;
	621	+ u16 vf_id;
	622	+ u16 queue_id;
	623	+ u16 location;
	624	+ u16 flow_id; /* only used for arfs */
	625	+ enum HCLGE_FD_ACTIVE_RULE_TYPE rule_type;
	626	+};
	627	+
	628	+struct hclge_fd_ad_data {
	629	+ u16 ad_id;
	630	+ u8 drop_packet;
	631	+ u8 forward_to_direct_queue;
	632	+ u16 queue_id;
	633	+ u8 use_counter;
	634	+ u8 counter_id;
	635	+ u8 use_next_stage;
	636	+ u8 write_rule_id_to_bd;
	637	+ u8 next_input_key;
	638	+ u16 rule_id;
	639	+};
	640	+
	641	+enum HCLGE_MAC_NODE_STATE {
	642	+ HCLGE_MAC_TO_ADD,
	643	+ HCLGE_MAC_TO_DEL,
	644	+ HCLGE_MAC_ACTIVE
	645	+};
	646	+
	647	+struct hclge_mac_node {
	648	+ struct list_head node;
	649	+ enum HCLGE_MAC_NODE_STATE state;
	650	+ u8 mac_addr[ETH_ALEN];
	651	+};
	652	+
	653	+enum HCLGE_MAC_ADDR_TYPE {
	654	+ HCLGE_MAC_ADDR_UC,
	655	+ HCLGE_MAC_ADDR_MC
	656	+};
	657	+
	658	+struct hclge_vport_vlan_cfg {
	659	+ struct list_head node;
	660	+ int hd_tbl_status;
	661	+ u16 vlan_id;
	662	+};
	663	+
	664	+struct hclge_rst_stats {
	665	+ u32 reset_done_cnt; /* the number of reset has completed */
	666	+ u32 hw_reset_done_cnt; /* the number of HW reset has completed */
	667	+ u32 pf_rst_cnt; /* the number of PF reset */
	668	+ u32 flr_rst_cnt; /* the number of FLR */
	669	+ u32 global_rst_cnt; /* the number of GLOBAL */
	670	+ u32 imp_rst_cnt; /* the number of IMP reset */
	671	+ u32 reset_cnt; /* the number of reset */
	672	+ u32 reset_fail_cnt; /* the number of reset fail */
	673	+};
	674	+
	675	+/* time and register status when mac tunnel interruption occur */
	676	+struct hclge_mac_tnl_stats {
	677	+ u64 time;
	678	+ u32 status;
	679	+};
	680	+
	681	+#define HCLGE_RESET_INTERVAL (10 * HZ)
	682	+#define HCLGE_WAIT_RESET_DONE 100
	683	+
	684	+#pragma pack(1)
	685	+struct hclge_vf_vlan_cfg {
	686	+ u8 mbx_cmd;
	687	+ u8 subcode;
	688	+ u8 is_kill;
	689	+ u16 vlan;
	690	+ u16 proto;
	691	+};
	692	+
	693	+#pragma pack()
	694	+
	695	+/* For each bit of TCAM entry, it uses a pair of 'x' and
	696	+ * 'y' to indicate which value to match, like below:
	697	+ * ----------------------------------
	698	+ * \| bit x \| bit y \| search value \|
	699	+ * ----------------------------------
	700	+ * \| 0 \| 0 \| always hit \|
	701	+ * ----------------------------------
	702	+ * \| 1 \| 0 \| match '0' \|
	703	+ * ----------------------------------
	704	+ * \| 0 \| 1 \| match '1' \|
	705	+ * ----------------------------------
	706	+ * \| 1 \| 1 \| invalid \|
	707	+ * ----------------------------------
	708	+ * Then for input key(k) and mask(v), we can calculate the value by
	709	+ * the formulae:
	710	+ * x = (~k) & v
	711	+ * y = (k ^ ~v) & k
	712	+ */
	713	+#define calc_x(x, k, v) ((x) = (~(k) & (v)))
	714	+#define calc_y(y, k, v) \
	715	+ do { \
	716	+ const typeof(k) _k_ = (k); \
	717	+ const typeof(v) _v_ = (v); \
	718	+ (y) = (_k_ ^ ~_v_) & (_k_); \
	719	+ } while (0)
	720	+
	721	+#define HCLGE_MAC_TNL_LOG_SIZE 8
468	722	#define HCLGE_VPORT_NUM 256
469	723	struct hclge_dev {
470	724	struct pci_dev *pdev;
471	725	struct hnae3_ae_dev *ae_dev;
472	726	struct hclge_hw hw;
473	727	struct hclge_misc_vector misc_vector;
474		- struct hclge_hw_stats hw_stats;
	728	+ struct hclge_mac_stats mac_stats;
475	729	unsigned long state;
	730	+ unsigned long flr_state;
	731	+ unsigned long last_reset_time;
476	732
477	733	enum hnae3_reset_type reset_type;
	734	+ enum hnae3_reset_type reset_level;
	735	+ unsigned long default_reset_request;
478	736	unsigned long reset_request; /* reset has been requested */
479	737	unsigned long reset_pending; /* client rst is pending to be served */
	738	+ struct hclge_rst_stats rst_stats;
	739	+ struct semaphore reset_sem; /* protect reset process */
480	740	u32 fw_version;
481	741	u16 num_vmdq_vport; /* Num vmdq vport this PF has set up */
482	742	u16 num_tqps; /* Num task queue pairs of this PF */
..	..	@@ -490,10 +750,11 @@
490	750	u16 num_alloc_vport; /* Num vports this driver supports */
491	751	u32 numa_node_mask;
492	752	u16 rx_buf_len;
493		- u16 num_desc;
	753	+ u16 num_tx_desc; /* desc num of per tx queue */
	754	+ u16 num_rx_desc; /* desc num of per rx queue */
494	755	u8 hw_tc_map;
495		- u8 tc_num_last_time;
496	756	enum hclge_fc_mode fc_mode_last_time;
	757	+ u8 support_sfp_query;
497	758
498	759	#define HCLGE_FLAG_TC_BASE_SCH_MODE 1
499	760	#define HCLGE_FLAG_VNET_BASE_SCH_MODE 2
..	..	@@ -512,21 +773,14 @@
512	773	u32 base_msi_vector;
513	774	u16 *vector_status;
514	775	int *vector_irq;
	776	+ u16 num_nic_msi; /* Num of nic vectors for this PF */
515	777	u16 num_roce_msi; /* Num of roce vectors for this PF */
516	778	int roce_base_vector;
517	779
518		- u16 pending_udp_bitmap;
519		-
520		- u16 rx_itr_default;
521		- u16 tx_itr_default;
522		-
523		- u16 adminq_work_limit; /* Num of admin receive queue desc to process */
524	780	unsigned long service_timer_period;
525	781	unsigned long service_timer_previous;
526		- struct timer_list service_timer;
527		- struct work_struct service_task;
528		- struct work_struct rst_service_task;
529		- struct work_struct mbx_service_task;
	782	+ struct timer_list reset_timer;
	783	+ struct delayed_work service_task;
530	784
531	785	bool cur_promisc;
532	786	int num_alloc_vfs; /* Actual number of VFs allocated */
..	..	@@ -546,14 +800,44 @@
546	800	u32 flag;
547	801
548	802	u32 pkt_buf_size; /* Total pf buf size for tx/rx */
549		- u32 mps; /* Max packet size */
	803	+ u32 tx_buf_size; /* Tx buffer size for each TC */
	804	+ u32 dv_buf_size; /* Dv buffer size for each TC */
550	805
551		- enum hclge_mta_dmac_sel_type mta_mac_sel_type;
552		- bool enable_mta; /* Multicast filter enable */
	806	+ u32 mps; /* Max packet size */
	807	+ /* vport_lock protect resource shared by vports */
	808	+ struct mutex vport_lock;
553	809
554	810	struct hclge_vlan_type_cfg vlan_type_cfg;
555	811
556	812	unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)];
	813	+ unsigned long vf_vlan_full[BITS_TO_LONGS(HCLGE_VPORT_NUM)];
	814	+
	815	+ unsigned long vport_config_block[BITS_TO_LONGS(HCLGE_VPORT_NUM)];
	816	+
	817	+ struct hclge_fd_cfg fd_cfg;
	818	+ struct hlist_head fd_rule_list;
	819	+ spinlock_t fd_rule_lock; /* protect fd_rule_list and fd_bmap */
	820	+ u16 hclge_fd_rule_num;
	821	+ unsigned long serv_processed_cnt;
	822	+ unsigned long last_serv_processed;
	823	+ unsigned long fd_bmap[BITS_TO_LONGS(MAX_FD_FILTER_NUM)];
	824	+ enum HCLGE_FD_ACTIVE_RULE_TYPE fd_active_type;
	825	+ u8 fd_en;
	826	+
	827	+ u16 wanted_umv_size;
	828	+ /* max available unicast mac vlan space */
	829	+ u16 max_umv_size;
	830	+ /* private unicast mac vlan space, it's same for PF and its VFs */
	831	+ u16 priv_umv_size;
	832	+ /* unicast mac vlan space shared by PF and its VFs */
	833	+ u16 share_umv_size;
	834	+
	835	+ DECLARE_KFIFO(mac_tnl_log, struct hclge_mac_tnl_stats,
	836	+ HCLGE_MAC_TNL_LOG_SIZE);
	837	+
	838	+ /* affinity mask and notify for misc interrupt */
	839	+ cpumask_t affinity_mask;
	840	+ struct irq_affinity_notify affinity_notify;
557	841	};
558	842
559	843	/* VPort level vlan tag configuration for TX direction */
..	..	@@ -570,10 +854,11 @@
570	854
571	855	/* VPort level vlan tag configuration for RX direction */
572	856	struct hclge_rx_vtag_cfg {
573		- bool strip_tag1_en; /* Whether strip inner vlan tag */
574		- bool strip_tag2_en; /* Whether strip outer vlan tag */
575		- bool vlan1_vlan_prionly;/* Inner VLAN Tag up to descriptor Enable */
576		- bool vlan2_vlan_prionly;/* Outer VLAN Tag up to descriptor Enable */
	857	+ u8 rx_vlan_offload_en; /* Whether enable rx vlan offload */
	858	+ u8 strip_tag1_en; /* Whether strip inner vlan tag */
	859	+ u8 strip_tag2_en; /* Whether strip outer vlan tag */
	860	+ u8 vlan1_vlan_prionly; /* Inner VLAN Tag up to descriptor Enable */
	861	+ u8 vlan2_vlan_prionly; /* Outer VLAN Tag up to descriptor Enable */
577	862	};
578	863
579	864	struct hclge_rss_tuple_cfg {
..	..	@@ -585,6 +870,32 @@
585	870	u8 ipv6_udp_en;
586	871	u8 ipv6_sctp_en;
587	872	u8 ipv6_fragment_en;
	873	+};
	874	+
	875	+enum HCLGE_VPORT_STATE {
	876	+ HCLGE_VPORT_STATE_ALIVE,
	877	+ HCLGE_VPORT_STATE_MAC_TBL_CHANGE,
	878	+ HCLGE_VPORT_STATE_MAX
	879	+};
	880	+
	881	+struct hclge_vlan_info {
	882	+ u16 vlan_proto; /* so far support 802.1Q only */
	883	+ u16 qos;
	884	+ u16 vlan_tag;
	885	+};
	886	+
	887	+struct hclge_port_base_vlan_config {
	888	+ u16 state;
	889	+ struct hclge_vlan_info vlan_info;
	890	+};
	891	+
	892	+struct hclge_vf_info {
	893	+ int link_state;
	894	+ u8 mac[ETH_ALEN];
	895	+ u32 spoofchk;
	896	+ u32 max_tx_rate;
	897	+ u32 trusted;
	898	+ u16 promisc_enable;
588	899	};
589	900
590	901	struct hclge_vport {
..	..	@@ -603,21 +914,34 @@
603	914	u32 bw_limit; /* VSI BW Limit (0 = disabled) */
604	915	u8 dwrr;
605	916
	917	+ unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)];
	918	+ struct hclge_port_base_vlan_config port_base_vlan_cfg;
606	919	struct hclge_tx_vtag_cfg txvlan_cfg;
607	920	struct hclge_rx_vtag_cfg rxvlan_cfg;
608	921
609		- int vport_id;
	922	+ u16 used_umv_num;
	923	+
	924	+ u16 vport_id;
610	925	struct hclge_dev back; / Back reference to associated dev */
611	926	struct hnae3_handle nic;
612	927	struct hnae3_handle roce;
613	928
614		- bool accept_mta_mc; /* whether to accept mta filter multicast */
615		- unsigned long mta_shadow[BITS_TO_LONGS(HCLGE_MTA_TBL_SIZE)];
	929	+ unsigned long state;
	930	+ unsigned long last_active_jiffies;
	931	+ u32 mps; /* Max packet size */
	932	+ struct hclge_vf_info vf_info;
	933	+
	934	+ u8 overflow_promisc_flags;
	935	+ u8 last_promisc_flags;
	936	+
	937	+ spinlock_t mac_list_lock; /* protect mac address need to add/detele */
	938	+ struct list_head uc_mac_list; /* Store VF unicast table */
	939	+ struct list_head mc_mac_list; /* Store VF multicast table */
	940	+ struct list_head vlan_list; /* Store VF vlan table */
616	941	};
617	942
618		-void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
619		- bool en_mc, bool en_bc, int vport_id);
620		-
	943	+int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc,
	944	+ bool en_mc_pmc, bool en_bc_pmc);
621	945	int hclge_add_uc_addr_common(struct hclge_vport *vport,
622	946	const unsigned char *addr);
623	947	int hclge_rm_uc_addr_common(struct hclge_vport *vport,
..	..	@@ -626,15 +950,6 @@
626	950	const unsigned char *addr);
627	951	int hclge_rm_mc_addr_common(struct hclge_vport *vport,
628	952	const unsigned char *addr);
629		-
630		-int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
631		- u8 func_id,
632		- bool enable);
633		-int hclge_update_mta_status_common(struct hclge_vport *vport,
634		- unsigned long *status,
635		- u16 idx,
636		- u16 count,
637		- bool update_filter);
638	953
639	954	struct hclge_vport hclge_get_vport(struct hnae3_handle handle);
640	955	int hclge_bind_ring_with_vector(struct hclge_vport *vport,
..	..	@@ -648,6 +963,12 @@
648	963	return tqp->index;
649	964	}
650	965
	966	+static inline bool hclge_is_reset_pending(struct hclge_dev *hdev)
	967	+{
	968	+ return !!hdev->reset_pending;
	969	+}
	970	+
	971	+int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport);
651	972	int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex);
652	973	int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
653	974	u16 vlan_id, bool is_kill);
..	..	@@ -658,8 +979,39 @@
658	979	void hclge_rss_indir_init_cfg(struct hclge_dev *hdev);
659	980
660	981	void hclge_mbx_handler(struct hclge_dev *hdev);
661		-void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id);
	982	+int hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id);
662	983	void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id);
663	984	int hclge_cfg_flowctrl(struct hclge_dev *hdev);
664	985	int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id);
	986	+int hclge_vport_start(struct hclge_vport *vport);
	987	+void hclge_vport_stop(struct hclge_vport *vport);
	988	+int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu);
	989	+int hclge_dbg_run_cmd(struct hnae3_handle handle, const char cmd_buf);
	990	+u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id);
	991	+int hclge_notify_client(struct hclge_dev *hdev,
	992	+ enum hnae3_reset_notify_type type);
	993	+int hclge_update_mac_list(struct hclge_vport *vport,
	994	+ enum HCLGE_MAC_NODE_STATE state,
	995	+ enum HCLGE_MAC_ADDR_TYPE mac_type,
	996	+ const unsigned char *addr);
	997	+int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport,
	998	+ const u8 old_addr, const u8 new_addr);
	999	+void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list,
	1000	+ enum HCLGE_MAC_ADDR_TYPE mac_type);
	1001	+void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list);
	1002	+void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev);
	1003	+void hclge_restore_mac_table_common(struct hclge_vport *vport);
	1004	+void hclge_restore_vport_vlan_table(struct hclge_vport *vport);
	1005	+int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state,
	1006	+ struct hclge_vlan_info *vlan_info);
	1007	+int hclge_push_vf_port_base_vlan_info(struct hclge_vport *vport, u8 vfid,
	1008	+ u16 state, u16 vlan_tag, u16 qos,
	1009	+ u16 vlan_proto);
	1010	+void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time);
	1011	+int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev,
	1012	+ struct hclge_desc *desc);
	1013	+void hclge_report_hw_error(struct hclge_dev *hdev,
	1014	+ enum hnae3_hw_error_type type);
	1015	+void hclge_inform_vf_promisc_info(struct hclge_vport *vport);
	1016	+void hclge_dbg_dump_rst_info(struct hclge_dev *hdev);
665	1017	#endif