forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da
kernel/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
....@@ -487,6 +487,12 @@
487487 #define ERROR_QID_M 0x1ffffU
488488 #define ERROR_QID_G(x) (((x) >> ERROR_QID_S) & ERROR_QID_M)
489489
490
+#define SGE_INT_CAUSE5_A 0x110c
491
+
492
+#define ERR_T_RXCRC_S 31
493
+#define ERR_T_RXCRC_V(x) ((x) << ERR_T_RXCRC_S)
494
+#define ERR_T_RXCRC_F ERR_T_RXCRC_V(1U)
495
+
490496 #define HP_INT_THRESH_S 28
491497 #define HP_INT_THRESH_M 0xfU
492498 #define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S)
....@@ -557,6 +563,12 @@
557563 #define AIVEC_V(x) ((x) << AIVEC_S)
558564
559565 #define PCIE_PF_CLI_A 0x44
566
+
567
+#define PCIE_PF_EXPROM_OFST_A 0x4c
568
+#define OFFSET_S 10
569
+#define OFFSET_M 0x3fffU
570
+#define OFFSET_G(x) (((x) >> OFFSET_S) & OFFSET_M)
571
+
560572 #define PCIE_INT_CAUSE_A 0x3004
561573
562574 #define UNXSPLCPLERR_S 29
....@@ -1333,6 +1345,10 @@
13331345 #define TP_DBG_LA_CONFIG_A 0x7ed4
13341346 #define TP_OUT_CONFIG_A 0x7d04
13351347 #define TP_GLOBAL_CONFIG_A 0x7d08
1348
+
1349
+#define ACTIVEFILTERCOUNTS_S 22
1350
+#define ACTIVEFILTERCOUNTS_V(x) ((x) << ACTIVEFILTERCOUNTS_S)
1351
+#define ACTIVEFILTERCOUNTS_F ACTIVEFILTERCOUNTS_V(1U)
13361352
13371353 #define TP_CMM_TCB_BASE_A 0x7d10
13381354 #define TP_CMM_MM_BASE_A 0x7d14
....@@ -3001,6 +3017,14 @@
30013017 #define REV_V(x) ((x) << REV_S)
30023018 #define REV_G(x) (((x) >> REV_S) & REV_M)
30033019
3020
+#define HASHTBLMEMCRCERR_S 27
3021
+#define HASHTBLMEMCRCERR_V(x) ((x) << HASHTBLMEMCRCERR_S)
3022
+#define HASHTBLMEMCRCERR_F HASHTBLMEMCRCERR_V(1U)
3023
+
3024
+#define CMDTIDERR_S 22
3025
+#define CMDTIDERR_V(x) ((x) << CMDTIDERR_S)
3026
+#define CMDTIDERR_F CMDTIDERR_V(1U)
3027
+
30043028 #define T6_UNKNOWNCMD_S 3
30053029 #define T6_UNKNOWNCMD_V(x) ((x) << T6_UNKNOWNCMD_S)
30063030 #define T6_UNKNOWNCMD_F T6_UNKNOWNCMD_V(1U)
....@@ -3028,6 +3052,10 @@
30283052 #define HASHTIDSIZE_M 0x3fU
30293053 #define HASHTIDSIZE_G(x) (((x) >> HASHTIDSIZE_S) & HASHTIDSIZE_M)
30303054
3055
+#define HASHTBLSIZE_S 3
3056
+#define HASHTBLSIZE_M 0x1ffffU
3057
+#define HASHTBLSIZE_G(x) (((x) >> HASHTBLSIZE_S) & HASHTBLSIZE_M)
3058
+
30313059 #define LE_DB_HASH_TID_BASE_A 0x19c30
30323060 #define LE_DB_HASH_TBL_BASE_ADDR_A 0x19c30
30333061 #define LE_DB_INT_CAUSE_A 0x19c3c