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2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da 
 kernel/drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h
....@@ -1,18 +1,6 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  *  Copyright (C) 2017 Chelsio Communications.  All rights reserved.
3
- *
4
- *  This program is free software; you can redistribute it and/or modify it
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- *  under the terms and conditions of the GNU General Public License,
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- *  version 2, as published by the Free Software Foundation.
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- *
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- *  This program is distributed in the hope it will be useful, but WITHOUT
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- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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- *  more details.
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- *
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- *  The full GNU General Public License is included in this distribution in
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- *  the file called "COPYING".
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- *
164  */
175 
186 #ifndef __CUDBG_ENTITY_H__
....@@ -94,7 +82,7 @@
9482 struct cudbg_tp_la {
9583 	u32 size;
9684 	u32 mode;
97
-	u8 data[0];
85
+	u8 data[];
9886 };
9987 
10088 static const char * const cudbg_region[] = {
....@@ -146,7 +134,7 @@
146134 
147135 struct cudbg_cim_pif_la {
148136 	int size;
149
-	u8 data[0];
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+	u8 data[];
150138 };
151139 
152140 struct cudbg_clk_info {
....@@ -315,169 +303,53 @@
315303 	u32 pbt_data[CUDBG_PBT_DATA_ENTRIES];
316304 };
317305 
306
+enum cudbg_qdesc_qtype {
307
+	CUDBG_QTYPE_UNKNOWN = 0,
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+	CUDBG_QTYPE_NIC_TXQ,
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+	CUDBG_QTYPE_NIC_RXQ,
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+	CUDBG_QTYPE_NIC_FLQ,
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+	CUDBG_QTYPE_CTRLQ,
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+	CUDBG_QTYPE_FWEVTQ,
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+	CUDBG_QTYPE_INTRQ,
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+	CUDBG_QTYPE_PTP_TXQ,
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+	CUDBG_QTYPE_OFLD_TXQ,
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+	CUDBG_QTYPE_RDMA_RXQ,
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+	CUDBG_QTYPE_RDMA_FLQ,
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+	CUDBG_QTYPE_RDMA_CIQ,
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+	CUDBG_QTYPE_ISCSI_RXQ,
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+	CUDBG_QTYPE_ISCSI_FLQ,
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+	CUDBG_QTYPE_ISCSIT_RXQ,
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+	CUDBG_QTYPE_ISCSIT_FLQ,
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+	CUDBG_QTYPE_CRYPTO_TXQ,
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+	CUDBG_QTYPE_CRYPTO_RXQ,
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+	CUDBG_QTYPE_CRYPTO_FLQ,
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+	CUDBG_QTYPE_TLS_RXQ,
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+	CUDBG_QTYPE_TLS_FLQ,
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+	CUDBG_QTYPE_ETHOFLD_TXQ,
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+	CUDBG_QTYPE_ETHOFLD_RXQ,
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+	CUDBG_QTYPE_ETHOFLD_FLQ,
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+	CUDBG_QTYPE_MAX,
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+};
333
+
334
+#define CUDBG_QDESC_REV 1
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+
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+struct cudbg_qdesc_entry {
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+	u32 data_size;
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+	u32 qtype;
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+	u32 qid;
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+	u32 desc_size;
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+	u32 num_desc;
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+	u8 data[]; /* Must be last */
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+};
344
+
345
+struct cudbg_qdesc_info {
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+	u32 qdesc_entry_size;
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+	u32 num_queues;
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+	u8 data[]; /* Must be last */
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+};
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+
318351 #define IREG_NUM_ELEM 4
319
-
320
-static const u32 t6_tp_pio_array[][IREG_NUM_ELEM] = {
321
-	{0x7e40, 0x7e44, 0x020, 28}, /* t6_tp_pio_regs_20_to_3b */
322
-	{0x7e40, 0x7e44, 0x040, 10}, /* t6_tp_pio_regs_40_to_49 */
323
-	{0x7e40, 0x7e44, 0x050, 10}, /* t6_tp_pio_regs_50_to_59 */
324
-	{0x7e40, 0x7e44, 0x060, 14}, /* t6_tp_pio_regs_60_to_6d */
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-	{0x7e40, 0x7e44, 0x06F, 1}, /* t6_tp_pio_regs_6f */
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-	{0x7e40, 0x7e44, 0x070, 6}, /* t6_tp_pio_regs_70_to_75 */
327
-	{0x7e40, 0x7e44, 0x130, 18}, /* t6_tp_pio_regs_130_to_141 */
328
-	{0x7e40, 0x7e44, 0x145, 19}, /* t6_tp_pio_regs_145_to_157 */
329
-	{0x7e40, 0x7e44, 0x160, 1}, /* t6_tp_pio_regs_160 */
330
-	{0x7e40, 0x7e44, 0x230, 25}, /* t6_tp_pio_regs_230_to_248 */
331
-	{0x7e40, 0x7e44, 0x24a, 3}, /* t6_tp_pio_regs_24c */
332
-	{0x7e40, 0x7e44, 0x8C0, 1} /* t6_tp_pio_regs_8c0 */
333
-};
334
-
335
-static const u32 t5_tp_pio_array[][IREG_NUM_ELEM] = {
336
-	{0x7e40, 0x7e44, 0x020, 28}, /* t5_tp_pio_regs_20_to_3b */
337
-	{0x7e40, 0x7e44, 0x040, 19}, /* t5_tp_pio_regs_40_to_52 */
338
-	{0x7e40, 0x7e44, 0x054, 2}, /* t5_tp_pio_regs_54_to_55 */
339
-	{0x7e40, 0x7e44, 0x060, 13}, /* t5_tp_pio_regs_60_to_6c */
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-	{0x7e40, 0x7e44, 0x06F, 1}, /* t5_tp_pio_regs_6f */
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-	{0x7e40, 0x7e44, 0x120, 4}, /* t5_tp_pio_regs_120_to_123 */
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-	{0x7e40, 0x7e44, 0x12b, 2}, /* t5_tp_pio_regs_12b_to_12c */
343
-	{0x7e40, 0x7e44, 0x12f, 21}, /* t5_tp_pio_regs_12f_to_143 */
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-	{0x7e40, 0x7e44, 0x145, 19}, /* t5_tp_pio_regs_145_to_157 */
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-	{0x7e40, 0x7e44, 0x230, 25}, /* t5_tp_pio_regs_230_to_248 */
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-	{0x7e40, 0x7e44, 0x8C0, 1} /* t5_tp_pio_regs_8c0 */
347
-};
348
-
349
-static const u32 t6_tp_tm_pio_array[][IREG_NUM_ELEM] = {
350
-	{0x7e18, 0x7e1c, 0x0, 12}
351
-};
352
-
353
-static const u32 t5_tp_tm_pio_array[][IREG_NUM_ELEM] = {
354
-	{0x7e18, 0x7e1c, 0x0, 12}
355
-};
356
-
357
-static const u32 t6_tp_mib_index_array[6][IREG_NUM_ELEM] = {
358
-	{0x7e50, 0x7e54, 0x0, 13},
359
-	{0x7e50, 0x7e54, 0x10, 6},
360
-	{0x7e50, 0x7e54, 0x18, 21},
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-	{0x7e50, 0x7e54, 0x30, 32},
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-	{0x7e50, 0x7e54, 0x50, 22},
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-	{0x7e50, 0x7e54, 0x68, 12}
364
-};
365
-
366
-static const u32 t5_tp_mib_index_array[9][IREG_NUM_ELEM] = {
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-	{0x7e50, 0x7e54, 0x0, 13},
368
-	{0x7e50, 0x7e54, 0x10, 6},
369
-	{0x7e50, 0x7e54, 0x18, 8},
370
-	{0x7e50, 0x7e54, 0x20, 13},
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-	{0x7e50, 0x7e54, 0x30, 16},
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-	{0x7e50, 0x7e54, 0x40, 16},
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-	{0x7e50, 0x7e54, 0x50, 16},
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-	{0x7e50, 0x7e54, 0x60, 6},
375
-	{0x7e50, 0x7e54, 0x68, 4}
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-};
377
-
378
-static const u32 t5_sge_dbg_index_array[2][IREG_NUM_ELEM] = {
379
-	{0x10cc, 0x10d0, 0x0, 16},
380
-	{0x10cc, 0x10d4, 0x0, 16},
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-};
382
-
383
-static const u32 t6_sge_qbase_index_array[] = {
384
-	/* 1 addr reg SGE_QBASE_INDEX and 4 data reg SGE_QBASE_MAP[0-3] */
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-	0x1250, 0x1240, 0x1244, 0x1248, 0x124c,
386
-};
387
-
388
-static const u32 t5_pcie_pdbg_array[][IREG_NUM_ELEM] = {
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-	{0x5a04, 0x5a0c, 0x00, 0x20}, /* t5_pcie_pdbg_regs_00_to_20 */
390
-	{0x5a04, 0x5a0c, 0x21, 0x20}, /* t5_pcie_pdbg_regs_21_to_40 */
391
-	{0x5a04, 0x5a0c, 0x41, 0x10}, /* t5_pcie_pdbg_regs_41_to_50 */
392
-};
393
-
394
-static const u32 t5_pcie_cdbg_array[][IREG_NUM_ELEM] = {
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-	{0x5a10, 0x5a18, 0x00, 0x20}, /* t5_pcie_cdbg_regs_00_to_20 */
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-	{0x5a10, 0x5a18, 0x21, 0x18}, /* t5_pcie_cdbg_regs_21_to_37 */
397
-};
398
-
399
-static const u32 t5_pm_rx_array[][IREG_NUM_ELEM] = {
400
-	{0x8FD0, 0x8FD4, 0x10000, 0x20}, /* t5_pm_rx_regs_10000_to_10020 */
401
-	{0x8FD0, 0x8FD4, 0x10021, 0x0D}, /* t5_pm_rx_regs_10021_to_1002c */
402
-};
403
-
404
-static const u32 t5_pm_tx_array[][IREG_NUM_ELEM] = {
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-	{0x8FF0, 0x8FF4, 0x10000, 0x20}, /* t5_pm_tx_regs_10000_to_10020 */
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-	{0x8FF0, 0x8FF4, 0x10021, 0x1D}, /* t5_pm_tx_regs_10021_to_1003c */
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-};
408352 
409353 #define CUDBG_NUM_PCIE_CONFIG_REGS 0x61
410354 
411
-static const u32 t5_pcie_config_array[][2] = {
412
-	{0x0, 0x34},
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-	{0x3c, 0x40},
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-	{0x50, 0x64},
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-	{0x70, 0x80},
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-	{0x94, 0xa0},
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-	{0xb0, 0xb8},
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-	{0xd0, 0xd4},
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-	{0x100, 0x128},
420
-	{0x140, 0x148},
421
-	{0x150, 0x164},
422
-	{0x170, 0x178},
423
-	{0x180, 0x194},
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-	{0x1a0, 0x1b8},
425
-	{0x1c0, 0x208},
426
-};
427
-
428
-static const u32 t6_ma_ireg_array[][IREG_NUM_ELEM] = {
429
-	{0x78f8, 0x78fc, 0xa000, 23}, /* t6_ma_regs_a000_to_a016 */
430
-	{0x78f8, 0x78fc, 0xa400, 30}, /* t6_ma_regs_a400_to_a41e */
431
-	{0x78f8, 0x78fc, 0xa800, 20} /* t6_ma_regs_a800_to_a813 */
432
-};
433
-
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-static const u32 t6_ma_ireg_array2[][IREG_NUM_ELEM] = {
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-	{0x78f8, 0x78fc, 0xe400, 17}, /* t6_ma_regs_e400_to_e600 */
436
-	{0x78f8, 0x78fc, 0xe640, 13} /* t6_ma_regs_e640_to_e7c0 */
437
-};
438
-
439
-static const u32 t6_up_cim_reg_array[][IREG_NUM_ELEM + 1] = {
440
-	{0x7b50, 0x7b54, 0x2000, 0x20, 0}, /* up_cim_2000_to_207c */
441
-	{0x7b50, 0x7b54, 0x2080, 0x1d, 0}, /* up_cim_2080_to_20fc */
442
-	{0x7b50, 0x7b54, 0x00, 0x20, 0}, /* up_cim_00_to_7c */
443
-	{0x7b50, 0x7b54, 0x80, 0x20, 0}, /* up_cim_80_to_fc */
444
-	{0x7b50, 0x7b54, 0x100, 0x11, 0}, /* up_cim_100_to_14c */
445
-	{0x7b50, 0x7b54, 0x200, 0x10, 0}, /* up_cim_200_to_23c */
446
-	{0x7b50, 0x7b54, 0x240, 0x2, 0}, /* up_cim_240_to_244 */
447
-	{0x7b50, 0x7b54, 0x250, 0x2, 0}, /* up_cim_250_to_254 */
448
-	{0x7b50, 0x7b54, 0x260, 0x2, 0}, /* up_cim_260_to_264 */
449
-	{0x7b50, 0x7b54, 0x270, 0x2, 0}, /* up_cim_270_to_274 */
450
-	{0x7b50, 0x7b54, 0x280, 0x20, 0}, /* up_cim_280_to_2fc */
451
-	{0x7b50, 0x7b54, 0x300, 0x20, 0}, /* up_cim_300_to_37c */
452
-	{0x7b50, 0x7b54, 0x380, 0x14, 0}, /* up_cim_380_to_3cc */
453
-	{0x7b50, 0x7b54, 0x4900, 0x4, 0x4}, /* up_cim_4900_to_4c60 */
454
-	{0x7b50, 0x7b54, 0x4904, 0x4, 0x4}, /* up_cim_4904_to_4c64 */
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-	{0x7b50, 0x7b54, 0x4908, 0x4, 0x4}, /* up_cim_4908_to_4c68 */
456
-	{0x7b50, 0x7b54, 0x4910, 0x4, 0x4}, /* up_cim_4910_to_4c70 */
457
-	{0x7b50, 0x7b54, 0x4914, 0x4, 0x4}, /* up_cim_4914_to_4c74 */
458
-	{0x7b50, 0x7b54, 0x4920, 0x10, 0x10}, /* up_cim_4920_to_4a10 */
459
-	{0x7b50, 0x7b54, 0x4924, 0x10, 0x10}, /* up_cim_4924_to_4a14 */
460
-	{0x7b50, 0x7b54, 0x4928, 0x10, 0x10}, /* up_cim_4928_to_4a18 */
461
-	{0x7b50, 0x7b54, 0x492c, 0x10, 0x10}, /* up_cim_492c_to_4a1c */
462
-};
463
-
464
-static const u32 t5_up_cim_reg_array[][IREG_NUM_ELEM + 1] = {
465
-	{0x7b50, 0x7b54, 0x2000, 0x20, 0}, /* up_cim_2000_to_207c */
466
-	{0x7b50, 0x7b54, 0x2080, 0x19, 0}, /* up_cim_2080_to_20ec */
467
-	{0x7b50, 0x7b54, 0x00, 0x20, 0}, /* up_cim_00_to_7c */
468
-	{0x7b50, 0x7b54, 0x80, 0x20, 0}, /* up_cim_80_to_fc */
469
-	{0x7b50, 0x7b54, 0x100, 0x11, 0}, /* up_cim_100_to_14c */
470
-	{0x7b50, 0x7b54, 0x200, 0x10, 0}, /* up_cim_200_to_23c */
471
-	{0x7b50, 0x7b54, 0x240, 0x2, 0}, /* up_cim_240_to_244 */
472
-	{0x7b50, 0x7b54, 0x250, 0x2, 0}, /* up_cim_250_to_254 */
473
-	{0x7b50, 0x7b54, 0x260, 0x2, 0}, /* up_cim_260_to_264 */
474
-	{0x7b50, 0x7b54, 0x270, 0x2, 0}, /* up_cim_270_to_274 */
475
-	{0x7b50, 0x7b54, 0x280, 0x20, 0}, /* up_cim_280_to_2fc */
476
-	{0x7b50, 0x7b54, 0x300, 0x20, 0}, /* up_cim_300_to_37c */
477
-	{0x7b50, 0x7b54, 0x380, 0x14, 0}, /* up_cim_380_to_3cc */
478
-};
479
-
480
-static const u32 t6_hma_ireg_array[][IREG_NUM_ELEM] = {
481
-	{0x51320, 0x51324, 0xa000, 32} /* t6_hma_regs_a000_to_a01f */
482
-};
483355 #endif /* __CUDBG_ENTITY_H__ */