add wifi6 8852be driver

hc

2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da

 kernel/drivers/mtd/nand/raw/ndfc.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  *  Overview:
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  *   Platform independent driver for NDFC (NanD Flash Controller)
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@@ -14,12 +15,6 @@
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  *  Copyright 2006 IBM
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  *  Copyright 2008 PIKA Technologies
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  *    Sean MacLennan <smaclennan@pikatech.com>
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- *
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- *  This program is free software; you can redistribute	 it and/or modify it
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- *  under  the terms of	 the GNU General  Public License as published by the
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- *  Free Software Foundation;  either version 2 of the	License, or (at your
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- *  option) any later version.
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- *
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  */
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 #include <linux/module.h>
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 #include <linux/mtd/rawnand.h>
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@@ -44,10 +39,9 @@
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39
 
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 static struct ndfc_controller ndfc_ctrl[NDFC_MAX_CS];
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-static void ndfc_select_chip(struct mtd_info *mtd, int chip)
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+static void ndfc_select_chip(struct nand_chip *nchip, int chip)
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 {
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 	uint32_t ccr;
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-	struct nand_chip *nchip = mtd_to_nand(mtd);
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 	struct ndfc_controller *ndfc = nand_get_controller_data(nchip);
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 	ccr = in_be32(ndfc->ndfcbase + NDFC_CCR);
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@@ -59,9 +53,8 @@
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 	out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
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 }
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-static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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+static void ndfc_hwcontrol(struct nand_chip *chip, int cmd, unsigned int ctrl)
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 {
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-	struct nand_chip *chip = mtd_to_nand(mtd);
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 	struct ndfc_controller *ndfc = nand_get_controller_data(chip);
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 	if (cmd == NAND_CMD_NONE)
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@@ -73,18 +66,16 @@
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 		writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_ALE);
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 }
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-static int ndfc_ready(struct mtd_info *mtd)
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+static int ndfc_ready(struct nand_chip *chip)
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 {
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-	struct nand_chip *chip = mtd_to_nand(mtd);
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 	struct ndfc_controller *ndfc = nand_get_controller_data(chip);
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 	return in_be32(ndfc->ndfcbase + NDFC_STAT) & NDFC_STAT_IS_READY;
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 }
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-static void ndfc_enable_hwecc(struct mtd_info *mtd, int mode)
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+static void ndfc_enable_hwecc(struct nand_chip *chip, int mode)
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 {
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 	uint32_t ccr;
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-	struct nand_chip *chip = mtd_to_nand(mtd);
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 	struct ndfc_controller *ndfc = nand_get_controller_data(chip);
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 	ccr = in_be32(ndfc->ndfcbase + NDFC_CCR);
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@@ -93,10 +84,9 @@
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 	wmb();
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 }
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-static int ndfc_calculate_ecc(struct mtd_info *mtd,
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+static int ndfc_calculate_ecc(struct nand_chip *chip,
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 			      const u_char *dat, u_char *ecc_code)
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 {
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-	struct nand_chip *chip = mtd_to_nand(mtd);
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 	struct ndfc_controller *ndfc = nand_get_controller_data(chip);
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 	uint32_t ecc;
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 	uint8_t *p = (uint8_t *)&ecc;
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@@ -118,9 +108,8 @@
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  * functions. No further checking, as nand_base will always read/write
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  * page aligned.
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  */
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-static void ndfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
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+static void ndfc_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
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 {
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-	struct nand_chip *chip = mtd_to_nand(mtd);
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 	struct ndfc_controller *ndfc = nand_get_controller_data(chip);
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 	uint32_t *p = (uint32_t *) buf;
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@@ -128,9 +117,8 @@
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 		*p++ = in_be32(ndfc->ndfcbase + NDFC_DATA);
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 }
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-static void ndfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
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+static void ndfc_write_buf(struct nand_chip *chip, const uint8_t *buf, int len)
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 {
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-	struct nand_chip *chip = mtd_to_nand(mtd);
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 	struct ndfc_controller *ndfc = nand_get_controller_data(chip);
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 	uint32_t *p = (uint32_t *) buf;
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@@ -149,19 +137,19 @@
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 	struct mtd_info *mtd = nand_to_mtd(chip);
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 	int ret;
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-	chip->IO_ADDR_R = ndfc->ndfcbase + NDFC_DATA;
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-	chip->IO_ADDR_W = ndfc->ndfcbase + NDFC_DATA;
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-	chip->cmd_ctrl = ndfc_hwcontrol;
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-	chip->dev_ready = ndfc_ready;
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-	chip->select_chip = ndfc_select_chip;
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-	chip->chip_delay = 50;
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+	chip->legacy.IO_ADDR_R = ndfc->ndfcbase + NDFC_DATA;
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+	chip->legacy.IO_ADDR_W = ndfc->ndfcbase + NDFC_DATA;
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+	chip->legacy.cmd_ctrl = ndfc_hwcontrol;
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+	chip->legacy.dev_ready = ndfc_ready;
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+	chip->legacy.select_chip = ndfc_select_chip;
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+	chip->legacy.chip_delay = 50;
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 	chip->controller = &ndfc->ndfc_control;
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-	chip->read_buf = ndfc_read_buf;
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-	chip->write_buf = ndfc_write_buf;
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+	chip->legacy.read_buf = ndfc_read_buf;
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+	chip->legacy.write_buf = ndfc_write_buf;
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 	chip->ecc.correct = nand_correct_data;
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 	chip->ecc.hwctl = ndfc_enable_hwecc;
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 	chip->ecc.calculate = ndfc_calculate_ecc;
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-	chip->ecc.mode = NAND_ECC_HW;
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+	chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
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 	chip->ecc.size = 256;
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 	chip->ecc.bytes = 3;
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 	chip->ecc.strength = 1;
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@@ -174,8 +162,8 @@
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 		return -ENODEV;
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 	nand_set_flash_node(chip, flash_np);
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-	mtd->name = kasprintf(GFP_KERNEL, "%s.%s", dev_name(&ndfc->ofdev->dev),
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-			      flash_np->name);
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+	mtd->name = kasprintf(GFP_KERNEL, "%s.%pOFn", dev_name(&ndfc->ofdev->dev),
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+			      flash_np);
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 	if (!mtd->name) {
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 		ret = -ENOMEM;
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 		goto err;
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@@ -256,9 +244,13 @@
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 static int ndfc_remove(struct platform_device *ofdev)
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 {
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 	struct ndfc_controller *ndfc = dev_get_drvdata(&ofdev->dev);
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-	struct mtd_info *mtd = nand_to_mtd(&ndfc->chip);
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+	struct nand_chip *chip = &ndfc->chip;
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+	struct mtd_info *mtd = nand_to_mtd(chip);
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+	int ret;
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-	nand_release(&ndfc->chip);
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+	ret = mtd_device_unregister(mtd);
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+	WARN_ON(ret);
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+	nand_cleanup(chip);
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 	kfree(mtd->name);
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 	return 0;