| .. | .. |
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| 1 | +# SPDX-License-Identifier: GPL-2.0-only |
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| 1 | 2 | menu "Mapping drivers for chip access" |
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| 2 | 3 | depends on MTD!=n |
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| 3 | 4 | depends on HAS_IOMEM |
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| .. | .. |
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| 10 | 11 | |
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| 11 | 12 | config MTD_PHYSMAP |
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| 12 | 13 | tristate "Flash device in physical memory map" |
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| 13 | | - depends on MTD_CFI || MTD_JEDECPROBE || MTD_ROM || MTD_LPDDR |
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| 14 | + depends on MTD_CFI || MTD_JEDECPROBE || MTD_ROM || MTD_RAM || MTD_LPDDR |
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| 14 | 15 | help |
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| 15 | 16 | This provides a 'mapping' driver which allows the NOR Flash and |
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| 16 | 17 | ROM driver code to communicate with chips which are mapped |
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| .. | .. |
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| 66 | 67 | used internally by the CFI drivers. |
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| 67 | 68 | |
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| 68 | 69 | config MTD_PHYSMAP_OF |
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| 69 | | - tristate "Memory device in physical memory map based on OF description" |
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| 70 | | - depends on OF && (MTD_CFI || MTD_JEDECPROBE || MTD_ROM || MTD_RAM) |
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| 70 | + bool "Memory device in physical memory map based on OF description" |
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| 71 | + depends on OF && MTD_PHYSMAP |
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| 71 | 72 | help |
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| 72 | 73 | This provides a 'mapping' driver which allows the NOR Flash, ROM |
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| 73 | 74 | and RAM driver code to communicate with chips which are mapped |
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| 74 | 75 | physically into the CPU's memory. The mapping description here is |
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| 75 | 76 | taken from OF device tree. |
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| 76 | 77 | |
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| 77 | | -config MTD_PHYSMAP_OF_VERSATILE |
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| 78 | +config MTD_PHYSMAP_BT1_ROM |
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| 79 | + bool "Baikal-T1 Boot ROMs OF-based physical memory map handling" |
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| 80 | + depends on MTD_PHYSMAP_OF |
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| 81 | + depends on MIPS_BAIKAL_T1 || COMPILE_TEST |
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| 82 | + select MTD_COMPLEX_MAPPINGS |
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| 83 | + select MULTIPLEXER |
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| 84 | + select MUX_MMIO |
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| 85 | + help |
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| 86 | + This provides some extra DT physmap parsing for the Baikal-T1 |
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| 87 | + platforms, some detection and setting up ROMs-specific accessors. |
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| 88 | + |
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| 89 | +config MTD_PHYSMAP_VERSATILE |
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| 78 | 90 | bool "ARM Versatile OF-based physical memory map handling" |
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| 79 | 91 | depends on MTD_PHYSMAP_OF |
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| 80 | 92 | depends on MFD_SYSCON |
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| .. | .. |
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| 84 | 96 | platforms, basically to add a VPP (write protection) callback so |
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| 85 | 97 | the flash can be taken out of write protection. |
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| 86 | 98 | |
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| 87 | | -config MTD_PHYSMAP_OF_GEMINI |
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| 99 | +config MTD_PHYSMAP_GEMINI |
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| 88 | 100 | bool "Cortina Gemini OF-based physical memory map handling" |
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| 89 | 101 | depends on MTD_PHYSMAP_OF |
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| 90 | 102 | depends on MFD_SYSCON |
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| 103 | + select MTD_COMPLEX_MAPPINGS |
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| 91 | 104 | default ARCH_GEMINI |
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| 92 | 105 | help |
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| 93 | 106 | This provides some extra DT physmap parsing for the Gemini |
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| 94 | 107 | platforms, some detection and setting up parallel mode on the |
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| 95 | 108 | external interface. |
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| 109 | + |
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| 110 | +config MTD_PHYSMAP_IXP4XX |
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| 111 | + bool "Intel IXP4xx OF-based physical memory map handling" |
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| 112 | + depends on MTD_PHYSMAP_OF |
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| 113 | + depends on ARM |
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| 114 | + select MTD_COMPLEX_MAPPINGS |
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| 115 | + select MTD_CFI_BE_BYTE_SWAP if CPU_BIG_ENDIAN |
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| 116 | + default ARCH_IXP4XX |
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| 117 | + help |
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| 118 | + This provides some extra DT physmap parsing for the Intel IXP4xx |
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| 119 | + platforms, some elaborate endianness handling in particular. |
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| 120 | + |
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| 121 | +config MTD_PHYSMAP_GPIO_ADDR |
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| 122 | + bool "GPIO-assisted Flash Chip Support" |
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| 123 | + depends on MTD_PHYSMAP |
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| 124 | + depends on GPIOLIB || COMPILE_TEST |
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| 125 | + depends on MTD_COMPLEX_MAPPINGS |
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| 126 | + help |
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| 127 | + Extend the physmap driver to allow flashes to be partially |
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| 128 | + physically addressed and assisted by GPIOs. |
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| 96 | 129 | |
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| 97 | 130 | config MTD_PMC_MSP_EVM |
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| 98 | 131 | tristate "CFI Flash device mapped on PMC-Sierra MSP" |
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| .. | .. |
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| 288 | 321 | help |
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| 289 | 322 | This provides a driver for the flash accessed using Intel's |
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| 290 | 323 | 21285 bridge used with Intel's StrongARM processors. More info at |
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| 291 | | - <http://www.intel.com/design/bridge/docs/21285_documentation.htm>. |
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| 324 | + <https://www.intel.com/design/bridge/docs/21285_documentation.htm>. |
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| 292 | 325 | |
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| 293 | 326 | config MTD_IXP4XX |
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| 294 | 327 | tristate "CFI Flash device mapped on Intel IXP4xx based systems" |
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| 295 | | - depends on MTD_CFI && MTD_COMPLEX_MAPPINGS && ARCH_IXP4XX |
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| 328 | + depends on MTD_CFI && MTD_COMPLEX_MAPPINGS && ARCH_IXP4XX && MTD_CFI_ADV_OPTIONS |
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| 296 | 329 | help |
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| 297 | 330 | This enables MTD access to flash devices on platforms based |
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| 298 | 331 | on Intel's IXP4xx family of network processors such as the |
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| .. | .. |
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| 333 | 366 | anything about themselves are assumed to be MTD cards. |
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| 334 | 367 | |
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| 335 | 368 | If unsure, say N. |
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| 336 | | - |
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| 337 | | -config MTD_GPIO_ADDR |
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| 338 | | - tristate "GPIO-assisted Flash Chip Support" |
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| 339 | | - depends on GPIOLIB || COMPILE_TEST |
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| 340 | | - depends on MTD_COMPLEX_MAPPINGS |
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| 341 | | - help |
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| 342 | | - Map driver which allows flashes to be partially physically addressed |
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| 343 | | - and assisted by GPIOs. |
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| 344 | | - |
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| 345 | | - If compiled as a module, it will be called gpio-addr-flash. |
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| 346 | 369 | |
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| 347 | 370 | config MTD_UCLINUX |
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| 348 | 371 | bool "Generic uClinux RAM/ROM filesystem support" |
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| .. | .. |
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| 399 | 422 | and/or MTD_PLATRAM according to the devices on your module. |
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| 400 | 423 | |
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| 401 | 424 | When built as a module, it will be called pismo.ko |
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| 402 | | - |
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| 403 | | -config MTD_LATCH_ADDR |
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| 404 | | - tristate "Latch-assisted Flash Chip Support" |
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| 405 | | - depends on MTD_COMPLEX_MAPPINGS |
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| 406 | | - help |
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| 407 | | - Map driver which allows flashes to be partially physically addressed |
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| 408 | | - and have the upper address lines set by a board specific code. |
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| 409 | | - |
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| 410 | | - If compiled as a module, it will be called latch-addr-flash. |
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| 411 | 425 | |
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| 412 | 426 | endmenu |
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