add wifi6 8852be driver

hc

2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da

 kernel/drivers/misc/lattice-ecp3-config.c
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@@ -1,10 +1,6 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  * Copyright (C) 2012 Stefan Roese <sr@denx.de>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; either version 2 of the License, or
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- * (at your option) any later version.
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  */
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 #include <linux/device.h>
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@@ -71,7 +67,6 @@
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 	struct spi_device *spi = (struct spi_device *)context;
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 	struct fpga_data *data = spi_get_drvdata(spi);
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 	u8 *buffer;
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-	int ret;
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 	u8 txbuf[8];
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 	u8 rxbuf[8];
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 	int rx_len = 8;
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@@ -96,7 +91,7 @@
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 	/* Trying to speak with the FPGA via SPI... */
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 	txbuf[0] = FPGA_CMD_READ_ID;
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-	ret = spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
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+	spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
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 	jedec_id = get_unaligned_be32(&rxbuf[4]);
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 	dev_dbg(&spi->dev, "FPGA JTAG ID=%08x\n", jedec_id);
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@@ -114,7 +109,7 @@
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 	dev_info(&spi->dev, "FPGA %s detected\n", ecp3_dev[i].name);
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 	txbuf[0] = FPGA_CMD_READ_STATUS;
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-	ret = spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
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+	spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
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 	status = get_unaligned_be32(&rxbuf[4]);
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 	dev_dbg(&spi->dev, "FPGA Status=%08x\n", status);
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@@ -134,20 +129,20 @@
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 	memcpy(buffer + 4, fw->data, fw->size);
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 	txbuf[0] = FPGA_CMD_REFRESH;
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-	ret = spi_write(spi, txbuf, 4);
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+	spi_write(spi, txbuf, 4);
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 	txbuf[0] = FPGA_CMD_WRITE_EN;
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-	ret = spi_write(spi, txbuf, 4);
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+	spi_write(spi, txbuf, 4);
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 	txbuf[0] = FPGA_CMD_CLEAR;
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-	ret = spi_write(spi, txbuf, 4);
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+	spi_write(spi, txbuf, 4);
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 	/*
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 	 * Wait for FPGA memory to become cleared
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 	 */
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 	for (i = 0; i < FPGA_CLEAR_LOOP_COUNT; i++) {
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 		txbuf[0] = FPGA_CMD_READ_STATUS;
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-		ret = spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
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+		spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
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 		status = get_unaligned_be32(&rxbuf[4]);
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 		if (status == FPGA_STATUS_CLEARED)
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 			break;
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@@ -164,13 +159,13 @@
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 	}
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 	dev_info(&spi->dev, "Configuring the FPGA...\n");
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-	ret = spi_write(spi, buffer, fw->size + 8);
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+	spi_write(spi, buffer, fw->size + 8);
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 	txbuf[0] = FPGA_CMD_WRITE_DIS;
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-	ret = spi_write(spi, txbuf, 4);
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+	spi_write(spi, txbuf, 4);
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 	txbuf[0] = FPGA_CMD_READ_STATUS;
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-	ret = spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
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+	spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
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 	status = get_unaligned_be32(&rxbuf[4]);
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 	dev_dbg(&spi->dev, "FPGA Status=%08x\n", status);
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