add wifi6 8852be driver

hc

2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da

 kernel/drivers/media/platform/xilinx/xilinx-vip.h
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@@ -1,3 +1,4 @@
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+/* SPDX-License-Identifier: GPL-2.0 */
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 /*
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  * Xilinx Video IP Core
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  *
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@@ -6,15 +7,12 @@
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  *
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  * Contacts: Hyun Kwon <hyun.kwon@xilinx.com>
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  *           Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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 #ifndef __XILINX_VIP_H__
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 #define __XILINX_VIP_H__
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+#include <linux/bitops.h>
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 #include <linux/io.h>
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 #include <media/v4l2-subdev.h>
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@@ -38,23 +36,23 @@
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 /* Xilinx Video IP Control Registers */
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 #define XVIP_CTRL_CONTROL			0x0000
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-#define XVIP_CTRL_CONTROL_SW_ENABLE		(1 << 0)
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-#define XVIP_CTRL_CONTROL_REG_UPDATE		(1 << 1)
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-#define XVIP_CTRL_CONTROL_BYPASS		(1 << 4)
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-#define XVIP_CTRL_CONTROL_TEST_PATTERN		(1 << 5)
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-#define XVIP_CTRL_CONTROL_FRAME_SYNC_RESET	(1 << 30)
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-#define XVIP_CTRL_CONTROL_SW_RESET		(1 << 31)
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+#define XVIP_CTRL_CONTROL_SW_ENABLE		BIT(0)
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+#define XVIP_CTRL_CONTROL_REG_UPDATE		BIT(1)
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+#define XVIP_CTRL_CONTROL_BYPASS		BIT(4)
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+#define XVIP_CTRL_CONTROL_TEST_PATTERN		BIT(5)
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+#define XVIP_CTRL_CONTROL_FRAME_SYNC_RESET	BIT(30)
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+#define XVIP_CTRL_CONTROL_SW_RESET		BIT(31)
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 #define XVIP_CTRL_STATUS			0x0004
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-#define XVIP_CTRL_STATUS_PROC_STARTED		(1 << 0)
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-#define XVIP_CTRL_STATUS_EOF			(1 << 1)
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+#define XVIP_CTRL_STATUS_PROC_STARTED		BIT(0)
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+#define XVIP_CTRL_STATUS_EOF			BIT(1)
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 #define XVIP_CTRL_ERROR				0x0008
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-#define XVIP_CTRL_ERROR_SLAVE_EOL_EARLY		(1 << 0)
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-#define XVIP_CTRL_ERROR_SLAVE_EOL_LATE		(1 << 1)
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-#define XVIP_CTRL_ERROR_SLAVE_SOF_EARLY		(1 << 2)
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-#define XVIP_CTRL_ERROR_SLAVE_SOF_LATE		(1 << 3)
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+#define XVIP_CTRL_ERROR_SLAVE_EOL_EARLY		BIT(0)
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+#define XVIP_CTRL_ERROR_SLAVE_EOL_LATE		BIT(1)
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+#define XVIP_CTRL_ERROR_SLAVE_SOF_EARLY		BIT(2)
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+#define XVIP_CTRL_ERROR_SLAVE_SOF_LATE		BIT(3)
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 #define XVIP_CTRL_IRQ_ENABLE			0x000c
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-#define XVIP_CTRL_IRQ_ENABLE_PROC_STARTED	(1 << 0)
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-#define XVIP_CTRL_IRQ_EOF			(1 << 1)
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+#define XVIP_CTRL_IRQ_ENABLE_PROC_STARTED	BIT(0)
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+#define XVIP_CTRL_IRQ_EOF			BIT(1)
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 #define XVIP_CTRL_VERSION			0x0010
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 #define XVIP_CTRL_VERSION_MAJOR_MASK		(0xff << 24)
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 #define XVIP_CTRL_VERSION_MAJOR_SHIFT		24
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@@ -111,7 +109,6 @@
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  * @code: media bus format code
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  * @bpp: bytes per pixel (when stored in memory)
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  * @fourcc: V4L2 pixel format FCC identifier
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- * @description: format description, suitable for userspace
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  */
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 struct xvip_video_format {
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 	unsigned int vf_code;
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 	unsigned int code;
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 	unsigned int bpp;
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 	u32 fourcc;
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-	const char *description;
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 };
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 const struct xvip_video_format *xvip_get_format_by_code(unsigned int code);