add wifi6 8852be driver

hc

2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da

 kernel/drivers/irqchip/irq-sun4i.c
..
..
@@ -28,11 +28,21 @@
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28
 #define SUN4I_IRQ_NMI_CTRL_REG		0x0c
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 #define SUN4I_IRQ_PENDING_REG(x)	(0x10 + 0x4 * x)
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 #define SUN4I_IRQ_FIQ_PENDING_REG(x)	(0x20 + 0x4 * x)
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-#define SUN4I_IRQ_ENABLE_REG(x)		(0x40 + 0x4 * x)
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-#define SUN4I_IRQ_MASK_REG(x)		(0x50 + 0x4 * x)
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+#define SUN4I_IRQ_ENABLE_REG(data, x)	((data)->enable_reg_offset + 0x4 * x)
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+#define SUN4I_IRQ_MASK_REG(data, x)	((data)->mask_reg_offset + 0x4 * x)
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+#define SUN4I_IRQ_ENABLE_REG_OFFSET	0x40
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+#define SUN4I_IRQ_MASK_REG_OFFSET	0x50
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+#define SUNIV_IRQ_ENABLE_REG_OFFSET	0x20
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+#define SUNIV_IRQ_MASK_REG_OFFSET	0x30
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37
 
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-static void __iomem *sun4i_irq_base;
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-static struct irq_domain *sun4i_irq_domain;
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+struct sun4i_irq_chip_data {
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+	void __iomem *irq_base;
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+	struct irq_domain *irq_domain;
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+	u32 enable_reg_offset;
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+	u32 mask_reg_offset;
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+};
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+
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+static struct sun4i_irq_chip_data *irq_ic_data;
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46
 
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 static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs);
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48
 
..
..
@@ -43,7 +53,7 @@
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 	if (irq != 0)
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 		return; /* Only IRQ 0 / the ENMI needs to be acked */
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55
 
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-	writel(BIT(0), sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0));
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+	writel(BIT(0), irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0));
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 }
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58
 
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 static void sun4i_irq_mask(struct irq_data *irqd)
..
..
@@ -53,9 +63,10 @@
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 	int reg = irq / 32;
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 	u32 val;
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65
 
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-	val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
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+	val = readl(irq_ic_data->irq_base +
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+			SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg));
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 	writel(val & ~(1 << irq_off),
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-	       sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
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+	       irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg));
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 }
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71
 
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 static void sun4i_irq_unmask(struct irq_data *irqd)
..
..
@@ -65,9 +76,10 @@
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 	int reg = irq / 32;
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 	u32 val;
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78
 
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-	val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
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+	val = readl(irq_ic_data->irq_base +
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+			SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg));
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 	writel(val | (1 << irq_off),
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-	       sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
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+	       irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg));
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 }
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84
 
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 static struct irq_chip sun4i_irq_chip = {
..
..
@@ -95,42 +107,76 @@
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 static int __init sun4i_of_init(struct device_node *node,
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 				struct device_node *parent)
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 {
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-	sun4i_irq_base = of_iomap(node, 0);
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-	if (!sun4i_irq_base)
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+	irq_ic_data->irq_base = of_iomap(node, 0);
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+	if (!irq_ic_data->irq_base)
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 		panic("%pOF: unable to map IC registers\n",
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 			node);
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114
 
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 	/* Disable all interrupts */
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-	writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(0));
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-	writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(1));
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-	writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(2));
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+	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 0));
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+	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 1));
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+	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 2));
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119
 
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 	/* Unmask all the interrupts, ENABLE_REG(x) is used for masking */
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-	writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(0));
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-	writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(1));
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-	writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(2));
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+	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 0));
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+	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 1));
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+	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 2));
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124
 
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 	/* Clear all the pending interrupts */
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-	writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0));
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-	writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(1));
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-	writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(2));
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+	writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0));
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+	writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(1));
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+	writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(2));
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129
 
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 	/* Enable protection mode */
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-	writel(0x01, sun4i_irq_base + SUN4I_IRQ_PROTECTION_REG);
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+	writel(0x01, irq_ic_data->irq_base + SUN4I_IRQ_PROTECTION_REG);
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132
 
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 	/* Configure the external interrupt source type */
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-	writel(0x00, sun4i_irq_base + SUN4I_IRQ_NMI_CTRL_REG);
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+	writel(0x00, irq_ic_data->irq_base + SUN4I_IRQ_NMI_CTRL_REG);
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135
 
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-	sun4i_irq_domain = irq_domain_add_linear(node, 3 * 32,
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+	irq_ic_data->irq_domain = irq_domain_add_linear(node, 3 * 32,
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 						 &sun4i_irq_ops, NULL);
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-	if (!sun4i_irq_domain)
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+	if (!irq_ic_data->irq_domain)
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 		panic("%pOF: unable to create IRQ domain\n", node);
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140
 
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 	set_handle_irq(sun4i_handle_irq);
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 	return 0;
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 }
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-IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_of_init);
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+
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+static int __init sun4i_ic_of_init(struct device_node *node,
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+				   struct device_node *parent)
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+{
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+	irq_ic_data = kzalloc(sizeof(struct sun4i_irq_chip_data), GFP_KERNEL);
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+	if (!irq_ic_data) {
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+		pr_err("kzalloc failed!\n");
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+		return -ENOMEM;
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+	}
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+
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+	irq_ic_data->enable_reg_offset = SUN4I_IRQ_ENABLE_REG_OFFSET;
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+	irq_ic_data->mask_reg_offset = SUN4I_IRQ_MASK_REG_OFFSET;
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+
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+	return sun4i_of_init(node, parent);
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+}
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+
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+IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_ic_of_init);
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+
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+static int __init suniv_ic_of_init(struct device_node *node,
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+				   struct device_node *parent)
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+{
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+	irq_ic_data = kzalloc(sizeof(struct sun4i_irq_chip_data), GFP_KERNEL);
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+	if (!irq_ic_data) {
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+		pr_err("kzalloc failed!\n");
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+		return -ENOMEM;
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+	}
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+
172
+	irq_ic_data->enable_reg_offset = SUNIV_IRQ_ENABLE_REG_OFFSET;
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+	irq_ic_data->mask_reg_offset = SUNIV_IRQ_MASK_REG_OFFSET;
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+
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+	return sun4i_of_init(node, parent);
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+}
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+
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+IRQCHIP_DECLARE(allwinner_sunvi_ic, "allwinner,suniv-f1c100s-ic",
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+		suniv_ic_of_init);
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180
 
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 static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs)
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 {
..
..
@@ -143,16 +189,18 @@
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 	 * 3) spurious irq
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 	 * So if we immediately get a reading of 0, check the irq-pending reg
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 	 * to differentiate between 2 and 3. We only do this once to avoid
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-	 * the extra check in the common case of 1 hapening after having
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+	 * the extra check in the common case of 1 happening after having
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 	 * read the vector-reg once.
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 	 */
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-	hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
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+	hwirq = readl(irq_ic_data->irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
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 	if (hwirq == 0 &&
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-		  !(readl(sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0)) & BIT(0)))
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+		  !(readl(irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0)) &
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+			  BIT(0)))
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 		return;
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200
 
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 	do {
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-		handle_domain_irq(sun4i_irq_domain, hwirq, regs);
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-		hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
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+		handle_domain_irq(irq_ic_data->irq_domain, hwirq, regs);
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+		hwirq = readl(irq_ic_data->irq_base +
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+				SUN4I_IRQ_VECTOR_REG) >> 2;
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 	} while (hwirq != 0);
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 }