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380 | 380 | #define DC_LCB_PRF_TX_FLIT_CNT (DC_LCB_CSRS + 0x000000000418) |
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381 | 381 | #define DC_LCB_STS_LINK_TRANSFER_ACTIVE (DC_LCB_CSRS + 0x000000000468) |
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382 | 382 | #define DC_LCB_STS_ROUND_TRIP_LTP_CNT (DC_LCB_CSRS + 0x0000000004B0) |
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| 383 | +#define RCV_LENGTH_ERR_CNT 0 |
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| 384 | +#define RCV_SHORT_ERR_CNT 2 |
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| 385 | +#define RCV_ICRC_ERR_CNT 6 |
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| 386 | +#define RCV_EBP_CNT 9 |
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383 | 387 | #define RCV_BUF_OVFL_CNT 10 |
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384 | 388 | #define RCV_CONTEXT_EGR_STALL 22 |
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385 | 389 | #define RCV_DATA_PKT_CNT 0 |
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878 | 882 | #define SEND_CTRL (TXE + 0x000000000000) |
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879 | 883 | #define SEND_CTRL_CM_RESET_SMASK 0x4ull |
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880 | 884 | #define SEND_CTRL_SEND_ENABLE_SMASK 0x1ull |
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| 885 | +#define SEND_CTRL_UNSUPPORTED_VL_SHIFT 3 |
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| 886 | +#define SEND_CTRL_UNSUPPORTED_VL_MASK 0xFFull |
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| 887 | +#define SEND_CTRL_UNSUPPORTED_VL_SMASK (SEND_CTRL_UNSUPPORTED_VL_MASK \ |
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| 888 | + << SEND_CTRL_UNSUPPORTED_VL_SHIFT) |
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881 | 889 | #define SEND_CTRL_VL_ARBITER_ENABLE_SMASK 0x2ull |
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882 | 890 | #define SEND_CTXT_CHECK_ENABLE (TXE + 0x000000100080) |
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883 | 891 | #define SEND_CTXT_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK 0x80ull |
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931 | 939 | #define SEND_CTXT_CREDIT_CTRL_THRESHOLD_MASK 0x7FFull |
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932 | 940 | #define SEND_CTXT_CREDIT_CTRL_THRESHOLD_SHIFT 0 |
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933 | 941 | #define SEND_CTXT_CREDIT_CTRL_THRESHOLD_SMASK 0x7FFull |
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| 942 | +#define SEND_CTXT_CREDIT_STATUS (TXE + 0x000000100018) |
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| 943 | +#define SEND_CTXT_CREDIT_STATUS_CURRENT_FREE_COUNTER_MASK 0x7FFull |
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| 944 | +#define SEND_CTXT_CREDIT_STATUS_CURRENT_FREE_COUNTER_SHIFT 32 |
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| 945 | +#define SEND_CTXT_CREDIT_STATUS_LAST_RETURNED_COUNTER_SMASK 0x7FFull |
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934 | 946 | #define SEND_CTXT_CREDIT_FORCE (TXE + 0x000000100028) |
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935 | 947 | #define SEND_CTXT_CREDIT_FORCE_FORCE_RETURN_SMASK 0x1ull |
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936 | 948 | #define SEND_CTXT_CREDIT_RETURN_ADDR (TXE + 0x000000100020) |
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