.. | .. |
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21 | 21 | * |
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22 | 22 | */ |
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23 | 23 | |
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24 | | -#include <drm/drmP.h> |
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| 24 | +#include <linux/math64.h> |
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| 25 | +#include <linux/pci.h> |
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| 26 | +#include <linux/seq_file.h> |
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| 27 | + |
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| 28 | +#include "atom.h" |
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| 29 | +#include "r600_dpm.h" |
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25 | 30 | #include "radeon.h" |
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26 | 31 | #include "radeon_asic.h" |
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27 | | -#include "sid.h" |
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28 | | -#include "r600_dpm.h" |
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29 | 32 | #include "si_dpm.h" |
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30 | | -#include "atom.h" |
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31 | | -#include <linux/math64.h> |
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32 | | -#include <linux/seq_file.h> |
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| 33 | +#include "sid.h" |
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33 | 34 | |
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34 | 35 | #define MC_CG_ARB_FREQ_F0 0x0a |
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35 | 36 | #define MC_CG_ARB_FREQ_F1 0x0b |
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.. | .. |
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249 | 250 | { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, |
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250 | 251 | 85, |
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251 | 252 | false |
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252 | | -}; |
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253 | | - |
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254 | | -static const struct si_dte_data dte_data_tahiti_le = |
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255 | | -{ |
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256 | | - { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 }, |
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257 | | - { 0x7D, 0x7D, 0x4E4, 0xB00, 0 }, |
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258 | | - 0x5, |
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259 | | - 0xAFC8, |
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260 | | - 0x64, |
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261 | | - 0x32, |
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262 | | - 1, |
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263 | | - 0, |
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264 | | - 0x10, |
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265 | | - { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 }, |
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266 | | - { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 }, |
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267 | | - { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 }, |
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268 | | - 85, |
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269 | | - true |
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270 | 253 | }; |
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271 | 254 | |
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272 | 255 | static const struct si_dte_data dte_data_tahiti_pro = |
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.. | .. |
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2978 | 2961 | |
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2979 | 2962 | if (rdev->family == CHIP_HAINAN) { |
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2980 | 2963 | if ((rdev->pdev->revision == 0x81) || |
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2981 | | - (rdev->pdev->revision == 0x83) || |
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2982 | 2964 | (rdev->pdev->revision == 0xC3) || |
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2983 | 2965 | (rdev->pdev->device == 0x6664) || |
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2984 | 2966 | (rdev->pdev->device == 0x6665) || |
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.. | .. |
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3641 | 3623 | |
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3642 | 3624 | static void si_program_response_times(struct radeon_device *rdev) |
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3643 | 3625 | { |
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3644 | | - u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out; |
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| 3626 | + u32 voltage_response_time, acpi_delay_time, vbi_time_out; |
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3645 | 3627 | u32 vddc_dly, acpi_dly, vbi_dly; |
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3646 | 3628 | u32 reference_clock; |
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3647 | 3629 | |
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3648 | 3630 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); |
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3649 | 3631 | |
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3650 | 3632 | voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; |
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3651 | | - backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; |
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3652 | 3633 | |
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3653 | 3634 | if (voltage_response_time == 0) |
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3654 | 3635 | voltage_response_time = 1000; |
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.. | .. |
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5766 | 5747 | si_pi->force_pcie_gen = RADEON_PCIE_GEN2; |
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5767 | 5748 | if (current_link_speed == RADEON_PCIE_GEN2) |
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5768 | 5749 | break; |
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| 5750 | + fallthrough; |
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5769 | 5751 | case RADEON_PCIE_GEN2: |
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5770 | 5752 | if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) |
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5771 | 5753 | break; |
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5772 | 5754 | #endif |
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| 5755 | + /* fall through */ |
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5773 | 5756 | default: |
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5774 | 5757 | si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); |
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5775 | 5758 | break; |
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.. | .. |
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5899 | 5882 | |
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5900 | 5883 | static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) |
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5901 | 5884 | { |
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5902 | | - int ret = 0; |
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| 5885 | + int ret; |
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5903 | 5886 | |
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5904 | 5887 | ret = si_patch_single_dependency_table_based_on_leakage(rdev, |
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5905 | 5888 | &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); |
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