add wifi6 8852be driver

hc

2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da

 kernel/drivers/gpu/drm/meson/meson_dw_hdmi.h
..
..
@@ -1,29 +1,20 @@
1
+/* SPDX-License-Identifier: GPL-2.0-or-later */
1
2
 /*
2
3
  * Copyright (C) 2016 BayLibre, SAS
3
4
  * Author: Neil Armstrong <narmstrong@baylibre.com>
4
5
  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5
- *
6
- * This program is free software; you can redistribute it and/or
7
- * modify it under the terms of the GNU General Public License as
8
- * published by the Free Software Foundation; either version 2 of the
9
- * License, or (at your option) any later version.
10
- *
11
- * This program is distributed in the hope that it will be useful, but
12
- * WITHOUT ANY WARRANTY; without even the implied warranty of
13
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
- * General Public License for more details.
15
- *
16
- * You should have received a copy of the GNU General Public License
17
- * along with this program; if not, see <http://www.gnu.org/licenses/>.
18
6
  */
19
7
 
20
8
 #ifndef __MESON_DW_HDMI_H
21
9
 #define __MESON_DW_HDMI_H
22
10
 
23
11
 /*
24
- * Bit 7 RW Reserved. Default 1.
25
- * Bit 6 RW Reserved. Default 1.
26
- * Bit 5 RW Reserved. Default 1.
12
+ * Bit 15-10: RW Reserved. Default 1 starting from G12A
13
+ * Bit 9 RW sw_reset_i2c starting from G12A
14
+ * Bit 8 RW sw_reset_axiarb starting from G12A
15
+ * Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A
16
+ * Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A
17
+ * Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A
27
18
  * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
28
19
  *     Default 1.
29
20
  * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
..
..
@@ -39,12 +30,16 @@
39
30
 #define HDMITX_TOP_SW_RESET                     (0x000)
40
31
 
41
32
 /*
33
+ * Bit 31 RW free_clk_en: 0=Enable clock gating for power saving; 1= Disable
42
34
  * Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0.
43
35
  * Bit 11 RW i2s_clk_inv: 1=Invert i2s_clk; 0=No invert. Default 0.
44
36
  * Bit 10 RW spdif_clk_inv: 1=Invert spdif_clk; 0=No invert. Default 0.
45
37
  * Bit 9 RW tmds_clk_inv: 1=Invert tmds_clk; 0=No invert. Default 0.
46
38
  * Bit 8 RW pixel_clk_inv: 1=Invert pixel_clk; 0=No invert. Default 0.
47
- * Bit 4 RW cec_clk_en: 1=enable cec_clk; 0=disable. Default 0.
39
+ * Bit 7 RW hdcp22_skpclk_en: starting from G12A, 1=enable; 0=disable
40
+ * Bit 6 RW hdcp22_esmclk_en: starting from G12A, 1=enable; 0=disable
41
+ * Bit 5 RW hdcp22_tmdsclk_en: starting from G12A, 1=enable; 0=disable
42
+ * Bit 4 RW cec_clk_en: 1=enable cec_clk; 0=disable. Default 0. Reserved for G12A
48
43
  * Bit 3 RW i2s_clk_en: 1=enable i2s_clk; 0=disable. Default 0.
49
44
  * Bit 2 RW spdif_clk_en: 1=enable spdif_clk; 0=disable. Default 0.
50
45
  * Bit 1 RW tmds_clk_en: 1=enable tmds_clk;  0=disable. Default 0.
..
..
@@ -53,6 +48,8 @@
53
48
 #define HDMITX_TOP_CLK_CNTL                     (0x001)
54
49
 
55
50
 /*
51
+ * Bit 31:28 RW rxsense_glitch_width: starting from G12A
52
+ * Bit 27:16 RW rxsense_valid_width: starting from G12A
56
53
  * Bit 11: 0 RW hpd_valid_width: filter out width <= M*1024.    Default 0.
57
54
  * Bit 15:12 RW hpd_glitch_width: filter out glitch <= N.       Default 0.
58
55
  */
..
..
@@ -61,6 +58,9 @@
61
58
 /*
62
59
  * intr_maskn: MASK_N, one bit per interrupt source.
63
60
  *     1=Enable interrupt source; 0=Disable interrupt source. Default 0.
61
+ * [  7] rxsense_fall starting from G12A
62
+ * [  6] rxsense_rise starting from G12A
63
+ * [  5] err_i2c_timeout starting from G12A
64
64
  * [  4] hdcp22_rndnum_err
65
65
  * [  3] nonce_rfrsh_rise
66
66
  * [  2] hpd_fall_intr
..
..
@@ -73,6 +73,9 @@
73
73
  * Bit 30: 0 RW intr_stat: For each bit, write 1 to manually set the interrupt
74
74
  *     bit, read back the interrupt status.
75
75
  * Bit    31 R  IP interrupt status
76
+ * Bit     7 RW rxsense_fall starting from G12A
77
+ * Bit     6 RW rxsense_rise starting from G12A
78
+ * Bit     5 RW err_i2c_timeout starting from G12A
76
79
  * Bit     2 RW hpd_fall
77
80
  * Bit     1 RW hpd_rise
78
81
  * Bit     0 RW IP interrupt
..
..
@@ -80,6 +83,9 @@
80
83
 #define HDMITX_TOP_INTR_STAT                    (0x004)
81
84
 
82
85
 /*
86
+ * [7]    rxsense_fall starting from G12A
87
+ * [6]    rxsense_rise starting from G12A
88
+ * [5]    err_i2c_timeout starting from G12A
83
89
  * [4]	  hdcp22_rndnum_err
84
90
  * [3]	  nonce_rfrsh_rise
85
91
  * [2]	  hpd_fall
..
..
@@ -91,8 +97,11 @@
91
97
 #define HDMITX_TOP_INTR_CORE		BIT(0)
92
98
 #define HDMITX_TOP_INTR_HPD_RISE	BIT(1)
93
99
 #define HDMITX_TOP_INTR_HPD_FALL	BIT(2)
100
+#define HDMITX_TOP_INTR_RXSENSE_RISE	BIT(6)
101
+#define HDMITX_TOP_INTR_RXSENSE_FALL	BIT(7)
94
102
 
95
-/* Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data;
103
+/*
104
+ * Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data;
96
105
  *     3'b010=Output PRBS data; 3'b100=Output shift pattern. Default 0.
97
106
  * Bit 11: 9 RW shift_pttn_repeat: 0=New pattern every clk cycle; 1=New pattern
98
107
  *     every 2 clk cycles; ...; 7=New pattern every 8 clk cycles. Default 0.
..
..
@@ -127,7 +136,8 @@
127
136
 /* Bit  9: 0 RW tmds_clk_pttn[29:20]. Default 0. */
128
137
 #define HDMITX_TOP_TMDS_CLK_PTTN_23             (0x00B)
129
138
 
130
-/* Bit 1 RW shift_tmds_clk_pttn:1=Enable shifting clk pattern,
139
+/*
140
+ * Bit 1 RW shift_tmds_clk_pttn:1=Enable shifting clk pattern,
131
141
  * used when TMDS CLK rate = TMDS character rate /4. Default 0.
132
142
  * Bit 0 R  Reserved. Default 0.
133
143
  * [	1] shift_tmds_clk_pttn
..
..
@@ -135,12 +145,16 @@
135
145
  */
136
146
 #define HDMITX_TOP_TMDS_CLK_PTTN_CNTL           (0x00C)
137
147
 
138
-/* Bit 0 RW revocmem_wr_fail: Read back 1 to indicate Host write REVOC MEM
148
+/*
149
+ * Bit 0 RW revocmem_wr_fail: Read back 1 to indicate Host write REVOC MEM
139
150
  * failure, write 1 to clear the failure flag.  Default 0.
140
151
  */
141
152
 #define HDMITX_TOP_REVOCMEM_STAT                (0x00D)
142
153
 
143
-/* Bit     0 R  filtered HPD status. */
154
+/*
155
+ * Bit	   1 R	filtered RxSense status
156
+ * Bit     0 R  filtered HPD status.
157
+ */
144
158
 #define HDMITX_TOP_STAT0                        (0x00E)
145
159
 
146
160
 #endif /* __MESON_DW_HDMI_H */