forked from ~ljy/RK356X_SDK_RELEASE

blame | history | patch | commit | commitdiff
hc
2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da 
 kernel/drivers/gpu/drm/meson/meson_drv.h
....@@ -1,51 +1,152 @@
1
+/* SPDX-License-Identifier: GPL-2.0-or-later */
12 /*
23  * Copyright (C) 2016 BayLibre, SAS
34  * Author: Neil Armstrong <narmstrong@baylibre.com>
4
- *
5
- * This program is free software; you can redistribute it and/or
6
- * modify it under the terms of the GNU General Public License as
7
- * published by the Free Software Foundation; either version 2 of the
8
- * License, or (at your option) any later version.
9
- *
10
- * This program is distributed in the hope that it will be useful, but
11
- * WITHOUT ANY WARRANTY; without even the implied warranty of
12
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
13
- * General Public License for more details.
14
- *
15
- * You should have received a copy of the GNU General Public License
16
- * along with this program; if not, see <http://www.gnu.org/licenses/>.
175  */
186 
197 #ifndef __MESON_DRV_H
208 #define __MESON_DRV_H
219 
22
-#include <linux/platform_device.h>
23
-#include <linux/regmap.h>
10
+#include <linux/device.h>
2411 #include <linux/of.h>
25
-#include <drm/drmP.h>
12
+#include <linux/of_device.h>
13
+#include <linux/regmap.h>
14
+
15
+struct drm_crtc;
16
+struct drm_device;
17
+struct drm_plane;
18
+struct meson_drm;
19
+struct meson_afbcd_ops;
20
+
21
+enum vpu_compatible {
22
+	VPU_COMPATIBLE_GXBB = 0,
23
+	VPU_COMPATIBLE_GXL  = 1,
24
+	VPU_COMPATIBLE_GXM  = 2,
25
+	VPU_COMPATIBLE_G12A = 3,
26
+};
27
+
28
+struct meson_drm_match_data {
29
+	enum vpu_compatible compat;
30
+	struct meson_afbcd_ops *afbcd_ops;
31
+};
32
+
33
+struct meson_drm_soc_limits {
34
+	unsigned int max_hdmi_phy_freq;
35
+};
2636 
2737 struct meson_drm {
2838 	struct device *dev;
39
+	enum vpu_compatible compat;
2940 	void __iomem *io_base;
3041 	struct regmap *hhi;
31
-	struct regmap *dmc;
3242 	int vsync_irq;
43
+
44
+	struct meson_canvas *canvas;
45
+	u8 canvas_id_osd1;
46
+	u8 canvas_id_vd1_0;
47
+	u8 canvas_id_vd1_1;
48
+	u8 canvas_id_vd1_2;
3349 
3450 	struct drm_device *drm;
3551 	struct drm_crtc *crtc;
36
-	struct drm_fbdev_cma *fbdev;
3752 	struct drm_plane *primary_plane;
53
+	struct drm_plane *overlay_plane;
54
+
55
+	const struct meson_drm_soc_limits *limits;
3856 
3957 	/* Components Data */
4058 	struct {
4159 		bool osd1_enabled;
4260 		bool osd1_interlace;
4361 		bool osd1_commit;
62
+		bool osd1_afbcd;
4463 		uint32_t osd1_ctrl_stat;
64
+		uint32_t osd1_ctrl_stat2;
4565 		uint32_t osd1_blk0_cfg[5];
66
+		uint32_t osd1_blk1_cfg4;
67
+		uint32_t osd1_blk2_cfg4;
4668 		uint32_t osd1_addr;
4769 		uint32_t osd1_stride;
4870 		uint32_t osd1_height;
71
+		uint32_t osd1_width;
72
+		uint32_t osd_sc_ctrl0;
73
+		uint32_t osd_sc_i_wh_m1;
74
+		uint32_t osd_sc_o_h_start_end;
75
+		uint32_t osd_sc_o_v_start_end;
76
+		uint32_t osd_sc_v_ini_phase;
77
+		uint32_t osd_sc_v_phase_step;
78
+		uint32_t osd_sc_h_ini_phase;
79
+		uint32_t osd_sc_h_phase_step;
80
+		uint32_t osd_sc_h_ctrl0;
81
+		uint32_t osd_sc_v_ctrl0;
82
+		uint32_t osd_blend_din0_scope_h;
83
+		uint32_t osd_blend_din0_scope_v;
84
+		uint32_t osb_blend0_size;
85
+		uint32_t osb_blend1_size;
86
+
87
+		bool vd1_enabled;
88
+		bool vd1_commit;
89
+		bool vd1_afbc;
90
+		unsigned int vd1_planes;
91
+		uint32_t vd1_if0_gen_reg;
92
+		uint32_t vd1_if0_luma_x0;
93
+		uint32_t vd1_if0_luma_y0;
94
+		uint32_t vd1_if0_chroma_x0;
95
+		uint32_t vd1_if0_chroma_y0;
96
+		uint32_t vd1_if0_repeat_loop;
97
+		uint32_t vd1_if0_luma0_rpt_pat;
98
+		uint32_t vd1_if0_chroma0_rpt_pat;
99
+		uint32_t vd1_range_map_y;
100
+		uint32_t vd1_range_map_cb;
101
+		uint32_t vd1_range_map_cr;
102
+		uint32_t viu_vd1_fmt_w;
103
+		uint32_t vd1_if0_canvas0;
104
+		uint32_t vd1_if0_gen_reg2;
105
+		uint32_t viu_vd1_fmt_ctrl;
106
+		uint32_t vd1_addr0;
107
+		uint32_t vd1_addr1;
108
+		uint32_t vd1_addr2;
109
+		uint32_t vd1_stride0;
110
+		uint32_t vd1_stride1;
111
+		uint32_t vd1_stride2;
112
+		uint32_t vd1_height0;
113
+		uint32_t vd1_height1;
114
+		uint32_t vd1_height2;
115
+		uint32_t vd1_afbc_mode;
116
+		uint32_t vd1_afbc_en;
117
+		uint32_t vd1_afbc_head_addr;
118
+		uint32_t vd1_afbc_body_addr;
119
+		uint32_t vd1_afbc_conv_ctrl;
120
+		uint32_t vd1_afbc_dec_def_color;
121
+		uint32_t vd1_afbc_vd_cfmt_ctrl;
122
+		uint32_t vd1_afbc_vd_cfmt_w;
123
+		uint32_t vd1_afbc_vd_cfmt_h;
124
+		uint32_t vd1_afbc_mif_hor_scope;
125
+		uint32_t vd1_afbc_mif_ver_scope;
126
+		uint32_t vd1_afbc_size_out;
127
+		uint32_t vd1_afbc_pixel_hor_scope;
128
+		uint32_t vd1_afbc_pixel_ver_scope;
129
+		uint32_t vd1_afbc_size_in;
130
+		uint32_t vpp_pic_in_height;
131
+		uint32_t vpp_postblend_vd1_h_start_end;
132
+		uint32_t vpp_postblend_vd1_v_start_end;
133
+		uint32_t vpp_hsc_region12_startp;
134
+		uint32_t vpp_hsc_region34_startp;
135
+		uint32_t vpp_hsc_region4_endp;
136
+		uint32_t vpp_hsc_start_phase_step;
137
+		uint32_t vpp_hsc_region1_phase_slope;
138
+		uint32_t vpp_hsc_region3_phase_slope;
139
+		uint32_t vpp_line_in_length;
140
+		uint32_t vpp_preblend_h_size;
141
+		uint32_t vpp_vsc_region12_startp;
142
+		uint32_t vpp_vsc_region34_startp;
143
+		uint32_t vpp_vsc_region4_endp;
144
+		uint32_t vpp_vsc_start_phase_step;
145
+		uint32_t vpp_vsc_ini_phase;
146
+		uint32_t vpp_vsc_phase_ctrl;
147
+		uint32_t vpp_hsc_phase_ctrl;
148
+		uint32_t vpp_blend_vd2_h_start_end;
149
+		uint32_t vpp_blend_vd2_v_start_end;
49150 	} viu;
50151 
51152 	struct {
....@@ -54,12 +155,24 @@
54155 		bool venc_repeat;
55156 		bool hdmi_use_enci;
56157 	} venc;
158
+
159
+	struct {
160
+		dma_addr_t addr_dma;
161
+		uint32_t *addr;
162
+		unsigned int offset;
163
+	} rdma;
164
+
165
+	struct {
166
+		struct meson_afbcd_ops *ops;
167
+		u64 modifier;
168
+		u32 format;
169
+	} afbcd;
57170 };
58171 
59172 static inline int meson_vpu_is_compatible(struct meson_drm *priv,
60
-					  const char *compat)
173
+					  enum vpu_compatible family)
61174 {
62
-	return of_device_is_compatible(priv->dev->of_node, compat);
175
+	return priv->compat == family;
63176 }
64177 
65178 #endif /* __MESON_DRV_H */