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2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da 
 kernel/drivers/gpu/drm/meson/meson_drv.h
....@@ -1,51 +1,152 @@
1
+/* SPDX-License-Identifier: GPL-2.0-or-later */
12 /*
23  * Copyright (C) 2016 BayLibre, SAS
34  * Author: Neil Armstrong <narmstrong@baylibre.com>
4
- *
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- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License as
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- * published by the Free Software Foundation; either version 2 of the
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- * License, or (at your option) any later version.
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- *
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- * This program is distributed in the hope that it will be useful, but
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- * WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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- * General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program; if not, see <http://www.gnu.org/licenses/>.
175  */
186 
197 #ifndef __MESON_DRV_H
208 #define __MESON_DRV_H
219 
22
-#include <linux/platform_device.h>
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-#include <linux/regmap.h>
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+#include <linux/device.h>
2411 #include <linux/of.h>
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-#include <drm/drmP.h>
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+#include <linux/of_device.h>
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+#include <linux/regmap.h>
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+
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+struct drm_crtc;
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+struct drm_device;
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+struct drm_plane;
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+struct meson_drm;
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+struct meson_afbcd_ops;
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+
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+enum vpu_compatible {
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+	VPU_COMPATIBLE_GXBB = 0,
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+	VPU_COMPATIBLE_GXL  = 1,
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+	VPU_COMPATIBLE_GXM  = 2,
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+	VPU_COMPATIBLE_G12A = 3,
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+};
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+
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+struct meson_drm_match_data {
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+	enum vpu_compatible compat;
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+	struct meson_afbcd_ops *afbcd_ops;
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+};
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+
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+struct meson_drm_soc_limits {
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+	unsigned int max_hdmi_phy_freq;
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+};
2636 
2737 struct meson_drm {
2838 	struct device *dev;
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+	enum vpu_compatible compat;
2940 	void __iomem *io_base;
3041 	struct regmap *hhi;
31
-	struct regmap *dmc;
3242 	int vsync_irq;
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+
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+	struct meson_canvas *canvas;
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+	u8 canvas_id_osd1;
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+	u8 canvas_id_vd1_0;
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+	u8 canvas_id_vd1_1;
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+	u8 canvas_id_vd1_2;
3349 
3450 	struct drm_device *drm;
3551 	struct drm_crtc *crtc;
36
-	struct drm_fbdev_cma *fbdev;
3752 	struct drm_plane *primary_plane;
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+	struct drm_plane *overlay_plane;
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+
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+	const struct meson_drm_soc_limits *limits;
3856 
3957 	/* Components Data */
4058 	struct {
4159 		bool osd1_enabled;
4260 		bool osd1_interlace;
4361 		bool osd1_commit;
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+		bool osd1_afbcd;
4463 		uint32_t osd1_ctrl_stat;
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+		uint32_t osd1_ctrl_stat2;
4565 		uint32_t osd1_blk0_cfg[5];
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+		uint32_t osd1_blk1_cfg4;
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+		uint32_t osd1_blk2_cfg4;
4668 		uint32_t osd1_addr;
4769 		uint32_t osd1_stride;
4870 		uint32_t osd1_height;
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+		uint32_t osd1_width;
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+		uint32_t osd_sc_ctrl0;
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+		uint32_t osd_sc_i_wh_m1;
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+		uint32_t osd_sc_o_h_start_end;
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+		uint32_t osd_sc_o_v_start_end;
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+		uint32_t osd_sc_v_ini_phase;
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+		uint32_t osd_sc_v_phase_step;
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+		uint32_t osd_sc_h_ini_phase;
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+		uint32_t osd_sc_h_phase_step;
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+		uint32_t osd_sc_h_ctrl0;
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+		uint32_t osd_sc_v_ctrl0;
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+		uint32_t osd_blend_din0_scope_h;
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+		uint32_t osd_blend_din0_scope_v;
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+		uint32_t osb_blend0_size;
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+		uint32_t osb_blend1_size;
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+
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+		bool vd1_enabled;
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+		bool vd1_commit;
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+		bool vd1_afbc;
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+		unsigned int vd1_planes;
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+		uint32_t vd1_if0_gen_reg;
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+		uint32_t vd1_if0_luma_x0;
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+		uint32_t vd1_if0_luma_y0;
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+		uint32_t vd1_if0_chroma_x0;
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+		uint32_t vd1_if0_chroma_y0;
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+		uint32_t vd1_if0_repeat_loop;
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+		uint32_t vd1_if0_luma0_rpt_pat;
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+		uint32_t vd1_if0_chroma0_rpt_pat;
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+		uint32_t vd1_range_map_y;
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+		uint32_t vd1_range_map_cb;
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+		uint32_t vd1_range_map_cr;
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+		uint32_t viu_vd1_fmt_w;
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+		uint32_t vd1_if0_canvas0;
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+		uint32_t vd1_if0_gen_reg2;
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+		uint32_t viu_vd1_fmt_ctrl;
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+		uint32_t vd1_addr0;
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+		uint32_t vd1_addr1;
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+		uint32_t vd1_addr2;
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+		uint32_t vd1_stride0;
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+		uint32_t vd1_stride1;
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+		uint32_t vd1_stride2;
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+		uint32_t vd1_height0;
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+		uint32_t vd1_height1;
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+		uint32_t vd1_height2;
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+		uint32_t vd1_afbc_mode;
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+		uint32_t vd1_afbc_en;
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+		uint32_t vd1_afbc_head_addr;
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+		uint32_t vd1_afbc_body_addr;
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+		uint32_t vd1_afbc_conv_ctrl;
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+		uint32_t vd1_afbc_dec_def_color;
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+		uint32_t vd1_afbc_vd_cfmt_ctrl;
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+		uint32_t vd1_afbc_vd_cfmt_w;
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+		uint32_t vd1_afbc_vd_cfmt_h;
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+		uint32_t vd1_afbc_mif_hor_scope;
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+		uint32_t vd1_afbc_mif_ver_scope;
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+		uint32_t vd1_afbc_size_out;
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+		uint32_t vd1_afbc_pixel_hor_scope;
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+		uint32_t vd1_afbc_pixel_ver_scope;
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+		uint32_t vd1_afbc_size_in;
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+		uint32_t vpp_pic_in_height;
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+		uint32_t vpp_postblend_vd1_h_start_end;
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+		uint32_t vpp_postblend_vd1_v_start_end;
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+		uint32_t vpp_hsc_region12_startp;
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+		uint32_t vpp_hsc_region34_startp;
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+		uint32_t vpp_hsc_region4_endp;
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+		uint32_t vpp_hsc_start_phase_step;
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+		uint32_t vpp_hsc_region1_phase_slope;
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+		uint32_t vpp_hsc_region3_phase_slope;
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+		uint32_t vpp_line_in_length;
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+		uint32_t vpp_preblend_h_size;
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+		uint32_t vpp_vsc_region12_startp;
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+		uint32_t vpp_vsc_region34_startp;
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+		uint32_t vpp_vsc_region4_endp;
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+		uint32_t vpp_vsc_start_phase_step;
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+		uint32_t vpp_vsc_ini_phase;
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+		uint32_t vpp_vsc_phase_ctrl;
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+		uint32_t vpp_hsc_phase_ctrl;
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+		uint32_t vpp_blend_vd2_h_start_end;
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+		uint32_t vpp_blend_vd2_v_start_end;
49150 	} viu;
50151 
51152 	struct {
....@@ -54,12 +155,24 @@
54155 		bool venc_repeat;
55156 		bool hdmi_use_enci;
56157 	} venc;
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+
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+	struct {
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+		dma_addr_t addr_dma;
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+		uint32_t *addr;
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+		unsigned int offset;
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+	} rdma;
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+
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+	struct {
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+		struct meson_afbcd_ops *ops;
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+		u64 modifier;
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+		u32 format;
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+	} afbcd;
57170 };
58171 
59172 static inline int meson_vpu_is_compatible(struct meson_drm *priv,
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-					  const char *compat)
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+					  enum vpu_compatible family)
61174 {
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-	return of_device_is_compatible(priv->dev->of_node, compat);
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+	return priv->compat == family;
63176 }
64177 
65178 #endif /* __MESON_DRV_H */