.. | .. |
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43 | 43 | enum dpcd_downstream_port_type { |
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44 | 44 | DOWNSTREAM_DP = 0, |
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45 | 45 | DOWNSTREAM_VGA, |
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46 | | - DOWNSTREAM_DVI_HDMI, |
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| 46 | + DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS,/* DVI, HDMI, DP++ */ |
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47 | 47 | DOWNSTREAM_NONDDC /* has no EDID (TV,CV) */ |
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48 | 48 | }; |
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49 | 49 | |
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.. | .. |
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149 | 149 | PSR_SINK_STATE_SINK_INTERNAL_ERROR = 7, |
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150 | 150 | }; |
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151 | 151 | |
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| 152 | +#define DP_SOURCE_TABLE_REVISION 0x310 |
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| 153 | +#define DP_SOURCE_PAYLOAD_SIZE 0x311 |
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| 154 | +#define DP_SOURCE_SINK_CAP 0x317 |
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| 155 | +#define DP_SOURCE_BACKLIGHT_LEVEL 0x320 |
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| 156 | +#define DP_SOURCE_BACKLIGHT_CURRENT_PEAK 0x326 |
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| 157 | +#define DP_SOURCE_BACKLIGHT_CONTROL 0x32E |
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| 158 | +#define DP_SOURCE_BACKLIGHT_ENABLE 0x32F |
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| 159 | + |
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152 | 160 | #endif /* __DAL_DPCD_DEFS_H__ */ |
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