add wifi6 8852be driver

hc

2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da

 kernel/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
..
..
@@ -52,7 +52,7 @@
52
52
 
53
53
 /* macro to set register fields. */
54
54
 #define REG_SET_N(reg_name, n, initial_val, ...)	\
55
-		generic_reg_update_ex(CTX, \
55
+		generic_reg_set_ex(CTX, \
56
56
 				REG(reg_name), \
57
57
 				initial_val, \
58
58
 				n, __VA_ARGS__)
..
..
@@ -225,7 +225,6 @@
225
225
 #define REG_UPDATE_N(reg_name, n, ...)	\
226
226
 		generic_reg_update_ex(CTX, \
227
227
 				REG(reg_name), \
228
-				REG_READ(reg_name), \
229
228
 				n, __VA_ARGS__)
230
229
 
231
230
 #define REG_UPDATE(reg_name, field, val)	\
..
..
@@ -380,16 +379,11 @@
380
379
 /* macro to update a register field to specified values in given sequences.
381
380
  * useful when toggling bits
382
381
  */
383
-#define REG_UPDATE_SEQ(reg, field, value1, value2) \
384
-{	uint32_t val = REG_UPDATE(reg, field, value1); \
385
-	REG_SET(reg, val, field, value2); }
386
-
387
-/* macro to update fields in register 1 field at a time in given order */
388
-#define REG_UPDATE_1BY1_2(reg, f1, v1, f2, v2) \
382
+#define REG_UPDATE_SEQ_2(reg, f1, v1, f2, v2) \
389
383
 {	uint32_t val = REG_UPDATE(reg, f1, v1); \
390
384
 	REG_SET(reg, val, f2, v2); }
391
385
 
392
-#define REG_UPDATE_1BY1_3(reg, f1, v1, f2, v2, f3, v3) \
386
+#define REG_UPDATE_SEQ_3(reg, f1, v1, f2, v2, f3, v3) \
393
387
 {	uint32_t val = REG_UPDATE(reg, f1, v1); \
394
388
 	val = REG_SET(reg, val, f2, v2); \
395
389
 	REG_SET(reg, val, f3, v3); }
..
..
@@ -464,7 +458,14 @@
464
458
 #define IX_REG_READ(index_reg_name, data_reg_name, index) \
465
459
 		generic_read_indirect_reg(CTX, REG(index_reg_name), REG(data_reg_name), IND_REG(index))
466
460
 
461
+#define IX_REG_GET_N(index_reg_name, data_reg_name, index, n, ...) \
462
+		generic_indirect_reg_get(CTX, REG(index_reg_name), REG(data_reg_name), \
463
+				IND_REG(index), \
464
+				n, __VA_ARGS__)
467
465
 
466
+#define IX_REG_GET(index_reg_name, data_reg_name, index, field, val) \
467
+		IX_REG_GET_N(index_reg_name, data_reg_name, index, 1, \
468
+				FN(data_reg_name, field), val)
468
469
 
469
470
 #define IX_REG_UPDATE_N(index_reg_name, data_reg_name, index, n, ...)	\
470
471
 		generic_indirect_reg_update_ex(CTX, \
..
..
@@ -485,10 +486,35 @@
485
486
 		uint32_t addr_index, uint32_t addr_data,
486
487
 		uint32_t index);
487
488
 
489
+uint32_t generic_indirect_reg_get(const struct dc_context *ctx,
490
+		uint32_t addr_index, uint32_t addr_data,
491
+		uint32_t index, int n,
492
+		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
493
+		...);
494
+
488
495
 uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx,
489
496
 		uint32_t addr_index, uint32_t addr_data,
490
497
 		uint32_t index, uint32_t reg_val, int n,
491
498
 		uint8_t shift1, uint32_t mask1, uint32_t field_value1,
492
499
 		...);
493
500
 
501
+/* register offload macros
502
+ *
503
+ * instead of MMIO to register directly, in some cases we want
504
+ * to gather register sequence and execute the register sequence
505
+ * from another thread so we optimize time required for lengthy ops
506
+ */
507
+
508
+/* start gathering register sequence */
509
+#define REG_SEQ_START() \
510
+	reg_sequence_start_gather(CTX)
511
+
512
+/* start execution of register sequence gathered since REG_SEQ_START */
513
+#define REG_SEQ_SUBMIT() \
514
+	reg_sequence_start_execute(CTX)
515
+
516
+/* wait for the last REG_SEQ_SUBMIT to finish */
517
+#define REG_SEQ_WAIT_DONE() \
518
+	reg_sequence_wait_done(CTX)
519
+
494
520
 #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_ */