add wifi6 8852be driver

hc

2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da

 kernel/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h
..
..
@@ -48,6 +48,12 @@
48
48
 	DDC_GPIO_REG_LIST(cd,id),\
49
49
 	.ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP)
50
50
 
51
+	#define DDC_REG_LIST_DCN2(cd, id) \
52
+	DDC_GPIO_REG_LIST(cd, id),\
53
+	.ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP),\
54
+	.phy_aux_cntl = REG(PHY_AUX_CNTL), \
55
+	.dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5)
56
+
51
57
 #define DDC_GPIO_VGA_REG_LIST_ENTRY(type,cd)\
52
58
 	.type ## _reg =   REG(DC_GPIO_DDCVGA_ ## type),\
53
59
 	.type ## _mask =  DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## _MASK,\
..
..
@@ -82,6 +88,11 @@
82
88
 	DDC_GPIO_I2C_REG_LIST(cd),\
83
89
 	.ddc_setup = 0
84
90
 
91
+#define DDC_I2C_REG_LIST_DCN2(cd) \
92
+	DDC_GPIO_I2C_REG_LIST(cd),\
93
+	.ddc_setup = 0,\
94
+	.phy_aux_cntl = REG(PHY_AUX_CNTL), \
95
+	.dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5)
85
96
 #define DDC_MASK_SH_LIST_COMMON(mask_sh) \
86
97
 		SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE, mask_sh),\
87
98
 		SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_EDID_DETECT_ENABLE, mask_sh),\
..
..
@@ -95,10 +106,18 @@
95
106
 		SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SDA_PD_DIS, mask_sh),\
96
107
 		SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SCL_PD_DIS, mask_sh)
97
108
 
109
+#define DDC_MASK_SH_LIST_DCN2(mask_sh, cd) \
110
+	{DDC_MASK_SH_LIST_COMMON(mask_sh),\
111
+	0,\
112
+	0,\
113
+	(PHY_AUX_CNTL__AUX## cd ##_PAD_RXSEL## mask_sh),\
114
+	(DC_GPIO_AUX_CTRL_5__DDC_PAD## cd ##_I2CMODE## mask_sh)}
98
115
 
99
116
 struct ddc_registers {
100
117
 	struct gpio_registers gpio;
101
118
 	uint32_t ddc_setup;
119
+	uint32_t phy_aux_cntl;
120
+	uint32_t dc_gpio_aux_ctrl_5;
102
121
 };
103
122
 
104
123
 struct ddc_sh_mask {
..
..
@@ -113,6 +132,9 @@
113
132
 	/* i2cpad_mask */
114
133
 	uint32_t DC_GPIO_SDA_PD_DIS;
115
134
 	uint32_t DC_GPIO_SCL_PD_DIS;
135
+	//phy_aux_cntl
136
+	uint32_t AUX_PAD_RXSEL;
137
+	uint32_t DDC_PAD_I2CMODE;
116
138
 };
117
139
 
118
140
 
..
..
@@ -148,6 +170,25 @@
148
170
 {\
149
171
 	DDC_I2C_REG_LIST(SCL)\
150
172
 }
173
+#define ddc_data_regs_dcn2(id) \
174
+{\
175
+	DDC_REG_LIST_DCN2(DATA, id)\
176
+}
177
+
178
+#define ddc_clk_regs_dcn2(id) \
179
+{\
180
+	DDC_REG_LIST_DCN2(CLK, id)\
181
+}
182
+
183
+#define ddc_i2c_data_regs_dcn2 \
184
+{\
185
+	DDC_I2C_REG_LIST_DCN2(SDA)\
186
+}
187
+
188
+#define ddc_i2c_clk_regs_dcn2 \
189
+{\
190
+	DDC_REG_LIST_DCN2(SCL)\
191
+}
151
192
 
152
193
 
153
194
 #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_ */