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2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da

 kernel/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
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@@ -22,6 +22,10 @@
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  * Authors: AMD
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  *
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  */
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+
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+#include "dc_features.h"
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+#include "display_mode_enums.h"
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+
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 #ifndef __DISPLAY_MODE_STRUCTS_H__
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 #define __DISPLAY_MODE_STRUCTS_H__
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31
 
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@@ -30,22 +34,15 @@
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 typedef struct _vcs_dpi_ip_params_st ip_params_st;
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 typedef struct _vcs_dpi_display_pipe_source_params_st display_pipe_source_params_st;
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 typedef struct _vcs_dpi_display_output_params_st display_output_params_st;
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-typedef struct _vcs_dpi_display_bandwidth_st display_bandwidth_st;
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 typedef struct _vcs_dpi_scaler_ratio_depth_st scaler_ratio_depth_st;
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 typedef struct _vcs_dpi_scaler_taps_st scaler_taps_st;
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 typedef struct _vcs_dpi_display_pipe_dest_params_st display_pipe_dest_params_st;
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 typedef struct _vcs_dpi_display_pipe_params_st display_pipe_params_st;
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 typedef struct _vcs_dpi_display_clocks_and_cfg_st display_clocks_and_cfg_st;
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 typedef struct _vcs_dpi_display_e2e_pipe_params_st display_e2e_pipe_params_st;
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-typedef struct _vcs_dpi_dchub_buffer_sizing_st dchub_buffer_sizing_st;
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-typedef struct _vcs_dpi_watermarks_perf_st watermarks_perf_st;
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-typedef struct _vcs_dpi_cstate_pstate_watermarks_st cstate_pstate_watermarks_st;
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-typedef struct _vcs_dpi_wm_calc_pipe_params_st wm_calc_pipe_params_st;
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-typedef struct _vcs_dpi_vratio_pre_st vratio_pre_st;
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 typedef struct _vcs_dpi_display_data_rq_misc_params_st display_data_rq_misc_params_st;
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 typedef struct _vcs_dpi_display_data_rq_sizing_params_st display_data_rq_sizing_params_st;
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 typedef struct _vcs_dpi_display_data_rq_dlg_params_st display_data_rq_dlg_params_st;
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-typedef struct _vcs_dpi_display_cur_rq_dlg_params_st display_cur_rq_dlg_params_st;
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 typedef struct _vcs_dpi_display_rq_dlg_params_st display_rq_dlg_params_st;
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 typedef struct _vcs_dpi_display_rq_sizing_params_st display_rq_sizing_params_st;
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 typedef struct _vcs_dpi_display_rq_misc_params_st display_rq_misc_params_st;
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@@ -55,8 +52,6 @@
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 typedef struct _vcs_dpi_display_data_rq_regs_st display_data_rq_regs_st;
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 typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st;
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 typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st;
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-typedef struct _vcs_dpi_display_dlg_prefetch_param_st display_dlg_prefetch_param_st;
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-typedef struct _vcs_dpi_display_pipe_clock_st display_pipe_clock_st;
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 typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st;
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 struct _vcs_dpi_voltage_scaling_st {
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@@ -64,14 +59,19 @@
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 	double dscclk_mhz;
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 	double dcfclk_mhz;
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 	double socclk_mhz;
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+	double phyclk_d18_mhz;
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 	double dram_speed_mts;
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 	double fabricclk_mhz;
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 	double dispclk_mhz;
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+	double dram_bw_per_chan_gbps;
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 	double phyclk_mhz;
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 	double dppclk_mhz;
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+	double dtbclk_mhz;
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 };
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 struct _vcs_dpi_soc_bounding_box_st {
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+	struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
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+	unsigned int num_states;
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 	double sr_exit_time_us;
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 	double sr_enter_plus_exit_time_us;
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 	double urgent_latency_us;
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@@ -83,6 +83,7 @@
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 	double pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly
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 	double pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;
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 	double pct_ideal_dram_sdp_bw_after_urgent_vm_only;
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+	double pct_ideal_sdp_bw_after_urgent;
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 	double max_avg_sdp_bw_use_normal_percent;
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 	double max_avg_dram_bw_use_normal_percent;
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 	unsigned int max_request_size_bytes;
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@@ -104,21 +105,33 @@
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 	unsigned int num_banks;
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 	unsigned int num_chans;
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 	unsigned int vmm_page_size_bytes;
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+	unsigned int hostvm_min_page_size_bytes;
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+	unsigned int gpuvm_min_page_size_bytes;
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 	double dram_clock_change_latency_us;
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+	double dummy_pstate_latency_us;
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 	double writeback_dram_clock_change_latency_us;
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 	unsigned int return_bus_width_bytes;
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 	unsigned int voltage_override;
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 	double xfc_bus_transport_time_us;
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 	double xfc_xbuf_latency_tolerance_us;
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 	int use_urgent_burst_bw;
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-	double max_hscl_ratio;
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-	double max_vscl_ratio;
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-	struct _vcs_dpi_voltage_scaling_st clock_limits[7];
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+	double min_dcfclk;
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+	bool do_urgent_latency_adjustment;
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+	double urgent_latency_adjustment_fabric_clock_component_us;
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+	double urgent_latency_adjustment_fabric_clock_reference_mhz;
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+	bool disable_dram_clock_change_vactive_support;
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+	bool allow_dram_clock_one_display_vactive;
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+	enum self_refresh_affinity allow_dram_self_refresh_or_dram_clock_change_in_vblank;
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 };
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 struct _vcs_dpi_ip_params_st {
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+	bool use_min_dcfclk;
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+#ifdef CONFIG_DRM_AMD_DC_DCN3_0
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+	bool clamp_min_dcfclk;
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+#endif
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 	bool gpuvm_enable;
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 	bool hostvm_enable;
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+	bool dsc422_native_support;
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 	unsigned int gpuvm_max_page_table_levels;
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 	unsigned int hostvm_max_page_table_levels;
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 	unsigned int hostvm_cached_page_table_levels;
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@@ -128,7 +141,8 @@
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 	unsigned int odm_capable;
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 	unsigned int rob_buffer_size_kbytes;
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 	unsigned int det_buffer_size_kbytes;
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-	unsigned int dpte_buffer_size_in_pte_reqs;
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+	unsigned int dpte_buffer_size_in_pte_reqs_luma;
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+	unsigned int dpte_buffer_size_in_pte_reqs_chroma;
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 	unsigned int pde_proc_buffer_size_64k_reqs;
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 	unsigned int dpp_output_buffer_pixels;
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 	unsigned int opp_output_buffer_lines;
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@@ -136,12 +150,28 @@
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 	unsigned char pte_enable;
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 	unsigned int pte_chunk_size_kbytes;
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 	unsigned int meta_chunk_size_kbytes;
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+	unsigned int min_meta_chunk_size_bytes;
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 	unsigned int writeback_chunk_size_kbytes;
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 	unsigned int line_buffer_size_bits;
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 	unsigned int max_line_buffer_lines;
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 	unsigned int writeback_luma_buffer_size_kbytes;
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 	unsigned int writeback_chroma_buffer_size_kbytes;
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 	unsigned int writeback_chroma_line_buffer_width_pixels;
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+
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+	unsigned int writeback_interface_buffer_size_kbytes;
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+	unsigned int writeback_line_buffer_buffer_size;
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+
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+	unsigned int writeback_10bpc420_supported;
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+	double writeback_max_hscl_ratio;
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+	double writeback_max_vscl_ratio;
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+	double writeback_min_hscl_ratio;
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+	double writeback_min_vscl_ratio;
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+	double maximum_dsc_bits_per_component;
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+	unsigned int writeback_max_hscl_taps;
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+	unsigned int writeback_max_vscl_taps;
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+	unsigned int writeback_line_buffer_luma_buffer_size;
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+	unsigned int writeback_line_buffer_chroma_buffer_size;
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+
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 	unsigned int max_page_table_levels;
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 	unsigned int max_num_dpp;
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 	unsigned int max_num_otg;
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@@ -159,6 +189,13 @@
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 	unsigned int max_hscl_taps;
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 	unsigned int max_vscl_taps;
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 	unsigned int xfc_supported;
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+	unsigned int ptoi_supported;
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+	unsigned int gfx7_compat_tiling_supported;
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+
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+	bool odm_combine_4to1_supported;
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+	bool dynamic_metadata_vm_enabled;
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+	unsigned int max_num_hdmi_frl_outputs;
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+
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 	unsigned int xfc_fill_constant_bytes;
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 	double dispclk_ramp_margin_percent;
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 	double xfc_fill_bw_overhead_percent;
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@@ -166,7 +203,7 @@
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 	unsigned int min_vblank_lines;
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 	unsigned int dppclk_delay_subtotal;
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 	unsigned int dispclk_delay_subtotal;
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-	unsigned int dcfclk_cstate_latency;
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+	double dcfclk_cstate_latency;
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 	unsigned int dppclk_delay_scl;
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 	unsigned int dppclk_delay_scl_lb_only;
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 	unsigned int dppclk_delay_cnvc_formatter;
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@@ -179,6 +216,7 @@
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 	unsigned int LineBufferFixedBpp;
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 	unsigned int can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
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 	unsigned int bug_forcing_LC_req_same_size_fixed;
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+	unsigned int number_of_cursors;
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 };
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 struct _vcs_dpi_display_xfc_params_st {
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@@ -190,11 +228,14 @@
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 struct _vcs_dpi_display_pipe_source_params_st {
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 	int source_format;
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+	double dcc_fraction_of_zs_req_luma;
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+	double dcc_fraction_of_zs_req_chroma;
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 	unsigned char dcc;
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-	unsigned int dcc_override;
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 	unsigned int dcc_rate;
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+	unsigned int dcc_rate_chroma;
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 	unsigned char dcc_use_global;
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 	unsigned char vm;
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+	bool unbounded_req_mode;
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 	bool gpuvm;    // gpuvm enabled
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 	bool hostvm;    // hostvm enabled
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 	bool gpuvm_levels_force_en;
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@@ -204,7 +245,10 @@
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 	int source_scan;
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 	int sw_mode;
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 	int macro_tile_size;
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-	unsigned char is_display_sw;
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+	unsigned int surface_width_y;
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+	unsigned int surface_height_y;
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+	unsigned int surface_width_c;
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+	unsigned int surface_height_c;
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 	unsigned int viewport_width;
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 	unsigned int viewport_height;
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 	unsigned int viewport_y_y;
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@@ -227,10 +271,15 @@
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 	unsigned int hsplit_grp;
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 	unsigned char xfc_enable;
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 	unsigned char xfc_slave;
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+	unsigned char immediate_flip;
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 	struct _vcs_dpi_display_xfc_params_st xfc_params;
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+	//for vstartuplines calculation freesync
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+	unsigned char v_total_min;
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+	unsigned char v_total_max;
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 };
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 struct writeback_st {
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 	int wb_src_height;
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+	int wb_src_width;
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 	int wb_dst_width;
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 	int wb_dst_height;
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 	int wb_pixel_format;
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@@ -244,21 +293,16 @@
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 struct _vcs_dpi_display_output_params_st {
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 	int dp_lanes;
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-	int output_bpp;
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+	double output_bpp;
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 	int dsc_enable;
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 	int wb_enable;
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 	int num_active_wb;
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 	int output_bpc;
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 	int output_type;
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 	int output_format;
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-	int output_standard;
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 	int dsc_slices;
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+	int max_audio_sample_rate;
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 	struct writeback_st wb;
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-};
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-
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-struct _vcs_dpi_display_bandwidth_st {
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-	double total_bw_consumed_gbps;
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-	double guaranteed_urgent_return_bw_gbps;
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 };
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 struct _vcs_dpi_scaler_ratio_depth_st {
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@@ -292,6 +336,8 @@
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 	unsigned int vblank_end;
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 	unsigned int htotal;
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 	unsigned int vtotal;
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+	unsigned int refresh_rate;
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+	unsigned int vfront_porch;
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 	unsigned int vactive;
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 	unsigned int hactive;
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 	unsigned int vstartup_start;
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@@ -299,13 +345,14 @@
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 	unsigned int vupdate_width;
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 	unsigned int vready_offset;
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 	unsigned char interlaced;
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-	unsigned char underscan;
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 	double pixel_rate_mhz;
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 	unsigned char synchronized_vblank_all_planes;
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+	unsigned char synchronize_timing_if_single_refresh_rate;
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 	unsigned char otg_inst;
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-	unsigned char odm_split_cnt;
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-	unsigned char odm_combine;
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+	unsigned int odm_combine;
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 	unsigned char use_maximum_vstartup;
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+	unsigned int vtotal_max;
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+	unsigned int vtotal_min;
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 };
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 struct _vcs_dpi_display_pipe_params_st {
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@@ -328,65 +375,6 @@
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 	display_pipe_params_st pipe;
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 	display_output_params_st dout;
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 	display_clocks_and_cfg_st clks_cfg;
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-};
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-
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-struct _vcs_dpi_dchub_buffer_sizing_st {
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-	unsigned int swath_width_y;
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-	unsigned int swath_height_y;
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-	unsigned int swath_height_c;
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-	unsigned int detail_buffer_size_y;
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-};
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-
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-struct _vcs_dpi_watermarks_perf_st {
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-	double stutter_eff_in_active_region_percent;
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-	double urgent_latency_supported_us;
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-	double non_urgent_latency_supported_us;
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-	double dram_clock_change_margin_us;
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-	double dram_access_eff_percent;
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-};
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-
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-struct _vcs_dpi_cstate_pstate_watermarks_st {
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-	double cstate_exit_us;
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-	double cstate_enter_plus_exit_us;
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-	double pstate_change_us;
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-};
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-
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-struct _vcs_dpi_wm_calc_pipe_params_st {
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-	unsigned int num_dpp;
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-	int voltage;
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-	int output_type;
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-	double dcfclk_mhz;
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-	double socclk_mhz;
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-	double dppclk_mhz;
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-	double pixclk_mhz;
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-	unsigned char interlace_en;
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-	unsigned char pte_enable;
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-	unsigned char dcc_enable;
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-	double dcc_rate;
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-	double bytes_per_pixel_c;
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-	double bytes_per_pixel_y;
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-	unsigned int swath_width_y;
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-	unsigned int swath_height_y;
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-	unsigned int swath_height_c;
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-	unsigned int det_buffer_size_y;
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-	double h_ratio;
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-	double v_ratio;
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-	unsigned int h_taps;
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-	unsigned int h_total;
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-	unsigned int v_total;
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-	unsigned int v_active;
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-	unsigned int e2e_index;
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-	double display_pipe_line_delivery_time;
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-	double read_bw;
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-	unsigned int lines_in_det_y;
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-	unsigned int lines_in_det_y_rounded_down_to_swath;
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-	double full_det_buffering_time;
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-	double dcfclk_deepsleep_mhz_per_plane;
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-};
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-
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-struct _vcs_dpi_vratio_pre_st {
388
-	double vratio_pre_l;
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-	double vratio_pre_c;
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 };
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 struct _vcs_dpi_display_data_rq_misc_params_st {
..
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@@ -422,16 +410,9 @@
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 	unsigned int meta_bytes_per_row_ub;
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 };
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425
-struct _vcs_dpi_display_cur_rq_dlg_params_st {
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-	unsigned char enable;
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-	unsigned int swath_height;
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-	unsigned int req_per_line;
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-};
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-
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 struct _vcs_dpi_display_rq_dlg_params_st {
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 	display_data_rq_dlg_params_st rq_l;
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 	display_data_rq_dlg_params_st rq_c;
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-	display_cur_rq_dlg_params_st rq_cur0;
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 };
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 struct _vcs_dpi_display_rq_sizing_params_st {
..
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@@ -447,6 +428,7 @@
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 struct _vcs_dpi_display_rq_params_st {
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 	unsigned char yuv420;
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430
 	unsigned char yuv420_10bpc;
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+	unsigned char rgbe_alpha;
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 	display_rq_misc_params_st misc;
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 	display_rq_sizing_params_st sizing;
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 	display_rq_dlg_params_st dlg;
..
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@@ -497,6 +479,12 @@
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 	unsigned int xfc_reg_remote_surface_flip_latency;
498
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 	unsigned int xfc_reg_prefetch_margin;
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481
 	unsigned int dst_y_delta_drq_limit;
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+	unsigned int refcyc_per_vm_group_vblank;
483
+	unsigned int refcyc_per_vm_group_flip;
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+	unsigned int refcyc_per_vm_req_vblank;
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+	unsigned int refcyc_per_vm_req_flip;
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+	unsigned int refcyc_per_vm_dmdata;
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+	unsigned int dmdata_dl_delta;
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 };
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502
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 struct _vcs_dpi_display_ttu_regs_st {
..
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@@ -553,19 +541,6 @@
553
541
 	double deepsleep_dcfclk_mhz;
554
542
 	double total_flip_bw;
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543
 	unsigned int total_flip_bytes;
556
-};
557
-
558
-struct _vcs_dpi_display_dlg_prefetch_param_st {
559
-	double prefetch_bw;
560
-	unsigned int flip_bytes;
561
-};
562
-
563
-struct _vcs_dpi_display_pipe_clock_st {
564
-	double dcfclk_mhz;
565
-	double dispclk_mhz;
566
-	double socclk_mhz;
567
-	double dscclk_mhz[6];
568
-	double dppclk_mhz[6];
569
544
 };
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545
 
571
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 struct _vcs_dpi_display_arb_params_st {