forked from ~ljy/RK356X_SDK_RELEASE

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hc
2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da 
 kernel/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
....@@ -81,13 +81,16 @@
8181 	SRI(DP_MSE_RATE_UPDATE, DP, id), \
8282 	SRI(DP_PIXEL_FORMAT, DP, id), \
8383 	SRI(DP_SEC_CNTL, DP, id), \
84
+	SRI(DP_SEC_CNTL2, DP, id), \
85
+	SRI(DP_SEC_CNTL6, DP, id), \
8486 	SRI(DP_STEER_FIFO, DP, id), \
8587 	SRI(DP_VID_M, DP, id), \
8688 	SRI(DP_VID_N, DP, id), \
8789 	SRI(DP_VID_STREAM_CNTL, DP, id), \
8890 	SRI(DP_VID_TIMING, DP, id), \
8991 	SRI(DP_SEC_AUD_N, DP, id), \
90
-	SRI(DP_SEC_TIMESTAMP, DP, id)
92
+	SRI(DP_SEC_TIMESTAMP, DP, id), \
93
+	SRI(DIG_CLOCK_PATTERN, DIG, id)
9194 
9295 #define SE_DCN_REG_LIST(id)\
9396 	SE_COMMON_DCN_REG_LIST(id)
....@@ -118,10 +121,13 @@
118121 	uint32_t AFMT_60958_1;
119122 	uint32_t AFMT_60958_2;
120123 	uint32_t DIG_FE_CNTL;
124
+	uint32_t DIG_FE_CNTL2;
121125 	uint32_t DP_MSE_RATE_CNTL;
122126 	uint32_t DP_MSE_RATE_UPDATE;
123127 	uint32_t DP_PIXEL_FORMAT;
124128 	uint32_t DP_SEC_CNTL;
129
+	uint32_t DP_SEC_CNTL2;
130
+	uint32_t DP_SEC_CNTL6;
125131 	uint32_t DP_STEER_FIFO;
126132 	uint32_t DP_VID_M;
127133 	uint32_t DP_VID_N;
....@@ -150,12 +156,28 @@
150156 	uint32_t HDMI_ACR_48_1;
151157 	uint32_t DP_DB_CNTL;
152158 	uint32_t DP_MSA_MISC;
159
+	uint32_t DP_MSA_VBID_MISC;
153160 	uint32_t DP_MSA_COLORIMETRY;
154161 	uint32_t DP_MSA_TIMING_PARAM1;
155162 	uint32_t DP_MSA_TIMING_PARAM2;
156163 	uint32_t DP_MSA_TIMING_PARAM3;
157164 	uint32_t DP_MSA_TIMING_PARAM4;
158165 	uint32_t HDMI_DB_CONTROL;
166
+	uint32_t DP_DSC_CNTL;
167
+	uint32_t DP_DSC_BYTES_PER_PIXEL;
168
+	uint32_t DME_CONTROL;
169
+	uint32_t DP_SEC_METADATA_TRANSMISSION;
170
+	uint32_t HDMI_METADATA_PACKET_CONTROL;
171
+	uint32_t DP_SEC_FRAMING4;
172
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
173
+	uint32_t DP_GSP11_CNTL;
174
+	uint32_t HDMI_GENERIC_PACKET_CONTROL6;
175
+	uint32_t HDMI_GENERIC_PACKET_CONTROL7;
176
+	uint32_t HDMI_GENERIC_PACKET_CONTROL8;
177
+	uint32_t HDMI_GENERIC_PACKET_CONTROL9;
178
+	uint32_t HDMI_GENERIC_PACKET_CONTROL10;
179
+#endif
180
+	uint32_t DIG_CLOCK_PATTERN;
159181 };
160182 
161183 
....@@ -175,6 +197,7 @@
175197 	SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
176198 	SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
177199 	SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
200
+	SE_SF(DIG0_HDMI_CONTROL, HDMI_NO_EXTRA_NULL_PACKET_FILLED, mask_sh),\
178201 	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
179202 	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\
180203 	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\
....@@ -191,6 +214,10 @@
191214 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
192215 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
193216 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
217
+	SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND, mask_sh),\
218
+	SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING, mask_sh),\
219
+	SE_SF(DP0_DP_SEC_CNTL4, DP_SEC_GSP4_LINE_NUM, mask_sh),\
220
+	SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, mask_sh),\
194221 	SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
195222 	SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
196223 	SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\
....@@ -245,6 +272,7 @@
245272 	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE_PENDING, mask_sh),\
246273 	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE_PENDING, mask_sh),\
247274 	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE_PENDING, mask_sh),\
275
+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING, mask_sh),\
248276 	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE_PENDING, mask_sh),\
249277 	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE_PENDING, mask_sh),\
250278 	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE_PENDING, mask_sh),\
....@@ -253,6 +281,14 @@
253281 	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE, mask_sh),\
254282 	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE, mask_sh),\
255283 	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE, mask_sh),\
284
+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_IMMEDIATE_UPDATE, mask_sh),\
285
+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_IMMEDIATE_UPDATE, mask_sh),\
286
+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_IMMEDIATE_UPDATE, mask_sh),\
287
+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_IMMEDIATE_UPDATE, mask_sh),\
288
+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE, mask_sh),\
289
+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_IMMEDIATE_UPDATE, mask_sh),\
290
+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_IMMEDIATE_UPDATE, mask_sh),\
291
+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_IMMEDIATE_UPDATE, mask_sh),\
256292 	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE, mask_sh),\
257293 	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE, mask_sh),\
258294 	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, mask_sh),\
....@@ -260,6 +296,9 @@
260296 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
261297 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\
262298 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\
299
+	SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP7_PPS, mask_sh),\
300
+	SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP7_SEND, mask_sh),\
301
+	SE_SF(DP0_DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, mask_sh),\
263302 	SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\
264303 	SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\
265304 	SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\
....@@ -273,7 +312,9 @@
273312 	SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\
274313 	SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\
275314 	SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\
276
-	SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh)
315
+	SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\
316
+	SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh),\
317
+	SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh)
277318 
278319 #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\
279320 	SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)
....@@ -302,6 +343,7 @@
302343 	type AFMT_GENERIC2_FRAME_UPDATE_PENDING;\
303344 	type AFMT_GENERIC3_FRAME_UPDATE_PENDING;\
304345 	type AFMT_GENERIC4_FRAME_UPDATE_PENDING;\
346
+	type AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING;\
305347 	type AFMT_GENERIC5_FRAME_UPDATE_PENDING;\
306348 	type AFMT_GENERIC6_FRAME_UPDATE_PENDING;\
307349 	type AFMT_GENERIC7_FRAME_UPDATE_PENDING;\
....@@ -310,6 +352,14 @@
310352 	type AFMT_GENERIC2_FRAME_UPDATE;\
311353 	type AFMT_GENERIC3_FRAME_UPDATE;\
312354 	type AFMT_GENERIC4_FRAME_UPDATE;\
355
+	type AFMT_GENERIC0_IMMEDIATE_UPDATE;\
356
+	type AFMT_GENERIC1_IMMEDIATE_UPDATE;\
357
+	type AFMT_GENERIC2_IMMEDIATE_UPDATE;\
358
+	type AFMT_GENERIC3_IMMEDIATE_UPDATE;\
359
+	type AFMT_GENERIC4_IMMEDIATE_UPDATE;\
360
+	type AFMT_GENERIC5_IMMEDIATE_UPDATE;\
361
+	type AFMT_GENERIC6_IMMEDIATE_UPDATE;\
362
+	type AFMT_GENERIC7_IMMEDIATE_UPDATE;\
313363 	type AFMT_GENERIC5_FRAME_UPDATE;\
314364 	type AFMT_GENERIC6_FRAME_UPDATE;\
315365 	type AFMT_GENERIC7_FRAME_UPDATE;\
....@@ -348,6 +398,7 @@
348398 	type HDMI_GC_SEND;\
349399 	type HDMI_NULL_SEND;\
350400 	type HDMI_DATA_SCRAMBLE_EN;\
401
+	type HDMI_NO_EXTRA_NULL_PACKET_FILLED;\
351402 	type HDMI_AUDIO_INFO_SEND;\
352403 	type AFMT_AUDIO_INFO_UPDATE;\
353404 	type HDMI_AUDIO_INFO_LINE;\
....@@ -364,6 +415,12 @@
364415 	type DP_SEC_GSP5_ENABLE;\
365416 	type DP_SEC_GSP6_ENABLE;\
366417 	type DP_SEC_GSP7_ENABLE;\
418
+	type DP_SEC_GSP7_PPS;\
419
+	type DP_SEC_GSP7_SEND;\
420
+	type DP_SEC_GSP4_SEND;\
421
+	type DP_SEC_GSP4_SEND_PENDING;\
422
+	type DP_SEC_GSP4_LINE_NUM;\
423
+	type DP_SEC_GSP4_SEND_ANY_LINE;\
367424 	type DP_SEC_MPG_ENABLE;\
368425 	type DP_VID_STREAM_DIS_DEFER;\
369426 	type DP_VID_STREAM_ENABLE;\
....@@ -404,6 +461,7 @@
404461 	type DP_SEC_ATP_ENABLE;\
405462 	type DP_SEC_AIP_ENABLE;\
406463 	type DP_SEC_ACM_ENABLE;\
464
+	type DP_SEC_GSP7_LINE_NUM;\
407465 	type AFMT_AUDIO_SAMPLE_SEND;\
408466 	type AFMT_AUDIO_CLOCK_EN;\
409467 	type TMDS_PIXEL_ENCODING;\
....@@ -424,14 +482,71 @@
424482 	type DP_MSA_VHEIGHT;\
425483 	type HDMI_DB_DISABLE;\
426484 	type DP_VID_N_MUL;\
427
-	type DP_VID_M_DOUBLE_VALUE_EN
485
+	type DP_VID_M_DOUBLE_VALUE_EN;\
486
+	type DIG_SOURCE_SELECT;\
487
+	type DIG_CLOCK_PATTERN
488
+
489
+#define SE_REG_FIELD_LIST_DCN2_0(type) \
490
+	type DP_DSC_MODE;\
491
+	type DP_DSC_SLICE_WIDTH;\
492
+	type DP_DSC_BYTES_PER_PIXEL;\
493
+	type DP_VBID6_LINE_REFERENCE;\
494
+	type DP_VBID6_LINE_NUM;\
495
+	type METADATA_ENGINE_EN;\
496
+	type METADATA_HUBP_REQUESTOR_ID;\
497
+	type METADATA_STREAM_TYPE;\
498
+	type DP_SEC_METADATA_PACKET_ENABLE;\
499
+	type DP_SEC_METADATA_PACKET_LINE_REFERENCE;\
500
+	type DP_SEC_METADATA_PACKET_LINE;\
501
+	type HDMI_METADATA_PACKET_ENABLE;\
502
+	type HDMI_METADATA_PACKET_LINE_REFERENCE;\
503
+	type HDMI_METADATA_PACKET_LINE;\
504
+	type DOLBY_VISION_EN;\
505
+	type DP_PIXEL_COMBINE;\
506
+	type DP_SST_SDP_SPLITTING
507
+
508
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
509
+#define SE_REG_FIELD_LIST_DCN3_0(type) \
510
+	type HDMI_GENERIC8_CONT;\
511
+	type HDMI_GENERIC8_SEND;\
512
+	type HDMI_GENERIC8_LINE;\
513
+	type HDMI_GENERIC9_CONT;\
514
+	type HDMI_GENERIC9_SEND;\
515
+	type HDMI_GENERIC9_LINE;\
516
+	type HDMI_GENERIC10_CONT;\
517
+	type HDMI_GENERIC10_SEND;\
518
+	type HDMI_GENERIC10_LINE;\
519
+	type HDMI_GENERIC11_CONT;\
520
+	type HDMI_GENERIC11_SEND;\
521
+	type HDMI_GENERIC11_LINE;\
522
+	type HDMI_GENERIC12_CONT;\
523
+	type HDMI_GENERIC12_SEND;\
524
+	type HDMI_GENERIC12_LINE;\
525
+	type HDMI_GENERIC13_CONT;\
526
+	type HDMI_GENERIC13_SEND;\
527
+	type HDMI_GENERIC13_LINE;\
528
+	type HDMI_GENERIC14_CONT;\
529
+	type HDMI_GENERIC14_SEND;\
530
+	type HDMI_GENERIC14_LINE;\
531
+	type DP_SEC_GSP11_PPS;\
532
+	type DP_SEC_GSP11_ENABLE;\
533
+	type DP_SEC_GSP11_LINE_NUM
534
+#endif
428535 
429536 struct dcn10_stream_encoder_shift {
430537 	SE_REG_FIELD_LIST_DCN1_0(uint8_t);
538
+	SE_REG_FIELD_LIST_DCN2_0(uint8_t);
539
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
540
+	SE_REG_FIELD_LIST_DCN3_0(uint8_t);
541
+#endif
431542 };
432543 
433544 struct dcn10_stream_encoder_mask {
434545 	SE_REG_FIELD_LIST_DCN1_0(uint32_t);
546
+	SE_REG_FIELD_LIST_DCN2_0(uint32_t);
547
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
548
+	SE_REG_FIELD_LIST_DCN3_0(uint32_t);
549
+#endif
435550 };
436551 
437552 struct dcn10_stream_encoder {
....@@ -458,7 +573,9 @@
458573 void enc1_stream_encoder_dp_set_stream_attribute(
459574 	struct stream_encoder *enc,
460575 	struct dc_crtc_timing *crtc_timing,
461
-	enum dc_color_space output_color_space);
576
+	enum dc_color_space output_color_space,
577
+	bool use_vsc_sdp_for_colorimetry,
578
+	uint32_t enable_sdp_splitting);
462579 
463580 void enc1_stream_encoder_hdmi_set_stream_attribute(
464581 	struct stream_encoder *enc,
....@@ -471,13 +588,18 @@
471588 	struct dc_crtc_timing *crtc_timing,
472589 	bool is_dual_link);
473590 
474
-void enc1_stream_encoder_set_mst_bandwidth(
591
+void enc1_stream_encoder_set_throttled_vcp_size(
475592 	struct stream_encoder *enc,
476593 	struct fixed31_32 avg_time_slots_per_mtp);
477594 
478595 void enc1_stream_encoder_update_dp_info_packets(
479596 	struct stream_encoder *enc,
480597 	const struct encoder_info_frame *info_frame);
598
+
599
+void enc1_stream_encoder_send_immediate_sdp_message(
600
+	struct stream_encoder *enc,
601
+	const uint8_t *custom_sdp_message,
602
+				unsigned int sdp_message_size);
481603 
482604 void enc1_stream_encoder_stop_dp_info_packets(
483605 	struct stream_encoder *enc);
....@@ -521,4 +643,36 @@
521643 void enc1_se_hdmi_audio_disable(
522644 	struct stream_encoder *enc);
523645 
646
+void enc1_dig_connect_to_otg(
647
+	struct stream_encoder *enc,
648
+	int tg_inst);
649
+
650
+unsigned int enc1_dig_source_otg(
651
+	struct stream_encoder *enc);
652
+
653
+void enc1_stream_encoder_set_stream_attribute_helper(
654
+	struct dcn10_stream_encoder *enc1,
655
+	struct dc_crtc_timing *crtc_timing);
656
+
657
+void enc1_se_enable_audio_clock(
658
+	struct stream_encoder *enc,
659
+	bool enable);
660
+
661
+void enc1_se_enable_dp_audio(
662
+	struct stream_encoder *enc);
663
+
664
+void get_audio_clock_info(
665
+	enum dc_color_depth color_depth,
666
+	uint32_t crtc_pixel_clock_100Hz,
667
+	uint32_t actual_pixel_clock_100Hz,
668
+	struct audio_clock_info *audio_clock_info);
669
+
670
+void enc1_reset_hdmi_stream_attribute(
671
+	struct stream_encoder *enc);
672
+
673
+bool enc1_stream_encoder_dp_get_pixel_format(
674
+	struct stream_encoder *enc,
675
+	enum dc_pixel_encoding *encoding,
676
+	enum dc_color_depth *depth);
677
+
524678 #endif /* __DC_STREAM_ENCODER_DCN10_H__ */