forked from ~ljy/RK356X_SDK_RELEASE

blame | history | patch | commit | commitdiff
hc
2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da 
 kernel/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
....@@ -23,6 +23,7 @@
2323  *
2424  */
2525 
26
+#include <linux/delay.h>
2627 
2728 #include "dc_bios_types.h"
2829 #include "dcn10_stream_encoder.h"
....@@ -120,35 +121,35 @@
120121 	switch (packet_index) {
121122 	case 0:
122123 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
123
-				AFMT_GENERIC0_FRAME_UPDATE, 1);
124
+				AFMT_GENERIC0_IMMEDIATE_UPDATE, 1);
124125 		break;
125126 	case 1:
126127 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
127
-				AFMT_GENERIC1_FRAME_UPDATE, 1);
128
+				AFMT_GENERIC1_IMMEDIATE_UPDATE, 1);
128129 		break;
129130 	case 2:
130131 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
131
-				AFMT_GENERIC2_FRAME_UPDATE, 1);
132
+				AFMT_GENERIC2_IMMEDIATE_UPDATE, 1);
132133 		break;
133134 	case 3:
134135 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
135
-				AFMT_GENERIC3_FRAME_UPDATE, 1);
136
+				AFMT_GENERIC3_IMMEDIATE_UPDATE, 1);
136137 		break;
137138 	case 4:
138139 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
139
-				AFMT_GENERIC4_FRAME_UPDATE, 1);
140
+				AFMT_GENERIC4_IMMEDIATE_UPDATE, 1);
140141 		break;
141142 	case 5:
142143 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
143
-				AFMT_GENERIC5_FRAME_UPDATE, 1);
144
+				AFMT_GENERIC5_IMMEDIATE_UPDATE, 1);
144145 		break;
145146 	case 6:
146147 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
147
-				AFMT_GENERIC6_FRAME_UPDATE, 1);
148
+				AFMT_GENERIC6_IMMEDIATE_UPDATE, 1);
148149 		break;
149150 	case 7:
150151 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
151
-				AFMT_GENERIC7_FRAME_UPDATE, 1);
152
+				AFMT_GENERIC7_IMMEDIATE_UPDATE, 1);
152153 		break;
153154 	default:
154155 		break;
....@@ -245,7 +246,9 @@
245246 void enc1_stream_encoder_dp_set_stream_attribute(
246247 	struct stream_encoder *enc,
247248 	struct dc_crtc_timing *crtc_timing,
248
-	enum dc_color_space output_color_space)
249
+	enum dc_color_space output_color_space,
250
+	bool use_vsc_sdp_for_colorimetry,
251
+	uint32_t enable_sdp_splitting)
249252 {
250253 	uint32_t h_active_start;
251254 	uint32_t v_active_start;
....@@ -261,17 +264,29 @@
261264 	uint8_t dp_component_depth = 0;
262265 
263266 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
267
+	struct dc_crtc_timing hw_crtc_timing = *crtc_timing;
268
+
269
+	if (hw_crtc_timing.flags.INTERLACE) {
270
+		/*the input timing is in VESA spec format with Interlace flag =1*/
271
+		hw_crtc_timing.v_total /= 2;
272
+		hw_crtc_timing.v_border_top /= 2;
273
+		hw_crtc_timing.v_addressable /= 2;
274
+		hw_crtc_timing.v_border_bottom /= 2;
275
+		hw_crtc_timing.v_front_porch /= 2;
276
+		hw_crtc_timing.v_sync_width /= 2;
277
+	}
278
+
264279 
265280 	/* set pixel encoding */
266
-	switch (crtc_timing->pixel_encoding) {
281
+	switch (hw_crtc_timing.pixel_encoding) {
267282 	case PIXEL_ENCODING_YCBCR422:
268283 		dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR422;
269284 		break;
270285 	case PIXEL_ENCODING_YCBCR444:
271286 		dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR444;
272287 
273
-		if (crtc_timing->flags.Y_ONLY)
274
-			if (crtc_timing->display_color_depth != COLOR_DEPTH_666)
288
+		if (hw_crtc_timing.flags.Y_ONLY)
289
+			if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666)
275290 				/* HW testing only, no use case yet.
276291 				 * Color depth of Y-only could be
277292 				 * 8, 10, 12, 16 bits
....@@ -286,7 +301,6 @@
286301 		break;
287302 	case PIXEL_ENCODING_YCBCR420:
288303 		dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR420;
289
-		REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
290304 		break;
291305 	default:
292306 		dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_RGB444;
....@@ -299,16 +313,13 @@
299313 	 * Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7,
300314 	 * and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care").
301315 	 */
302
-	if ((crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) ||
303
-			(output_color_space == COLOR_SPACE_2020_YCBCR) ||
304
-			(output_color_space == COLOR_SPACE_2020_RGB_FULLRANGE) ||
305
-			(output_color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE))
316
+	if (use_vsc_sdp_for_colorimetry)
306317 		misc1 = misc1 | 0x40;
307318 	else
308319 		misc1 = misc1 & ~0x40;
309320 
310321 	/* set color depth */
311
-	switch (crtc_timing->display_color_depth) {
322
+	switch (hw_crtc_timing.display_color_depth) {
312323 	case COLOR_DEPTH_666:
313324 		dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC;
314325 		break;
....@@ -336,7 +347,7 @@
336347 
337348 	/* set dynamic range and YCbCr range */
338349 
339
-	switch (crtc_timing->display_color_depth) {
350
+	switch (hw_crtc_timing.display_color_depth) {
340351 	case COLOR_DEPTH_666:
341352 		colorimetry_bpc = 0;
342353 		break;
....@@ -372,9 +383,9 @@
372383 		misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
373384 		misc1 = misc1 & ~0x80; /* bit7 = 0*/
374385 		dynamic_range_ycbcr = 0; /*bt601*/
375
-		if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
386
+		if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
376387 			misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
377
-		else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
388
+		else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
378389 			misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
379390 		break;
380391 	case COLOR_SPACE_YCBCR709:
....@@ -382,9 +393,9 @@
382393 		misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
383394 		misc1 = misc1 & ~0x80; /* bit7 = 0*/
384395 		dynamic_range_ycbcr = 1; /*bt709*/
385
-		if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
396
+		if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
386397 			misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
387
-		else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
398
+		else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
388399 			misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
389400 		break;
390401 	case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
....@@ -403,6 +414,7 @@
403414 	case COLOR_SPACE_APPCTRL:
404415 	case COLOR_SPACE_CUSTOMPOINTS:
405416 	case COLOR_SPACE_UNKNOWN:
417
+	case COLOR_SPACE_YCBCR709_BLACK:
406418 		/* do nothing */
407419 		break;
408420 	}
....@@ -414,26 +426,26 @@
414426 	 * dc_crtc_timing is vesa dmt struct. data from edid
415427 	 */
416428 	REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
417
-			DP_MSA_HTOTAL, crtc_timing->h_total,
418
-			DP_MSA_VTOTAL, crtc_timing->v_total);
429
+			DP_MSA_HTOTAL, hw_crtc_timing.h_total,
430
+			DP_MSA_VTOTAL, hw_crtc_timing.v_total);
419431 
420432 	/* calculate from vesa timing parameters
421433 	 * h_active_start related to leading edge of sync
422434 	 */
423435 
424
-	h_blank = crtc_timing->h_total - crtc_timing->h_border_left -
425
-			crtc_timing->h_addressable - crtc_timing->h_border_right;
436
+	h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left -
437
+			hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right;
426438 
427
-	h_back_porch = h_blank - crtc_timing->h_front_porch -
428
-			crtc_timing->h_sync_width;
439
+	h_back_porch = h_blank - hw_crtc_timing.h_front_porch -
440
+			hw_crtc_timing.h_sync_width;
429441 
430442 	/* start at beginning of left border */
431
-	h_active_start = crtc_timing->h_sync_width + h_back_porch;
443
+	h_active_start = hw_crtc_timing.h_sync_width + h_back_porch;
432444 
433445 
434
-	v_active_start = crtc_timing->v_total - crtc_timing->v_border_top -
435
-			crtc_timing->v_addressable - crtc_timing->v_border_bottom -
436
-			crtc_timing->v_front_porch;
446
+	v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top -
447
+			hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom -
448
+			hw_crtc_timing.v_front_porch;
437449 
438450 
439451 	/* start at beginning of left border */
....@@ -443,23 +455,23 @@
443455 
444456 	REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
445457 			DP_MSA_HSYNCWIDTH,
446
-			crtc_timing->h_sync_width,
458
+			hw_crtc_timing.h_sync_width,
447459 			DP_MSA_HSYNCPOLARITY,
448
-			!crtc_timing->flags.HSYNC_POSITIVE_POLARITY,
460
+			!hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY,
449461 			DP_MSA_VSYNCWIDTH,
450
-			crtc_timing->v_sync_width,
462
+			hw_crtc_timing.v_sync_width,
451463 			DP_MSA_VSYNCPOLARITY,
452
-			!crtc_timing->flags.VSYNC_POSITIVE_POLARITY);
464
+			!hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY);
453465 
454466 	/* HWDITH include border or overscan */
455467 	REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
456
-		DP_MSA_HWIDTH, crtc_timing->h_border_left +
457
-		crtc_timing->h_addressable + crtc_timing->h_border_right,
458
-		DP_MSA_VHEIGHT, crtc_timing->v_border_top +
459
-		crtc_timing->v_addressable + crtc_timing->v_border_bottom);
468
+		DP_MSA_HWIDTH, hw_crtc_timing.h_border_left +
469
+		hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right,
470
+		DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top +
471
+		hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom);
460472 }
461473 
462
-static void enc1_stream_encoder_set_stream_attribute_helper(
474
+void enc1_stream_encoder_set_stream_attribute_helper(
463475 		struct dcn10_stream_encoder *enc1,
464476 		struct dc_crtc_timing *crtc_timing)
465477 {
....@@ -498,11 +510,12 @@
498510 	enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
499511 
500512 	/* setup HDMI engine */
501
-	REG_UPDATE_5(HDMI_CONTROL,
513
+	REG_UPDATE_6(HDMI_CONTROL,
502514 		HDMI_PACKET_GEN_VERSION, 1,
503515 		HDMI_KEEPOUT_MODE, 1,
504516 		HDMI_DEEP_COLOR_ENABLE, 0,
505517 		HDMI_DATA_SCRAMBLE_EN, 0,
518
+		HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1,
506519 		HDMI_CLOCK_CHANNEL_RATE, 0);
507520 
508521 
....@@ -594,7 +607,7 @@
594607 	cntl.signal = is_dual_link ?
595608 			SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
596609 	cntl.enable_dp_audio = false;
597
-	cntl.pixel_clock = crtc_timing->pix_clk_khz;
610
+	cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
598611 	cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
599612 
600613 	if (enc1->base.bp->funcs->encoder_control(
....@@ -606,7 +619,7 @@
606619 	enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
607620 }
608621 
609
-void enc1_stream_encoder_set_mst_bandwidth(
622
+void enc1_stream_encoder_set_throttled_vcp_size(
610623 	struct stream_encoder *enc,
611624 	struct fixed31_32 avg_time_slots_per_mtp)
612625 {
....@@ -714,6 +727,10 @@
714727 				3,  /* packetIndex */
715728 				&info_frame->hdrsmd);
716729 
730
+	/* packetIndex 4 is used for send immediate sdp message, and please
731
+	 * use other packetIndex (such as 5,6) for other info packet
732
+	 */
733
+
717734 	/* enable/disable transmission of packet(s).
718735 	 * If enabled, packet transmission begins on the next frame
719736 	 */
....@@ -721,6 +738,100 @@
721738 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
722739 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
723740 
741
+
742
+	/* This bit is the master enable bit.
743
+	 * When enabling secondary stream engine,
744
+	 * this master bit must also be set.
745
+	 * This register shared with audio info frame.
746
+	 * Therefore we need to enable master bit
747
+	 * if at least on of the fields is not 0
748
+	 */
749
+	value = REG_READ(DP_SEC_CNTL);
750
+	if (value)
751
+		REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
752
+}
753
+
754
+void enc1_stream_encoder_send_immediate_sdp_message(
755
+	struct stream_encoder *enc,
756
+	const uint8_t *custom_sdp_message,
757
+	unsigned int sdp_message_size)
758
+{
759
+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
760
+	uint32_t value = 0;
761
+
762
+	/* TODOFPGA Figure out a proper number for max_retries polling for lock
763
+	 * use 50 for now.
764
+	 */
765
+	uint32_t max_retries = 50;
766
+
767
+	/* check if GSP4 is transmitted */
768
+	REG_WAIT(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING,
769
+		0, 10, max_retries);
770
+
771
+	/* disable GSP4 transmitting */
772
+	REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 0);
773
+
774
+	/* transmit GSP4 at the earliest time in a frame */
775
+	REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, 1);
776
+
777
+	/*we need turn on clock before programming AFMT block*/
778
+	REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
779
+
780
+	/* check if HW reading GSP memory */
781
+	REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
782
+			0, 10, max_retries);
783
+
784
+	/* HW does is not reading GSP memory not reading too long ->
785
+	 * something wrong. clear GPS memory access and notify?
786
+	 * hw SW is writing to GSP memory
787
+	 */
788
+	REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
789
+
790
+	/* use generic packet 4 for immediate sdp message */
791
+	REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
792
+			AFMT_GENERIC_INDEX, 4);
793
+
794
+	/* write generic packet header
795
+	 * (4th byte is for GENERIC0 only)
796
+	 */
797
+	REG_SET_4(AFMT_GENERIC_HDR, 0,
798
+			AFMT_GENERIC_HB0, custom_sdp_message[0],
799
+			AFMT_GENERIC_HB1, custom_sdp_message[1],
800
+			AFMT_GENERIC_HB2, custom_sdp_message[2],
801
+			AFMT_GENERIC_HB3, custom_sdp_message[3]);
802
+
803
+	/* write generic packet contents
804
+	 * (we never use last 4 bytes)
805
+	 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers
806
+	 */
807
+	{
808
+		const uint32_t *content =
809
+			(const uint32_t *) &custom_sdp_message[4];
810
+
811
+		REG_WRITE(AFMT_GENERIC_0, *content++);
812
+		REG_WRITE(AFMT_GENERIC_1, *content++);
813
+		REG_WRITE(AFMT_GENERIC_2, *content++);
814
+		REG_WRITE(AFMT_GENERIC_3, *content++);
815
+		REG_WRITE(AFMT_GENERIC_4, *content++);
816
+		REG_WRITE(AFMT_GENERIC_5, *content++);
817
+		REG_WRITE(AFMT_GENERIC_6, *content++);
818
+		REG_WRITE(AFMT_GENERIC_7, *content);
819
+	}
820
+
821
+	/* check whether GENERIC4 registers double buffer update in immediate mode
822
+	 * is pending
823
+	 */
824
+	REG_WAIT(AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING,
825
+			0, 10, max_retries);
826
+
827
+	/* atomically update double-buffered GENERIC4 registers in immediate mode
828
+	 * (update immediately)
829
+	 */
830
+	REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
831
+			AFMT_GENERIC4_IMMEDIATE_UPDATE, 1);
832
+
833
+	/* enable GSP4 transmitting */
834
+	REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 1);
724835 
725836 	/* This bit is the master enable bit.
726837 	 * When enabling secondary stream engine,
....@@ -766,7 +877,6 @@
766877 	struct stream_encoder *enc)
767878 {
768879 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
769
-	uint32_t retries = 0;
770880 	uint32_t  reg1 = 0;
771881 	uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
772882 
....@@ -786,10 +896,10 @@
786896 	 */
787897 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
788898 	/* Larger delay to wait until VBLANK - use max retry of
789
-	 * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
899
+	 * 10us*10200=102ms. This covers 100.0ms of minimum 10 Hz mode +
790900 	 * a little more because we may not trust delay accuracy.
791901 	 */
792
-	max_retries = DP_BLANK_MAX_RETRY * 150;
902
+	max_retries = DP_BLANK_MAX_RETRY * 501;
793903 
794904 	/* disable DP stream */
795905 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
....@@ -802,8 +912,6 @@
802912 	REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
803913 			0,
804914 			10, max_retries);
805
-
806
-	ASSERT(retries <= max_retries);
807915 
808916 	/* Tell the DP encoder to ignore timing from CRTC, must be done after
809917 	 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
....@@ -824,14 +932,19 @@
824932 	if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
825933 		uint32_t n_vid = 0x8000;
826934 		uint32_t m_vid;
935
+		uint32_t n_multiply = 0;
936
+		uint64_t m_vid_l = n_vid;
827937 
938
+		/* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
939
+		if (param->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
940
+			/*this param->pixel_clk_khz is half of 444 rate for 420 already*/
941
+			n_multiply = 1;
942
+		}
828943 		/* M / N = Fstream / Flink
829944 		 * m_vid / n_vid = pixel rate / link rate
830945 		 */
831946 
832
-		uint64_t m_vid_l = n_vid;
833
-
834
-		m_vid_l *= param->pixel_clk_khz;
947
+		m_vid_l *= param->timing.pix_clk_100hz / 10;
835948 		m_vid_l = div_u64(m_vid_l,
836949 			param->link_settings.link_rate
837950 				* LINK_RATE_REF_FREQ_IN_KHZ);
....@@ -850,7 +963,9 @@
850963 
851964 		REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
852965 
853
-		REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);
966
+		REG_UPDATE_2(DP_VID_TIMING,
967
+				DP_VID_M_N_GEN_EN, 1,
968
+				DP_VID_N_MUL, n_multiply);
854969 	}
855970 
856971 	/* set DIG_START to 0x1 to resync FIFO */
....@@ -885,6 +1000,19 @@
8851000 	unsigned int value = enable ? 1 : 0;
8861001 
8871002 	REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
1003
+}
1004
+
1005
+void enc1_reset_hdmi_stream_attribute(
1006
+	struct stream_encoder *enc)
1007
+{
1008
+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1009
+
1010
+	REG_UPDATE_5(HDMI_CONTROL,
1011
+		HDMI_PACKET_GEN_VERSION, 1,
1012
+		HDMI_KEEPOUT_MODE, 1,
1013
+		HDMI_DEEP_COLOR_ENABLE, 0,
1014
+		HDMI_DATA_SCRAMBLE_EN, 0,
1015
+		HDMI_CLOCK_CHANNEL_RATE, 0);
8881016 }
8891017 
8901018 
....@@ -974,19 +1102,6 @@
9741102 		uint32_t RC_RLC_FLC:1;
9751103 		uint32_t RRC_FRC:1;
9761104 	} channels;
977
-};
978
-
979
-struct audio_clock_info {
980
-	/* pixel clock frequency*/
981
-	uint32_t pixel_clock_in_10khz;
982
-	/* N - 32KHz audio */
983
-	uint32_t n_32khz;
984
-	/* CTS - 32KHz audio*/
985
-	uint32_t cts_32khz;
986
-	uint32_t n_44khz;
987
-	uint32_t cts_44khz;
988
-	uint32_t n_48khz;
989
-	uint32_t cts_48khz;
9901105 };
9911106 
9921107 /* 25.2MHz/1.001*/
....@@ -1091,15 +1206,15 @@
10911206 	return cea_channels;
10921207 }
10931208 
1094
-static void get_audio_clock_info(
1209
+void get_audio_clock_info(
10951210 	enum dc_color_depth color_depth,
1096
-	uint32_t crtc_pixel_clock_in_khz,
1097
-	uint32_t actual_pixel_clock_in_khz,
1211
+	uint32_t crtc_pixel_clock_100Hz,
1212
+	uint32_t actual_pixel_clock_100Hz,
10981213 	struct audio_clock_info *audio_clock_info)
10991214 {
11001215 	const struct audio_clock_info *clock_info;
11011216 	uint32_t index;
1102
-	uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10;
1217
+	uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100;
11031218 	uint32_t audio_array_size;
11041219 
11051220 	switch (color_depth) {
....@@ -1136,16 +1251,16 @@
11361251 	}
11371252 
11381253 	/* not found */
1139
-	if (actual_pixel_clock_in_khz == 0)
1140
-		actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz;
1254
+	if (actual_pixel_clock_100Hz == 0)
1255
+		actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz;
11411256 
11421257 	/* See HDMI spec  the table entry under
11431258 	 *  pixel clock of "Other". */
11441259 	audio_clock_info->pixel_clock_in_10khz =
1145
-			actual_pixel_clock_in_khz / 10;
1146
-	audio_clock_info->cts_32khz = actual_pixel_clock_in_khz;
1147
-	audio_clock_info->cts_44khz = actual_pixel_clock_in_khz;
1148
-	audio_clock_info->cts_48khz = actual_pixel_clock_in_khz;
1260
+			actual_pixel_clock_100Hz / 100;
1261
+	audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10;
1262
+	audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10;
1263
+	audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10;
11491264 
11501265 	audio_clock_info->n_32khz = 4096;
11511266 	audio_clock_info->n_44khz = 6272;
....@@ -1159,7 +1274,6 @@
11591274 {
11601275 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
11611276 
1162
-	uint32_t speakers = 0;
11631277 	uint32_t channels = 0;
11641278 
11651279 	ASSERT(audio_info);
....@@ -1167,7 +1281,6 @@
11671281 		/* This should not happen.it does so we don't get BSOD*/
11681282 		return;
11691283 
1170
-	speakers = audio_info->flags.info.ALLSPEAKERS;
11711284 	channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
11721285 
11731286 	/* setup the audio stream source select (audio -> dig mapping) */
....@@ -1205,14 +1318,14 @@
12051318 
12061319 	/* Program audio clock sample/regeneration parameters */
12071320 	get_audio_clock_info(crtc_info->color_depth,
1208
-			     crtc_info->requested_pixel_clock,
1209
-			     crtc_info->calculated_pixel_clock,
1321
+			     crtc_info->requested_pixel_clock_100Hz,
1322
+			     crtc_info->calculated_pixel_clock_100Hz,
12101323 			     &audio_clock_info);
12111324 	DC_LOG_HW_AUDIO(
1212
-			"\n%s:Input::requested_pixel_clock = %d"	\
1213
-			"calculated_pixel_clock = %d \n", __func__,	\
1214
-			crtc_info->requested_pixel_clock,		\
1215
-			crtc_info->calculated_pixel_clock);
1325
+			"\n%s:Input::requested_pixel_clock_100Hz = %d"	\
1326
+			"calculated_pixel_clock_100Hz = %d \n", __func__,	\
1327
+			crtc_info->requested_pixel_clock_100Hz,		\
1328
+			crtc_info->calculated_pixel_clock_100Hz);
12161329 
12171330 	/* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
12181331 	REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
....@@ -1295,7 +1408,7 @@
12951408 	REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
12961409 }
12971410 
1298
-static void enc1_se_enable_audio_clock(
1411
+void enc1_se_enable_audio_clock(
12991412 	struct stream_encoder *enc,
13001413 	bool enable)
13011414 {
....@@ -1317,7 +1430,7 @@
13171430 	 */
13181431 }
13191432 
1320
-static void enc1_se_enable_dp_audio(
1433
+void enc1_se_enable_dp_audio(
13211434 	struct stream_encoder *enc)
13221435 {
13231436 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
....@@ -1416,6 +1529,85 @@
14161529 	REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
14171530 }
14181531 
1532
+void enc1_dig_connect_to_otg(
1533
+	struct stream_encoder *enc,
1534
+	int tg_inst)
1535
+{
1536
+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1537
+
1538
+	REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
1539
+}
1540
+
1541
+unsigned int enc1_dig_source_otg(
1542
+	struct stream_encoder *enc)
1543
+{
1544
+	uint32_t tg_inst = 0;
1545
+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1546
+
1547
+	REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst);
1548
+
1549
+	return tg_inst;
1550
+}
1551
+
1552
+bool enc1_stream_encoder_dp_get_pixel_format(
1553
+	struct stream_encoder *enc,
1554
+	enum dc_pixel_encoding *encoding,
1555
+	enum dc_color_depth *depth)
1556
+{
1557
+	uint32_t hw_encoding = 0;
1558
+	uint32_t hw_depth = 0;
1559
+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1560
+
1561
+	if (enc == NULL ||
1562
+		encoding == NULL ||
1563
+		depth == NULL)
1564
+		return false;
1565
+
1566
+	REG_GET_2(DP_PIXEL_FORMAT,
1567
+		DP_PIXEL_ENCODING, &hw_encoding,
1568
+		DP_COMPONENT_DEPTH, &hw_depth);
1569
+
1570
+	switch (hw_depth) {
1571
+	case DP_COMPONENT_PIXEL_DEPTH_6BPC:
1572
+		*depth = COLOR_DEPTH_666;
1573
+		break;
1574
+	case DP_COMPONENT_PIXEL_DEPTH_8BPC:
1575
+		*depth = COLOR_DEPTH_888;
1576
+		break;
1577
+	case DP_COMPONENT_PIXEL_DEPTH_10BPC:
1578
+		*depth = COLOR_DEPTH_101010;
1579
+		break;
1580
+	case DP_COMPONENT_PIXEL_DEPTH_12BPC:
1581
+		*depth = COLOR_DEPTH_121212;
1582
+		break;
1583
+	case DP_COMPONENT_PIXEL_DEPTH_16BPC:
1584
+		*depth = COLOR_DEPTH_161616;
1585
+		break;
1586
+	default:
1587
+		*depth = COLOR_DEPTH_UNDEFINED;
1588
+		break;
1589
+	}
1590
+
1591
+	switch (hw_encoding) {
1592
+	case DP_PIXEL_ENCODING_TYPE_RGB444:
1593
+		*encoding = PIXEL_ENCODING_RGB;
1594
+		break;
1595
+	case DP_PIXEL_ENCODING_TYPE_YCBCR422:
1596
+		*encoding = PIXEL_ENCODING_YCBCR422;
1597
+		break;
1598
+	case DP_PIXEL_ENCODING_TYPE_YCBCR444:
1599
+	case DP_PIXEL_ENCODING_TYPE_Y_ONLY:
1600
+		*encoding = PIXEL_ENCODING_YCBCR444;
1601
+		break;
1602
+	case DP_PIXEL_ENCODING_TYPE_YCBCR420:
1603
+		*encoding = PIXEL_ENCODING_YCBCR420;
1604
+		break;
1605
+	default:
1606
+		*encoding = PIXEL_ENCODING_UNDEFINED;
1607
+		break;
1608
+	}
1609
+	return true;
1610
+}
14191611 
14201612 static const struct stream_encoder_funcs dcn10_str_enc_funcs = {
14211613 	.dp_set_stream_attribute =
....@@ -1424,14 +1616,16 @@
14241616 		enc1_stream_encoder_hdmi_set_stream_attribute,
14251617 	.dvi_set_stream_attribute =
14261618 		enc1_stream_encoder_dvi_set_stream_attribute,
1427
-	.set_mst_bandwidth =
1428
-		enc1_stream_encoder_set_mst_bandwidth,
1619
+	.set_throttled_vcp_size =
1620
+		enc1_stream_encoder_set_throttled_vcp_size,
14291621 	.update_hdmi_info_packets =
14301622 		enc1_stream_encoder_update_hdmi_info_packets,
14311623 	.stop_hdmi_info_packets =
14321624 		enc1_stream_encoder_stop_hdmi_info_packets,
14331625 	.update_dp_info_packets =
14341626 		enc1_stream_encoder_update_dp_info_packets,
1627
+	.send_immediate_sdp_message =
1628
+		enc1_stream_encoder_send_immediate_sdp_message,
14351629 	.stop_dp_info_packets =
14361630 		enc1_stream_encoder_stop_dp_info_packets,
14371631 	.dp_blank =
....@@ -1448,6 +1642,11 @@
14481642 	.hdmi_audio_disable = enc1_se_hdmi_audio_disable,
14491643 	.setup_stereo_sync  = enc1_setup_stereo_sync,
14501644 	.set_avmute = enc1_stream_encoder_set_avmute,
1645
+	.dig_connect_to_otg  = enc1_dig_connect_to_otg,
1646
+	.hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
1647
+	.dig_source_otg = enc1_dig_source_otg,
1648
+
1649
+	.dp_get_pixel_format  = enc1_stream_encoder_dp_get_pixel_format,
14511650 };
14521651 
14531652 void dcn10_stream_encoder_construct(
....@@ -1466,5 +1665,6 @@
14661665 	enc1->regs = regs;
14671666 	enc1->se_shift = se_shift;
14681667 	enc1->se_mask = se_mask;
1668
+	enc1->base.stream_enc_inst = eng_id - ENGINE_ID_DIGA;
14691669 }
14701670