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2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da 
 kernel/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
....@@ -24,6 +24,8 @@
2424  *
2525  */
2626 
27
+#include <linux/slab.h>
28
+
2729 #include "dm_services.h"
2830 
2931 
....@@ -31,6 +33,7 @@
3133 #include "resource.h"
3234 #include "include/irq_service_interface.h"
3335 #include "dce120_resource.h"
36
+
3437 #include "dce112/dce112_resource.h"
3538 
3639 #include "dce110/dce110_resource.h"
....@@ -39,14 +42,14 @@
3942 #include "irq/dce120/irq_service_dce120.h"
4043 #include "dce/dce_opp.h"
4144 #include "dce/dce_clock_source.h"
42
-#include "dce/dce_clocks.h"
4345 #include "dce/dce_ipp.h"
4446 #include "dce/dce_mem_input.h"
47
+#include "dce/dce_panel_cntl.h"
4548 
4649 #include "dce110/dce110_hw_sequencer.h"
4750 #include "dce120/dce120_hw_sequencer.h"
4851 #include "dce/dce_transform.h"
49
-
52
+#include "clk_mgr.h"
5053 #include "dce/dce_audio.h"
5154 #include "dce/dce_link_encoder.h"
5255 #include "dce/dce_stream_encoder.h"
....@@ -54,12 +57,15 @@
5457 #include "dce/dce_abm.h"
5558 #include "dce/dce_dmcu.h"
5659 #include "dce/dce_aux.h"
60
+#include "dce/dce_i2c.h"
5761 
5862 #include "dce/dce_12_0_offset.h"
5963 #include "dce/dce_12_0_sh_mask.h"
6064 #include "soc15_hw_ip.h"
6165 #include "vega10_ip_offset.h"
6266 #include "nbio/nbio_6_1_offset.h"
67
+#include "mmhub/mmhub_1_0_offset.h"
68
+#include "mmhub/mmhub_1_0_sh_mask.h"
6369 #include "reg_helper.h"
6470 
6571 #include "dce100/dce100_resource.h"
....@@ -136,6 +142,17 @@
136142 #define SRI(reg_name, block, id)\
137143 	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
138144 					mm ## block ## id ## _ ## reg_name
145
+
146
+/* MMHUB */
147
+#define MMHUB_BASE_INNER(seg) \
148
+	MMHUB_BASE__INST0_SEG ## seg
149
+
150
+#define MMHUB_BASE(seg) \
151
+	MMHUB_BASE_INNER(seg)
152
+
153
+#define MMHUB_SR(reg_name)\
154
+		.reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) +  \
155
+					mm ## reg_name
139156 
140157 /* macros to expend register list macro defined in HW object header file
141158  * end *********************/
....@@ -277,6 +294,26 @@
277294 		SE_COMMON_MASK_SH_LIST_DCE120(_MASK)
278295 };
279296 
297
+static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
298
+	{ DCE_PANEL_CNTL_REG_LIST() }
299
+};
300
+
301
+static const struct dce_panel_cntl_shift panel_cntl_shift = {
302
+	DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
303
+};
304
+
305
+static const struct dce_panel_cntl_mask panel_cntl_mask = {
306
+	DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
307
+};
308
+
309
+static const struct dce110_aux_registers_shift aux_shift = {
310
+	DCE12_AUX_MASK_SH_LIST(__SHIFT)
311
+};
312
+
313
+static const struct dce110_aux_registers_mask aux_mask = {
314
+	DCE12_AUX_MASK_SH_LIST(_MASK)
315
+};
316
+
280317 #define opp_regs(id)\
281318 [id] = {\
282319 	OPP_DCE_120_REG_LIST(id),\
....@@ -324,7 +361,8 @@
324361 	audio_regs(2),
325362 	audio_regs(3),
326363 	audio_regs(4),
327
-	audio_regs(5)
364
+	audio_regs(5),
365
+	audio_regs(6),
328366 };
329367 
330368 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
....@@ -336,9 +374,40 @@
336374 		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
337375 };
338376 
339
-static const struct dce_aduio_mask audio_mask = {
377
+static const struct dce_audio_mask audio_mask = {
340378 		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
341379 };
380
+
381
+static int map_transmitter_id_to_phy_instance(
382
+	enum transmitter transmitter)
383
+{
384
+	switch (transmitter) {
385
+	case TRANSMITTER_UNIPHY_A:
386
+		return 0;
387
+	break;
388
+	case TRANSMITTER_UNIPHY_B:
389
+		return 1;
390
+	break;
391
+	case TRANSMITTER_UNIPHY_C:
392
+		return 2;
393
+	break;
394
+	case TRANSMITTER_UNIPHY_D:
395
+		return 3;
396
+	break;
397
+	case TRANSMITTER_UNIPHY_E:
398
+		return 4;
399
+	break;
400
+	case TRANSMITTER_UNIPHY_F:
401
+		return 5;
402
+	break;
403
+	case TRANSMITTER_UNIPHY_G:
404
+		return 6;
405
+	break;
406
+	default:
407
+		ASSERT(0);
408
+		return 0;
409
+	}
410
+}
342411 
343412 #define clk_src_regs(index, id)\
344413 [index] = {\
....@@ -376,7 +445,7 @@
376445 			     ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
377446 	return &opp->base;
378447 }
379
-struct aux_engine *dce120_aux_engine_create(
448
+struct dce_aux *dce120_aux_engine_create(
380449 	struct dc_context *ctx,
381450 	uint32_t inst)
382451 {
....@@ -388,12 +457,49 @@
388457 
389458 	dce110_aux_engine_construct(aux_engine, ctx, inst,
390459 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
391
-				    &aux_engine_regs[inst]);
460
+				    &aux_engine_regs[inst],
461
+					&aux_mask,
462
+					&aux_shift,
463
+					ctx->dc->caps.extended_aux_timeout_support);
392464 
393465 	return &aux_engine->base;
394466 }
467
+#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
395468 
469
+static const struct dce_i2c_registers i2c_hw_regs[] = {
470
+		i2c_inst_regs(1),
471
+		i2c_inst_regs(2),
472
+		i2c_inst_regs(3),
473
+		i2c_inst_regs(4),
474
+		i2c_inst_regs(5),
475
+		i2c_inst_regs(6),
476
+};
477
+
478
+static const struct dce_i2c_shift i2c_shifts = {
479
+		I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
480
+};
481
+
482
+static const struct dce_i2c_mask i2c_masks = {
483
+		I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
484
+};
485
+
486
+struct dce_i2c_hw *dce120_i2c_hw_create(
487
+	struct dc_context *ctx,
488
+	uint32_t inst)
489
+{
490
+	struct dce_i2c_hw *dce_i2c_hw =
491
+		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
492
+
493
+	if (!dce_i2c_hw)
494
+		return NULL;
495
+
496
+	dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst,
497
+				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
498
+
499
+	return dce_i2c_hw;
500
+}
396501 static const struct bios_registers bios_regs = {
502
+	.BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3 + NBIO_BASE(mmBIOS_SCRATCH_3_BASE_IDX),
397503 	.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX)
398504 };
399505 
....@@ -402,13 +508,36 @@
402508 		.num_audio = 7,
403509 		.num_stream_encoder = 6,
404510 		.num_pll = 6,
511
+		.num_ddc = 6,
512
+};
513
+
514
+static const struct dc_plane_cap plane_cap = {
515
+	.type = DC_PLANE_TYPE_DCE_RGB,
516
+
517
+	.pixel_format_support = {
518
+			.argb8888 = true,
519
+			.nv12 = false,
520
+			.fp16 = true
521
+	},
522
+
523
+	.max_upscale_factor = {
524
+			.argb8888 = 16000,
525
+			.nv12 = 1,
526
+			.fp16 = 1
527
+	},
528
+
529
+	.max_downscale_factor = {
530
+			.argb8888 = 250,
531
+			.nv12 = 1,
532
+			.fp16 = 1
533
+	}
405534 };
406535 
407536 static const struct dc_debug_options debug_defaults = {
408537 		.disable_clock_gate = true,
409538 };
410539 
411
-struct clock_source *dce120_clock_source_create(
540
+static struct clock_source *dce120_clock_source_create(
412541 	struct dc_context *ctx,
413542 	struct dc_bios *bios,
414543 	enum clock_source_id id,
....@@ -421,24 +550,25 @@
421550 	if (!clk_src)
422551 		return NULL;
423552 
424
-	if (dce110_clk_src_construct(clk_src, ctx, bios, id,
553
+	if (dce112_clk_src_construct(clk_src, ctx, bios, id,
425554 				     regs, &cs_shift, &cs_mask)) {
426555 		clk_src->base.dp_clk_src = dp_clk_src;
427556 		return &clk_src->base;
428557 	}
429558 
559
+	kfree(clk_src);
430560 	BREAK_TO_DEBUGGER();
431561 	return NULL;
432562 }
433563 
434
-void dce120_clock_source_destroy(struct clock_source **clk_src)
564
+static void dce120_clock_source_destroy(struct clock_source **clk_src)
435565 {
436566 	kfree(TO_DCE110_CLK_SRC(*clk_src));
437567 	*clk_src = NULL;
438568 }
439569 
440570 
441
-bool dce120_hw_sequencer_create(struct dc *dc)
571
+static bool dce120_hw_sequencer_create(struct dc *dc)
442572 {
443573 	/* All registers used by dce11.2 match those in dce11 in offset and
444574 	 * structure
....@@ -471,7 +601,7 @@
471601 	*xfm = NULL;
472602 }
473603 
474
-static void destruct(struct dce110_resource_pool *pool)
604
+static void dce120_resource_destruct(struct dce110_resource_pool *pool)
475605 {
476606 	unsigned int i;
477607 
....@@ -498,10 +628,19 @@
498628 			kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
499629 			pool->base.timing_generators[i] = NULL;
500630 		}
631
+	}
501632 
633
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
502634 		if (pool->base.engines[i] != NULL)
503635 			dce110_engine_destroy(&pool->base.engines[i]);
504
-
636
+		if (pool->base.hw_i2cs[i] != NULL) {
637
+			kfree(pool->base.hw_i2cs[i]);
638
+			pool->base.hw_i2cs[i] = NULL;
639
+		}
640
+		if (pool->base.sw_i2cs[i] != NULL) {
641
+			kfree(pool->base.sw_i2cs[i]);
642
+			pool->base.sw_i2cs[i] = NULL;
643
+		}
505644 	}
506645 
507646 	for (i = 0; i < pool->base.audio_count; i++) {
....@@ -528,9 +667,6 @@
528667 
529668 	if (pool->base.dmcu != NULL)
530669 		dce_dmcu_destroy(&pool->base.dmcu);
531
-
532
-	if (pool->base.dccg != NULL)
533
-		dce_dccg_destroy(&pool->base.dccg);
534670 }
535671 
536672 static void read_dce_straps(
....@@ -562,12 +698,12 @@
562698 static const struct encoder_feature_support link_enc_feature = {
563699 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
564700 		.max_hdmi_pixel_clock = 600000,
565
-		.ycbcr420_supported = true,
701
+		.hdmi_ycbcr420_supported = true,
702
+		.dp_ycbcr420_supported = false,
566703 		.flags.bits.IS_HBR2_CAPABLE = true,
567704 		.flags.bits.IS_HBR3_CAPABLE = true,
568705 		.flags.bits.IS_TPS3_CAPABLE = true,
569706 		.flags.bits.IS_TPS4_CAPABLE = true,
570
-		.flags.bits.IS_YCBCR_CAPABLE = true
571707 };
572708 
573709 static struct link_encoder *dce120_link_encoder_create(
....@@ -575,18 +711,39 @@
575711 {
576712 	struct dce110_link_encoder *enc110 =
577713 		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
714
+	int link_regs_id;
578715 
579716 	if (!enc110)
580717 		return NULL;
581718 
719
+	link_regs_id =
720
+		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
721
+
582722 	dce110_link_encoder_construct(enc110,
583723 				      enc_init_data,
584724 				      &link_enc_feature,
585
-				      &link_enc_regs[enc_init_data->transmitter],
725
+				      &link_enc_regs[link_regs_id],
586726 				      &link_enc_aux_regs[enc_init_data->channel - 1],
587727 				      &link_enc_hpd_regs[enc_init_data->hpd_source]);
588728 
589729 	return &enc110->base;
730
+}
731
+
732
+static struct panel_cntl *dce120_panel_cntl_create(const struct panel_cntl_init_data *init_data)
733
+{
734
+	struct dce_panel_cntl *panel_cntl =
735
+		kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
736
+
737
+	if (!panel_cntl)
738
+		return NULL;
739
+
740
+	dce_panel_cntl_construct(panel_cntl,
741
+			init_data,
742
+			&panel_cntl_regs[init_data->inst],
743
+			&panel_cntl_shift,
744
+			&panel_cntl_mask);
745
+
746
+	return &panel_cntl->base;
590747 }
591748 
592749 static struct input_pixel_processor *dce120_ipp_create(
....@@ -636,6 +793,19 @@
636793 		HWSEQ_DCE12_MASK_SH_LIST(_MASK)
637794 };
638795 
796
+/* HWSEQ regs for VG20 */
797
+static const struct dce_hwseq_registers dce121_hwseq_reg = {
798
+		HWSEQ_VG20_REG_LIST()
799
+};
800
+
801
+static const struct dce_hwseq_shift dce121_hwseq_shift = {
802
+		HWSEQ_VG20_MASK_SH_LIST(__SHIFT)
803
+};
804
+
805
+static const struct dce_hwseq_mask dce121_hwseq_mask = {
806
+		HWSEQ_VG20_MASK_SH_LIST(_MASK)
807
+};
808
+
639809 static struct dce_hwseq *dce120_hwseq_create(
640810 	struct dc_context *ctx)
641811 {
....@@ -650,12 +820,34 @@
650820 	return hws;
651821 }
652822 
823
+static struct dce_hwseq *dce121_hwseq_create(
824
+	struct dc_context *ctx)
825
+{
826
+	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
827
+
828
+	if (hws) {
829
+		hws->ctx = ctx;
830
+		hws->regs = &dce121_hwseq_reg;
831
+		hws->shifts = &dce121_hwseq_shift;
832
+		hws->masks = &dce121_hwseq_mask;
833
+	}
834
+	return hws;
835
+}
836
+
653837 static const struct resource_create_funcs res_create_funcs = {
654838 	.read_dce_straps = read_dce_straps,
655839 	.create_audio = create_audio,
656840 	.create_stream_encoder = dce120_stream_encoder_create,
657841 	.create_hwseq = dce120_hwseq_create,
658842 };
843
+
844
+static const struct resource_create_funcs dce121_res_create_funcs = {
845
+	.read_dce_straps = read_dce_straps,
846
+	.create_audio = create_audio,
847
+	.create_stream_encoder = dce120_stream_encoder_create,
848
+	.create_hwseq = dce121_hwseq_create,
849
+};
850
+
659851 
660852 #define mi_inst_regs(id) { MI_DCE12_REG_LIST(id) }
661853 static const struct dce_mem_input_registers mi_regs[] = {
....@@ -711,7 +903,7 @@
711903 {
712904 	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
713905 
714
-	destruct(dce110_pool);
906
+	dce120_resource_destruct(dce110_pool);
715907 	kfree(dce110_pool);
716908 	*pool = NULL;
717909 }
....@@ -719,9 +911,11 @@
719911 static const struct resource_funcs dce120_res_pool_funcs = {
720912 	.destroy = dce120_destroy_resource_pool,
721913 	.link_enc_create = dce120_link_encoder_create,
914
+	.panel_cntl_create = dce120_panel_cntl_create,
722915 	.validate_bandwidth = dce112_validate_bandwidth,
723916 	.validate_plane = dce100_validate_plane,
724
-	.add_stream_to_ctx = dce112_add_stream_to_ctx
917
+	.add_stream_to_ctx = dce112_add_stream_to_ctx,
918
+	.find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link
725919 };
726920 
727921 static void bw_calcs_data_update_from_pplib(struct dc *dc)
....@@ -732,6 +926,8 @@
732926 	int i;
733927 	unsigned int clk;
734928 	unsigned int latency;
929
+	/*original logic in dal3*/
930
+	int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ;
735931 
736932 	/*do system clock*/
737933 	if (!dm_pp_get_clock_levels_by_type_with_latency(
....@@ -790,13 +986,16 @@
790986 	 * ALSO always convert UMA clock (from PPLIB)  to YCLK (HW formula):
791987 	 * YCLK = UMACLK*m_memoryTypeMultiplier
792988 	 */
989
+	if (dc->bw_vbios->memory_type == bw_def_hbm)
990
+		memory_type_multiplier = MEMORY_TYPE_HBM;
991
+
793992 	dc->bw_vbios->low_yclk = bw_frc_to_fixed(
794
-		mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000);
993
+		mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000);
795994 	dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
796
-		mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
995
+		mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier,
797996 		1000);
798997 	dc->bw_vbios->high_yclk = bw_frc_to_fixed(
799
-		mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
998
+		mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier,
800999 		1000);
8011000 
8021001 	/* Now notify PPLib/SMU about which Watermarks sets they should select
....@@ -857,7 +1056,7 @@
8571056 	return value;
8581057 }
8591058 
860
-static bool construct(
1059
+static bool dce120_resource_construct(
8611060 	uint8_t num_virtual_links,
8621061 	struct dc *dc,
8631062 	struct dce110_resource_pool *pool)
....@@ -866,7 +1065,8 @@
8661065 	int j;
8671066 	struct dc_context *ctx = dc->ctx;
8681067 	struct irq_service_init_data irq_init_data;
869
-	bool harvest_enabled = ASICREV_IS_VEGA20_P(ctx->asic_id.hw_internal_rev);
1068
+	static const struct resource_create_funcs *res_funcs;
1069
+	bool is_vg20 = ASICREV_IS_VEGA20_P(ctx->asic_id.hw_internal_rev);
8701070 	uint32_t pipe_fuses;
8711071 
8721072 	ctx->dc_bios->regs = &bios_regs;
....@@ -884,7 +1084,7 @@
8841084 	dc->caps.max_cursor_size = 128;
8851085 	dc->caps.dual_link_dvi = true;
8861086 	dc->caps.psp_setup_panel_mode = true;
887
-
1087
+	dc->caps.extended_aux_timeout_support = false;
8881088 	dc->debug = debug_defaults;
8891089 
8901090 	/*************************************************
....@@ -930,13 +1130,6 @@
9301130 		}
9311131 	}
9321132 
933
-	pool->base.dccg = dce120_dccg_create(ctx);
934
-	if (pool->base.dccg == NULL) {
935
-		dm_error("DC: failed to create display clock!\n");
936
-		BREAK_TO_DEBUGGER();
937
-		goto dccg_create_fail;
938
-	}
939
-
9401133 	pool->base.dmcu = dce_dmcu_create(ctx,
9411134 			&dmcu_regs,
9421135 			&dmcu_shift,
....@@ -957,19 +1150,20 @@
9571150 		goto res_create_fail;
9581151 	}
9591152 
1153
+
9601154 	irq_init_data.ctx = dc->ctx;
9611155 	pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data);
9621156 	if (!pool->base.irqs)
9631157 		goto irqs_create_fail;
9641158 
965
-	/* retrieve valid pipe fuses */
966
-	if (harvest_enabled)
1159
+	/* VG20: Pipe harvesting enabled, retrieve valid pipe fuses */
1160
+	if (is_vg20)
9671161 		pipe_fuses = read_pipe_fuses(ctx);
9681162 
9691163 	/* index to valid pipe resource */
9701164 	j = 0;
9711165 	for (i = 0; i < pool->base.pipe_count; i++) {
972
-		if (harvest_enabled) {
1166
+		if (is_vg20) {
9731167 			if ((pipe_fuses & (1 << i)) != 0) {
9741168 				dm_error("DC: skip invalid pipe %d!\n", i);
9751169 				continue;
....@@ -1020,24 +1214,39 @@
10201214 			dm_error(
10211215 				"DC: failed to create output pixel processor!\n");
10221216 		}
1023
-		pool->base.engines[i] = dce120_aux_engine_create(ctx, i);
1024
-				if (pool->base.engines[i] == NULL) {
1025
-					BREAK_TO_DEBUGGER();
1026
-					dm_error(
1027
-						"DC:failed to create aux engine!!\n");
1028
-					goto res_create_fail;
1029
-				}
10301217 
10311218 		/* check next valid pipe */
10321219 		j++;
1220
+	}
1221
+
1222
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1223
+		pool->base.engines[i] = dce120_aux_engine_create(ctx, i);
1224
+		if (pool->base.engines[i] == NULL) {
1225
+			BREAK_TO_DEBUGGER();
1226
+			dm_error(
1227
+				"DC:failed to create aux engine!!\n");
1228
+			goto res_create_fail;
1229
+		}
1230
+		pool->base.hw_i2cs[i] = dce120_i2c_hw_create(ctx, i);
1231
+		if (pool->base.hw_i2cs[i] == NULL) {
1232
+			BREAK_TO_DEBUGGER();
1233
+			dm_error(
1234
+				"DC:failed to create i2c engine!!\n");
1235
+			goto res_create_fail;
1236
+		}
1237
+		pool->base.sw_i2cs[i] = NULL;
10331238 	}
10341239 
10351240 	/* valid pipe num */
10361241 	pool->base.pipe_count = j;
10371242 	pool->base.timing_generator_count = j;
10381243 
1039
-	if (!resource_construct(num_virtual_links, dc, &pool->base,
1040
-			 &res_create_funcs))
1244
+	if (is_vg20)
1245
+		res_funcs = &dce121_res_create_funcs;
1246
+	else
1247
+		res_funcs = &res_create_funcs;
1248
+
1249
+	if (!resource_construct(num_virtual_links, dc, &pool->base, res_funcs))
10411250 		goto res_create_fail;
10421251 
10431252 	/* Create hardware sequencer */
....@@ -1045,6 +1254,9 @@
10451254 		goto controller_create_fail;
10461255 
10471256 	dc->caps.max_planes =  pool->base.pipe_count;
1257
+
1258
+	for (i = 0; i < dc->caps.max_planes; ++i)
1259
+		dc->caps.planes[i] = plane_cap;
10481260 
10491261 	bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
10501262 
....@@ -1054,11 +1266,10 @@
10541266 
10551267 irqs_create_fail:
10561268 controller_create_fail:
1057
-dccg_create_fail:
10581269 clk_src_create_fail:
10591270 res_create_fail:
10601271 
1061
-	destruct(pool);
1272
+	dce120_resource_destruct(pool);
10621273 
10631274 	return false;
10641275 }
....@@ -1073,7 +1284,7 @@
10731284 	if (!pool)
10741285 		return NULL;
10751286 
1076
-	if (construct(num_virtual_links, dc, pool))
1287
+	if (dce120_resource_construct(num_virtual_links, dc, pool))
10771288 		return &pool->base;
10781289 
10791290 	kfree(pool);