forked from ~ljy/RK356X_SDK_RELEASE

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2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da 
 kernel/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
....@@ -23,6 +23,8 @@
2323  *
2424  */
2525 
26
+#include <linux/slab.h>
27
+
2628 #include "dm_services.h"
2729 
2830 #include "link_encoder.h"
....@@ -30,7 +32,6 @@
3032 
3133 #include "resource.h"
3234 #include "dce110/dce110_resource.h"
33
-
3435 #include "include/irq_service_interface.h"
3536 #include "dce/dce_audio.h"
3637 #include "dce110/dce110_timing_generator.h"
....@@ -45,13 +46,14 @@
4546 #include "dce110/dce110_transform_v.h"
4647 #include "dce/dce_opp.h"
4748 #include "dce110/dce110_opp_v.h"
48
-#include "dce/dce_clocks.h"
4949 #include "dce/dce_clock_source.h"
5050 #include "dce/dce_hwseq.h"
5151 #include "dce110/dce110_hw_sequencer.h"
5252 #include "dce/dce_aux.h"
5353 #include "dce/dce_abm.h"
5454 #include "dce/dce_dmcu.h"
55
+#include "dce/dce_i2c.h"
56
+#include "dce/dce_panel_cntl.h"
5557 
5658 #define DC_LOGGER \
5759 		dc->ctx->logger
....@@ -83,6 +85,7 @@
8385 
8486 #ifndef mmBIOS_SCRATCH_2
8587 	#define mmBIOS_SCRATCH_2 0x05CB
88
+	#define mmBIOS_SCRATCH_3 0x05CC
8689 	#define mmBIOS_SCRATCH_6 0x05CF
8790 #endif
8891 
....@@ -146,18 +149,6 @@
146149 /* set register offset with instance */
147150 #define SRI(reg_name, block, id)\
148151 	.reg_name = mm ## block ## id ## _ ## reg_name
149
-
150
-static const struct dccg_registers disp_clk_regs = {
151
-		CLK_COMMON_REG_LIST_DCE_BASE()
152
-};
153
-
154
-static const struct dccg_shift disp_clk_shift = {
155
-		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
156
-};
157
-
158
-static const struct dccg_mask disp_clk_mask = {
159
-		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
160
-};
161152 
162153 static const struct dce_dmcu_registers dmcu_regs = {
163154 		DMCU_DCE110_COMMON_REG_LIST()
....@@ -285,6 +276,26 @@
285276 		SE_COMMON_MASK_SH_LIST_DCE110(_MASK)
286277 };
287278 
279
+static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
280
+	{ DCE_PANEL_CNTL_REG_LIST() }
281
+};
282
+
283
+static const struct dce_panel_cntl_shift panel_cntl_shift = {
284
+	DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
285
+};
286
+
287
+static const struct dce_panel_cntl_mask panel_cntl_mask = {
288
+	DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
289
+};
290
+
291
+static const struct dce110_aux_registers_shift aux_shift = {
292
+	DCE_AUX_MASK_SH_LIST(__SHIFT)
293
+};
294
+
295
+static const struct dce110_aux_registers_mask aux_mask = {
296
+	DCE_AUX_MASK_SH_LIST(_MASK)
297
+};
298
+
288299 #define opp_regs(id)\
289300 [id] = {\
290301 	OPP_DCE_110_REG_LIST(id),\
....@@ -341,7 +352,7 @@
341352 		AUD_COMMON_MASK_SH_LIST(__SHIFT)
342353 };
343354 
344
-static const struct dce_aduio_mask audio_mask = {
355
+static const struct dce_audio_mask audio_mask = {
345356 		AUD_COMMON_MASK_SH_LIST(_MASK)
346357 };
347358 
....@@ -368,6 +379,7 @@
368379 };
369380 
370381 static const struct bios_registers bios_regs = {
382
+	.BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
371383 	.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
372384 };
373385 
....@@ -377,6 +389,7 @@
377389 		.num_audio = 3,
378390 		.num_stream_encoder = 3,
379391 		.num_pll = 2,
392
+		.num_ddc = 3,
380393 };
381394 
382395 static const struct resource_caps stoney_resource_cap = {
....@@ -385,6 +398,60 @@
385398 		.num_audio = 3,
386399 		.num_stream_encoder = 3,
387400 		.num_pll = 2,
401
+		.num_ddc = 3,
402
+};
403
+
404
+static const struct dc_plane_cap plane_cap = {
405
+		.type = DC_PLANE_TYPE_DCE_RGB,
406
+		.blends_with_below = true,
407
+		.blends_with_above = true,
408
+		.per_pixel_alpha = 1,
409
+
410
+		.pixel_format_support = {
411
+				.argb8888 = true,
412
+				.nv12 = false,
413
+				.fp16 = false
414
+		},
415
+
416
+		.max_upscale_factor = {
417
+				.argb8888 = 16000,
418
+				.nv12 = 1,
419
+				.fp16 = 1
420
+		},
421
+
422
+		.max_downscale_factor = {
423
+				.argb8888 = 250,
424
+				.nv12 = 1,
425
+				.fp16 = 1
426
+		},
427
+		64,
428
+		64
429
+};
430
+
431
+static const struct dc_plane_cap underlay_plane_cap = {
432
+		.type = DC_PLANE_TYPE_DCE_UNDERLAY,
433
+		.blends_with_above = true,
434
+		.per_pixel_alpha = 1,
435
+
436
+		.pixel_format_support = {
437
+				.argb8888 = false,
438
+				.nv12 = true,
439
+				.fp16 = false
440
+		},
441
+
442
+		.max_upscale_factor = {
443
+				.argb8888 = 1,
444
+				.nv12 = 16000,
445
+				.fp16 = 1
446
+		},
447
+
448
+		.max_downscale_factor = {
449
+				.argb8888 = 1,
450
+				.nv12 = 250,
451
+				.fp16 = 1
452
+		},
453
+		64,
454
+		64
388455 };
389456 
390457 #define CTX  ctx
....@@ -397,6 +464,37 @@
397464 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
398465 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
399466 #endif
467
+
468
+static int map_transmitter_id_to_phy_instance(
469
+	enum transmitter transmitter)
470
+{
471
+	switch (transmitter) {
472
+	case TRANSMITTER_UNIPHY_A:
473
+		return 0;
474
+	break;
475
+	case TRANSMITTER_UNIPHY_B:
476
+		return 1;
477
+	break;
478
+	case TRANSMITTER_UNIPHY_C:
479
+		return 2;
480
+	break;
481
+	case TRANSMITTER_UNIPHY_D:
482
+		return 3;
483
+	break;
484
+	case TRANSMITTER_UNIPHY_E:
485
+		return 4;
486
+	break;
487
+	case TRANSMITTER_UNIPHY_F:
488
+		return 5;
489
+	break;
490
+	case TRANSMITTER_UNIPHY_G:
491
+		return 6;
492
+	break;
493
+	default:
494
+		ASSERT(0);
495
+		return 0;
496
+	}
497
+}
400498 
401499 static void read_dce_straps(
402500 	struct dc_context *ctx,
....@@ -565,10 +663,9 @@
565663 
566664 static const struct encoder_feature_support link_enc_feature = {
567665 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
568
-		.max_hdmi_pixel_clock = 594000,
666
+		.max_hdmi_pixel_clock = 300000,
569667 		.flags.bits.IS_HBR2_CAPABLE = true,
570
-		.flags.bits.IS_TPS3_CAPABLE = true,
571
-		.flags.bits.IS_YCBCR_CAPABLE = true
668
+		.flags.bits.IS_TPS3_CAPABLE = true
572669 };
573670 
574671 static struct link_encoder *dce110_link_encoder_create(
....@@ -576,17 +673,38 @@
576673 {
577674 	struct dce110_link_encoder *enc110 =
578675 		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
676
+	int link_regs_id;
579677 
580678 	if (!enc110)
581679 		return NULL;
582680 
681
+	link_regs_id =
682
+		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
683
+
583684 	dce110_link_encoder_construct(enc110,
584685 				      enc_init_data,
585686 				      &link_enc_feature,
586
-				      &link_enc_regs[enc_init_data->transmitter],
687
+				      &link_enc_regs[link_regs_id],
587688 				      &link_enc_aux_regs[enc_init_data->channel - 1],
588689 				      &link_enc_hpd_regs[enc_init_data->hpd_source]);
589690 	return &enc110->base;
691
+}
692
+
693
+static struct panel_cntl *dce110_panel_cntl_create(const struct panel_cntl_init_data *init_data)
694
+{
695
+	struct dce_panel_cntl *panel_cntl =
696
+		kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
697
+
698
+	if (!panel_cntl)
699
+		return NULL;
700
+
701
+	dce_panel_cntl_construct(panel_cntl,
702
+			init_data,
703
+			&panel_cntl_regs[init_data->inst],
704
+			&panel_cntl_shift,
705
+			&panel_cntl_mask);
706
+
707
+	return &panel_cntl->base;
590708 }
591709 
592710 static struct output_pixel_processor *dce110_opp_create(
....@@ -604,7 +722,7 @@
604722 	return &opp->base;
605723 }
606724 
607
-struct aux_engine *dce110_aux_engine_create(
725
+struct dce_aux *dce110_aux_engine_create(
608726 	struct dc_context *ctx,
609727 	uint32_t inst)
610728 {
....@@ -616,11 +734,47 @@
616734 
617735 	dce110_aux_engine_construct(aux_engine, ctx, inst,
618736 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
619
-				    &aux_engine_regs[inst]);
737
+				    &aux_engine_regs[inst],
738
+					&aux_mask,
739
+					&aux_shift,
740
+					ctx->dc->caps.extended_aux_timeout_support);
620741 
621742 	return &aux_engine->base;
622743 }
744
+#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
623745 
746
+static const struct dce_i2c_registers i2c_hw_regs[] = {
747
+		i2c_inst_regs(1),
748
+		i2c_inst_regs(2),
749
+		i2c_inst_regs(3),
750
+		i2c_inst_regs(4),
751
+		i2c_inst_regs(5),
752
+		i2c_inst_regs(6),
753
+};
754
+
755
+static const struct dce_i2c_shift i2c_shifts = {
756
+		I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
757
+};
758
+
759
+static const struct dce_i2c_mask i2c_masks = {
760
+		I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
761
+};
762
+
763
+struct dce_i2c_hw *dce110_i2c_hw_create(
764
+	struct dc_context *ctx,
765
+	uint32_t inst)
766
+{
767
+	struct dce_i2c_hw *dce_i2c_hw =
768
+		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
769
+
770
+	if (!dce_i2c_hw)
771
+		return NULL;
772
+
773
+	dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst,
774
+				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
775
+
776
+	return dce_i2c_hw;
777
+}
624778 struct clock_source *dce110_clock_source_create(
625779 	struct dc_context *ctx,
626780 	struct dc_bios *bios,
....@@ -640,6 +794,7 @@
640794 		return &clk_src->base;
641795 	}
642796 
797
+	kfree(clk_src);
643798 	BREAK_TO_DEBUGGER();
644799 	return NULL;
645800 }
....@@ -661,7 +816,7 @@
661816 	*clk_src = NULL;
662817 }
663818 
664
-static void destruct(struct dce110_resource_pool *pool)
819
+static void dce110_resource_destruct(struct dce110_resource_pool *pool)
665820 {
666821 	unsigned int i;
667822 
....@@ -684,10 +839,19 @@
684839 			kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
685840 			pool->base.timing_generators[i] = NULL;
686841 		}
842
+	}
687843 
844
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
688845 		if (pool->base.engines[i] != NULL)
689846 			dce110_engine_destroy(&pool->base.engines[i]);
690
-
847
+		if (pool->base.hw_i2cs[i] != NULL) {
848
+			kfree(pool->base.hw_i2cs[i]);
849
+			pool->base.hw_i2cs[i] = NULL;
850
+		}
851
+		if (pool->base.sw_i2cs[i] != NULL) {
852
+			kfree(pool->base.sw_i2cs[i]);
853
+			pool->base.sw_i2cs[i] = NULL;
854
+		}
691855 	}
692856 
693857 	for (i = 0; i < pool->base.stream_enc_count; i++) {
....@@ -716,9 +880,6 @@
716880 	if (pool->base.dmcu != NULL)
717881 		dce_dmcu_destroy(&pool->base.dmcu);
718882 
719
-	if (pool->base.dccg != NULL)
720
-		dce_dccg_destroy(&pool->base.dccg);
721
-
722883 	if (pool->base.irqs != NULL) {
723884 		dal_irq_service_destroy(&pool->base.irqs);
724885 	}
....@@ -735,8 +896,8 @@
735896 	 * the pixel clock normalization for hdmi up to here instead of doing it
736897 	 * in pll_adjust_pix_clk
737898 	 */
738
-	pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz;
739
-	pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id;
899
+	pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
900
+	pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
740901 	pixel_clk_params->signal_type = pipe_ctx->stream->signal;
741902 	pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
742903 	/* TODO: un-hardcode*/
....@@ -753,8 +914,11 @@
753914 		pixel_clk_params->color_depth = COLOR_DEPTH_888;
754915 	}
755916 	if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
756
-		pixel_clk_params->requested_pix_clk  = pixel_clk_params->requested_pix_clk / 2;
917
+		pixel_clk_params->requested_pix_clk_100hz  = pixel_clk_params->requested_pix_clk_100hz / 2;
757918 	}
919
+	if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
920
+		pixel_clk_params->requested_pix_clk_100hz *= 2;
921
+
758922 }
759923 
760924 void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
....@@ -805,7 +969,8 @@
805969 
806970 static bool dce110_validate_bandwidth(
807971 	struct dc *dc,
808
-	struct dc_state *context)
972
+	struct dc_state *context,
973
+	bool fast_validate)
809974 {
810975 	bool result = false;
811976 
....@@ -819,7 +984,7 @@
819984 			dc->bw_vbios,
820985 			context->res_ctx.pipe_ctx,
821986 			dc->res_pool->pipe_count,
822
-			&context->bw.dce))
987
+			&context->bw_ctx.bw.dce))
823988 		result =  true;
824989 
825990 	if (!result)
....@@ -827,10 +992,10 @@
827992 			__func__,
828993 			context->streams[0]->timing.h_addressable,
829994 			context->streams[0]->timing.v_addressable,
830
-			context->streams[0]->timing.pix_clk_khz);
995
+			context->streams[0]->timing.pix_clk_100hz / 10);
831996 
832
-	if (memcmp(&dc->current_state->bw.dce,
833
-			&context->bw.dce, sizeof(context->bw.dce))) {
997
+	if (memcmp(&dc->current_state->bw_ctx.bw.dce,
998
+			&context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) {
834999 
8351000 		DC_LOG_BANDWIDTH_CALCS(
8361001 			"%s: finish,\n"
....@@ -844,34 +1009,34 @@
8441009 			"sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n"
8451010 			,
8461011 			__func__,
847
-			context->bw.dce.nbp_state_change_wm_ns[0].b_mark,
848
-			context->bw.dce.nbp_state_change_wm_ns[0].a_mark,
849
-			context->bw.dce.urgent_wm_ns[0].b_mark,
850
-			context->bw.dce.urgent_wm_ns[0].a_mark,
851
-			context->bw.dce.stutter_exit_wm_ns[0].b_mark,
852
-			context->bw.dce.stutter_exit_wm_ns[0].a_mark,
853
-			context->bw.dce.nbp_state_change_wm_ns[1].b_mark,
854
-			context->bw.dce.nbp_state_change_wm_ns[1].a_mark,
855
-			context->bw.dce.urgent_wm_ns[1].b_mark,
856
-			context->bw.dce.urgent_wm_ns[1].a_mark,
857
-			context->bw.dce.stutter_exit_wm_ns[1].b_mark,
858
-			context->bw.dce.stutter_exit_wm_ns[1].a_mark,
859
-			context->bw.dce.nbp_state_change_wm_ns[2].b_mark,
860
-			context->bw.dce.nbp_state_change_wm_ns[2].a_mark,
861
-			context->bw.dce.urgent_wm_ns[2].b_mark,
862
-			context->bw.dce.urgent_wm_ns[2].a_mark,
863
-			context->bw.dce.stutter_exit_wm_ns[2].b_mark,
864
-			context->bw.dce.stutter_exit_wm_ns[2].a_mark,
865
-			context->bw.dce.stutter_mode_enable,
866
-			context->bw.dce.cpuc_state_change_enable,
867
-			context->bw.dce.cpup_state_change_enable,
868
-			context->bw.dce.nbp_state_change_enable,
869
-			context->bw.dce.all_displays_in_sync,
870
-			context->bw.dce.dispclk_khz,
871
-			context->bw.dce.sclk_khz,
872
-			context->bw.dce.sclk_deep_sleep_khz,
873
-			context->bw.dce.yclk_khz,
874
-			context->bw.dce.blackout_recovery_time_us);
1012
+			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark,
1013
+			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark,
1014
+			context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark,
1015
+			context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark,
1016
+			context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark,
1017
+			context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark,
1018
+			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark,
1019
+			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].a_mark,
1020
+			context->bw_ctx.bw.dce.urgent_wm_ns[1].b_mark,
1021
+			context->bw_ctx.bw.dce.urgent_wm_ns[1].a_mark,
1022
+			context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].b_mark,
1023
+			context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].a_mark,
1024
+			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].b_mark,
1025
+			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].a_mark,
1026
+			context->bw_ctx.bw.dce.urgent_wm_ns[2].b_mark,
1027
+			context->bw_ctx.bw.dce.urgent_wm_ns[2].a_mark,
1028
+			context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].b_mark,
1029
+			context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].a_mark,
1030
+			context->bw_ctx.bw.dce.stutter_mode_enable,
1031
+			context->bw_ctx.bw.dce.cpuc_state_change_enable,
1032
+			context->bw_ctx.bw.dce.cpup_state_change_enable,
1033
+			context->bw_ctx.bw.dce.nbp_state_change_enable,
1034
+			context->bw_ctx.bw.dce.all_displays_in_sync,
1035
+			context->bw_ctx.bw.dce.dispclk_khz,
1036
+			context->bw_ctx.bw.dce.sclk_khz,
1037
+			context->bw_ctx.bw.dce.sclk_deep_sleep_khz,
1038
+			context->bw_ctx.bw.dce.yclk_khz,
1039
+			context->bw_ctx.bw.dce.blackout_recovery_time_us);
8751040 	}
8761041 	return result;
8771042 }
....@@ -966,6 +1131,7 @@
9661131 		struct dc_stream_state *stream)
9671132 {
9681133 	struct dc *dc = stream->ctx->dc;
1134
+	struct dce_hwseq *hws = dc->hwseq;
9691135 	struct resource_context *res_ctx = &context->res_ctx;
9701136 	unsigned int underlay_idx = pool->underlay_pipe_index;
9711137 	struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx];
....@@ -986,7 +1152,7 @@
9861152 		struct tg_color black_color = {0};
9871153 		struct dc_bios *dcb = dc->ctx->dc_bios;
9881154 
989
-		dc->hwss.enable_display_power_gating(
1155
+		hws->funcs.enable_display_power_gating(
9901156 				dc,
9911157 				pipe_ctx->stream_res.tg->inst,
9921158 				dcb, PIPE_GATING_CONTROL_DISABLE);
....@@ -998,6 +1164,11 @@
9981164 
9991165 		pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg,
10001166 				&stream->timing,
1167
+				0,
1168
+				0,
1169
+				0,
1170
+				0,
1171
+				pipe_ctx->stream->signal,
10011172 				false);
10021173 
10031174 		pipe_ctx->stream_res.tg->funcs->enable_advanced_request(
....@@ -1008,7 +1179,7 @@
10081179 		pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi,
10091180 				stream->timing.h_total,
10101181 				stream->timing.v_total,
1011
-				stream->timing.pix_clk_khz,
1182
+				stream->timing.pix_clk_100hz / 10,
10121183 				context->stream_count);
10131184 
10141185 		color_space_to_black_color(dc,
....@@ -1025,20 +1196,54 @@
10251196 {
10261197 	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
10271198 
1028
-	destruct(dce110_pool);
1199
+	dce110_resource_destruct(dce110_pool);
10291200 	kfree(dce110_pool);
10301201 	*pool = NULL;
1202
+}
1203
+
1204
+struct stream_encoder *dce110_find_first_free_match_stream_enc_for_link(
1205
+		struct resource_context *res_ctx,
1206
+		const struct resource_pool *pool,
1207
+		struct dc_stream_state *stream)
1208
+{
1209
+	int i;
1210
+	int j = -1;
1211
+	struct dc_link *link = stream->link;
1212
+
1213
+	for (i = 0; i < pool->stream_enc_count; i++) {
1214
+		if (!res_ctx->is_stream_enc_acquired[i] &&
1215
+				pool->stream_enc[i]) {
1216
+			/* Store first available for MST second display
1217
+			 * in daisy chain use case
1218
+			 */
1219
+			j = i;
1220
+			if (pool->stream_enc[i]->id ==
1221
+					link->link_enc->preferred_engine)
1222
+				return pool->stream_enc[i];
1223
+		}
1224
+	}
1225
+
1226
+	/*
1227
+	 * For CZ and later, we can allow DIG FE and BE to differ for all display types
1228
+	 */
1229
+
1230
+	if (j >= 0)
1231
+		return pool->stream_enc[j];
1232
+
1233
+	return NULL;
10311234 }
10321235 
10331236 
10341237 static const struct resource_funcs dce110_res_pool_funcs = {
10351238 	.destroy = dce110_destroy_resource_pool,
10361239 	.link_enc_create = dce110_link_encoder_create,
1240
+	.panel_cntl_create = dce110_panel_cntl_create,
10371241 	.validate_bandwidth = dce110_validate_bandwidth,
10381242 	.validate_plane = dce110_validate_plane,
10391243 	.acquire_idle_pipe_for_layer = dce110_acquire_underlay,
10401244 	.add_stream_to_ctx = dce110_add_stream_to_ctx,
1041
-	.validate_global = dce110_validate_global
1245
+	.validate_global = dce110_validate_global,
1246
+	.find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link
10421247 };
10431248 
10441249 static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool)
....@@ -1126,12 +1331,12 @@
11261331 			&clks);
11271332 
11281333 	dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1129
-		clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000);
1334
+		clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER_CZ, 1000);
11301335 	dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1131
-		clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER,
1336
+		clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER_CZ,
11321337 		1000);
11331338 	dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1134
-		clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER,
1339
+		clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER_CZ,
11351340 		1000);
11361341 }
11371342 
....@@ -1144,7 +1349,7 @@
11441349 		return &carrizo_resource_cap;
11451350 }
11461351 
1147
-static bool construct(
1352
+static bool dce110_resource_construct(
11481353 	uint8_t num_virtual_links,
11491354 	struct dc *dc,
11501355 	struct dce110_resource_pool *pool,
....@@ -1152,9 +1357,7 @@
11521357 {
11531358 	unsigned int i;
11541359 	struct dc_context *ctx = dc->ctx;
1155
-	struct dc_firmware_info info;
11561360 	struct dc_bios *bp;
1157
-	struct dm_pp_static_clock_info static_clk_info = {0};
11581361 
11591362 	ctx->dc_bios->regs = &bios_regs;
11601363 
....@@ -1172,6 +1375,7 @@
11721375 	dc->caps.i2c_speed_in_khz = 100;
11731376 	dc->caps.max_cursor_size = 128;
11741377 	dc->caps.is_apu = true;
1378
+	dc->caps.extended_aux_timeout_support = false;
11751379 
11761380 	/*************************************************
11771381 	 *  Create resources                             *
....@@ -1179,8 +1383,7 @@
11791383 
11801384 	bp = ctx->dc_bios;
11811385 
1182
-	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
1183
-		info.external_clock_source_frequency_for_dp != 0) {
1386
+	if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
11841387 		pool->base.dp_clock_source =
11851388 				dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
11861389 
....@@ -1210,16 +1413,6 @@
12101413 		}
12111414 	}
12121415 
1213
-	pool->base.dccg = dce110_dccg_create(ctx,
1214
-			&disp_clk_regs,
1215
-			&disp_clk_shift,
1216
-			&disp_clk_mask);
1217
-	if (pool->base.dccg == NULL) {
1218
-		dm_error("DC: failed to create display clock!\n");
1219
-		BREAK_TO_DEBUGGER();
1220
-		goto res_create_fail;
1221
-	}
1222
-
12231416 	pool->base.dmcu = dce_dmcu_create(ctx,
12241417 			&dmcu_regs,
12251418 			&dmcu_shift,
....@@ -1239,13 +1432,6 @@
12391432 		BREAK_TO_DEBUGGER();
12401433 		goto res_create_fail;
12411434 	}
1242
-
1243
-	/* get static clock information for PPLIB or firmware, save
1244
-	 * max_clock_state
1245
-	 */
1246
-	if (dm_pp_get_static_clocks(ctx, &static_clk_info))
1247
-		pool->base.dccg->max_clks_state =
1248
-				static_clk_info.max_clocks_state;
12491435 
12501436 	{
12511437 		struct irq_service_init_data init_data;
....@@ -1295,7 +1481,9 @@
12951481 				"DC: failed to create output pixel processor!\n");
12961482 			goto res_create_fail;
12971483 		}
1484
+	}
12981485 
1486
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
12991487 		pool->base.engines[i] = dce110_aux_engine_create(ctx, i);
13001488 		if (pool->base.engines[i] == NULL) {
13011489 			BREAK_TO_DEBUGGER();
....@@ -1303,9 +1491,18 @@
13031491 				"DC:failed to create aux engine!!\n");
13041492 			goto res_create_fail;
13051493 		}
1494
+		pool->base.hw_i2cs[i] = dce110_i2c_hw_create(ctx, i);
1495
+		if (pool->base.hw_i2cs[i] == NULL) {
1496
+			BREAK_TO_DEBUGGER();
1497
+			dm_error(
1498
+				"DC:failed to create i2c engine!!\n");
1499
+			goto res_create_fail;
1500
+		}
1501
+		pool->base.sw_i2cs[i] = NULL;
13061502 	}
13071503 
1308
-	dc->fbc_compressor = dce110_compressor_create(ctx);
1504
+	if (dc->config.fbc_support)
1505
+		dc->fbc_compressor = dce110_compressor_create(ctx);
13091506 
13101507 	if (!underlay_create(ctx, &pool->base))
13111508 		goto res_create_fail;
....@@ -1319,6 +1516,11 @@
13191516 
13201517 	dc->caps.max_planes =  pool->base.pipe_count;
13211518 
1519
+	for (i = 0; i < pool->base.underlay_pipe_index; ++i)
1520
+		dc->caps.planes[i] = plane_cap;
1521
+
1522
+	dc->caps.planes[pool->base.underlay_pipe_index] = underlay_plane_cap;
1523
+
13221524 	bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
13231525 
13241526 	bw_calcs_data_update_from_pplib(dc);
....@@ -1326,7 +1528,7 @@
13261528 	return true;
13271529 
13281530 res_create_fail:
1329
-	destruct(pool);
1531
+	dce110_resource_destruct(pool);
13301532 	return false;
13311533 }
13321534 
....@@ -1341,7 +1543,7 @@
13411543 	if (!pool)
13421544 		return NULL;
13431545 
1344
-	if (construct(num_virtual_links, dc, pool, asic_id))
1546
+	if (dce110_resource_construct(num_virtual_links, dc, pool, asic_id))
13451547 		return &pool->base;
13461548 
13471549 	kfree(pool);