add wifi6 8852be driver

hc

2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da

 kernel/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h
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@@ -108,6 +108,68 @@
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 	SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \
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 	SRI(DCFE_MEM_PWR_STATUS, DCFE, id)
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+#if defined(CONFIG_DRM_AMD_DC_SI)
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+#define XFM_COMMON_REG_LIST_DCE60_BASE(id) \
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+	SRI(DATA_FORMAT, LB, id), \
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+	SRI(GAMUT_REMAP_CONTROL, DCP, id), \
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+	SRI(GAMUT_REMAP_C11_C12, DCP, id), \
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+	SRI(GAMUT_REMAP_C13_C14, DCP, id), \
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+	SRI(GAMUT_REMAP_C21_C22, DCP, id), \
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+	SRI(GAMUT_REMAP_C23_C24, DCP, id), \
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+	SRI(GAMUT_REMAP_C31_C32, DCP, id), \
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+	SRI(GAMUT_REMAP_C33_C34, DCP, id), \
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+	SRI(OUTPUT_CSC_C11_C12, DCP, id), \
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+	SRI(OUTPUT_CSC_C13_C14, DCP, id), \
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+	SRI(OUTPUT_CSC_C21_C22, DCP, id), \
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+	SRI(OUTPUT_CSC_C23_C24, DCP, id), \
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+	SRI(OUTPUT_CSC_C31_C32, DCP, id), \
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+	SRI(OUTPUT_CSC_C33_C34, DCP, id), \
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+	SRI(OUTPUT_CSC_CONTROL, DCP, id), \
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+	SRI(REGAMMA_CNTLA_START_CNTL, DCP, id), \
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+	SRI(REGAMMA_CNTLA_SLOPE_CNTL, DCP, id), \
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+	SRI(REGAMMA_CNTLA_END_CNTL1, DCP, id), \
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+	SRI(REGAMMA_CNTLA_END_CNTL2, DCP, id), \
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+	SRI(REGAMMA_CNTLA_REGION_0_1, DCP, id), \
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+	SRI(REGAMMA_CNTLA_REGION_2_3, DCP, id), \
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+	SRI(REGAMMA_CNTLA_REGION_4_5, DCP, id), \
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+	SRI(REGAMMA_CNTLA_REGION_6_7, DCP, id), \
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+	SRI(REGAMMA_CNTLA_REGION_8_9, DCP, id), \
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+	SRI(REGAMMA_CNTLA_REGION_10_11, DCP, id), \
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+	SRI(REGAMMA_CNTLA_REGION_12_13, DCP, id), \
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+	SRI(REGAMMA_CNTLA_REGION_14_15, DCP, id), \
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+	SRI(REGAMMA_LUT_WRITE_EN_MASK, DCP, id), \
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+	SRI(REGAMMA_LUT_INDEX, DCP, id), \
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+	SRI(REGAMMA_LUT_DATA, DCP, id), \
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+	SRI(REGAMMA_CONTROL, DCP, id), \
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+	SRI(DENORM_CONTROL, DCP, id), \
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+	SRI(DCP_SPATIAL_DITHER_CNTL, DCP, id), \
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+	SRI(OUT_ROUND_CONTROL, DCP, id), \
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+	SRI(SCL_TAP_CONTROL, SCL, id), \
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+	SRI(SCL_CONTROL, SCL, id), \
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+	SRI(SCL_BYPASS_CONTROL, SCL, id), \
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+	SRI(EXT_OVERSCAN_LEFT_RIGHT, SCL, id), \
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+	SRI(EXT_OVERSCAN_TOP_BOTTOM, SCL, id), \
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+	SRI(SCL_VERT_FILTER_CONTROL, SCL, id), \
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+	SRI(SCL_HORZ_FILTER_CONTROL, SCL, id), \
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+	SRI(SCL_COEF_RAM_SELECT, SCL, id), \
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+	SRI(SCL_COEF_RAM_TAP_DATA, SCL, id), \
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+	SRI(VIEWPORT_START, SCL, id), \
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+	SRI(VIEWPORT_SIZE, SCL, id), \
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+	SRI(SCL_HORZ_FILTER_SCALE_RATIO, SCL, id), \
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+	SRI(SCL_VERT_FILTER_SCALE_RATIO, SCL, id), \
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+	SRI(SCL_VERT_FILTER_INIT, SCL, id), \
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+	SRI(SCL_AUTOMATIC_MODE_CONTROL, SCL, id), \
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+	SRI(DC_LB_MEMORY_SPLIT, LB, id), \
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+	SRI(DC_LB_MEM_SIZE, LB, id), \
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+	SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id), \
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+	SRI(SCL_UPDATE, SCL, id), \
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+	SRI(SCL_F_SHARP_CONTROL, SCL, id)
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+
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+#define XFM_COMMON_REG_LIST_DCE60(id) \
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+	XFM_COMMON_REG_LIST_DCE60_BASE(id), \
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+	SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id)
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+#endif
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+
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 #define XFM_SF(reg_name, field_name, post_fix)\
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 	.field_name = reg_name ## __ ## field_name ## post_fix
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@@ -203,6 +265,83 @@
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 	XFM_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\
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 	XFM_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\
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 	XFM_SF(SCL_MODE, SCL_PSCL_EN, mask_sh)
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+
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+#if defined(CONFIG_DRM_AMD_DC_SI)
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+#define XFM_COMMON_MASK_SH_LIST_DCE60(mask_sh) \
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+	XFM_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(mask_sh), \
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+	OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_LIGHT_SLEEP_DIS, mask_sh),\
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+	OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, DCP_LUT_LIGHT_SLEEP_DIS, mask_sh),\
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+	OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, mask_sh)
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+
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+#define XFM_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(mask_sh) \
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+	XFM_SF(OUT_ROUND_CONTROL, OUT_ROUND_TRUNC_MODE, mask_sh), \
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+	XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_EN, mask_sh), \
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+	XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_MODE, mask_sh), \
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+	XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_DEPTH, mask_sh), \
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+	XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_FRAME_RANDOM_ENABLE, mask_sh), \
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+	XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_RGB_RANDOM_ENABLE, mask_sh), \
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+	XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_HIGHPASS_RANDOM_ENABLE, mask_sh), \
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+	XFM_SF(DENORM_CONTROL, DENORM_MODE, mask_sh), \
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+	XFM_SF(DATA_FORMAT, INTERLEAVE_EN, mask_sh), \
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+	XFM_SF(GAMUT_REMAP_C11_C12, GAMUT_REMAP_C11, mask_sh), \
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+	XFM_SF(GAMUT_REMAP_C11_C12, GAMUT_REMAP_C12, mask_sh), \
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+	XFM_SF(GAMUT_REMAP_C13_C14, GAMUT_REMAP_C13, mask_sh), \
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+	XFM_SF(GAMUT_REMAP_C13_C14, GAMUT_REMAP_C14, mask_sh), \
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+	XFM_SF(GAMUT_REMAP_C21_C22, GAMUT_REMAP_C21, mask_sh), \
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+	XFM_SF(GAMUT_REMAP_C21_C22, GAMUT_REMAP_C22, mask_sh), \
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+	XFM_SF(GAMUT_REMAP_C23_C24, GAMUT_REMAP_C23, mask_sh), \
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+	XFM_SF(GAMUT_REMAP_C23_C24, GAMUT_REMAP_C24, mask_sh), \
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+	XFM_SF(GAMUT_REMAP_C31_C32, GAMUT_REMAP_C31, mask_sh), \
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+	XFM_SF(GAMUT_REMAP_C31_C32, GAMUT_REMAP_C32, mask_sh), \
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+	XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C33, mask_sh), \
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+	XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \
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+	XFM_SF(GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \
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+	XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\
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+	XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\
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+	XFM_SF(OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\
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+	XFM_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\
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+	XFM_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\
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+	XFM_SF(REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\
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+	XFM_SF(REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\
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+	XFM_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\
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+	XFM_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\
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+	XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\
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+	XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
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+	XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\
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+	XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
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+	XFM_SF(REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\
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+	XFM_SF(REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\
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+	XFM_SF(SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \
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+	XFM_SF(SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \
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+	XFM_SF(SCL_BYPASS_CONTROL, SCL_BYPASS_MODE, mask_sh), \
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+	XFM_SF(EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh), \
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+	XFM_SF(EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh), \
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+	XFM_SF(EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh), \
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+	XFM_SF(EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh), \
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+	XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE, mask_sh), \
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+	XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_PHASE, mask_sh), \
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+	XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX, mask_sh), \
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+	XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF_EN, mask_sh), \
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+	XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF, mask_sh), \
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+	XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF_EN, mask_sh), \
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+	XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF, mask_sh), \
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+	XFM_SF(VIEWPORT_START, VIEWPORT_X_START, mask_sh), \
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+	XFM_SF(VIEWPORT_START, VIEWPORT_Y_START, mask_sh), \
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+	XFM_SF(VIEWPORT_SIZE, VIEWPORT_HEIGHT, mask_sh), \
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+	XFM_SF(VIEWPORT_SIZE, VIEWPORT_WIDTH, mask_sh), \
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+	XFM_SF(SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh), \
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+	XFM_SF(SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh), \
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+	XFM_SF(SCL_HORZ_FILTER_INIT_RGB_LUMA, SCL_H_INIT_INT_RGB_Y, mask_sh), \
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+	XFM_SF(SCL_HORZ_FILTER_INIT_RGB_LUMA, SCL_H_INIT_FRAC_RGB_Y, mask_sh), \
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+	XFM_SF(SCL_HORZ_FILTER_INIT_CHROMA, SCL_H_INIT_INT_CBCR, mask_sh), \
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+	XFM_SF(SCL_HORZ_FILTER_INIT_CHROMA, SCL_H_INIT_FRAC_CBCR, mask_sh), \
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+	XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh), \
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+	XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh), \
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+	XFM_SF(SCL_HORZ_FILTER_CONTROL, SCL_H_FILTER_PICK_NEAREST, mask_sh), \
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+	XFM_SF(SCL_VERT_FILTER_CONTROL, SCL_V_FILTER_PICK_NEAREST, mask_sh), \
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+	XFM_SF(DC_LB_MEMORY_SPLIT, DC_LB_MEMORY_CONFIG, mask_sh), \
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+	XFM_SF(DC_LB_MEM_SIZE, DC_LB_MEM_SIZE, mask_sh)
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+#endif
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345
 
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 #define XFM_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \
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 	XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MIN_B_CB, mask_sh), \
..
..
@@ -302,6 +441,7 @@
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 	type DCP_RGB_RANDOM_ENABLE; \
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 	type DCP_HIGHPASS_RANDOM_ENABLE; \
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 	type DENORM_MODE; \
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+	type INTERLEAVE_EN; \
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 	type PIXEL_DEPTH; \
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 	type PIXEL_EXPAN_MODE; \
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 	type GAMUT_REMAP_C11; \
..
..
@@ -365,12 +505,20 @@
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 	type SCL_V_SCALE_RATIO; \
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 	type SCL_H_INIT_INT; \
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 	type SCL_H_INIT_FRAC; \
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+	type SCL_H_INIT_INT_RGB_Y; \
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+	type SCL_H_INIT_FRAC_RGB_Y; \
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+	type SCL_H_INIT_INT_CBCR; \
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+	type SCL_H_INIT_FRAC_CBCR; \
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 	type SCL_V_INIT_INT; \
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 	type SCL_V_INIT_FRAC; \
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+	type DC_LB_MEMORY_CONFIG; \
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+	type DC_LB_MEM_SIZE; \
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 	type LB_MEMORY_CONFIG; \
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 	type LB_MEMORY_SIZE; \
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 	type SCL_V_2TAP_HARDCODE_COEF_EN; \
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 	type SCL_H_2TAP_HARDCODE_COEF_EN; \
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+	type SCL_V_FILTER_PICK_NEAREST; \
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+	type SCL_H_FILTER_PICK_NEAREST; \
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 	type SCL_COEF_UPDATE_COMPLETE; \
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 	type ALPHA_EN
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524
 
..
..
@@ -383,6 +531,9 @@
383
531
 };
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532
 
385
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 struct dce_transform_registers {
534
+#if defined(CONFIG_DRM_AMD_DC_SI)
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+	uint32_t DATA_FORMAT;
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+#endif
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 	uint32_t LB_DATA_FORMAT;
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 	uint32_t GAMUT_REMAP_CONTROL;
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 	uint32_t GAMUT_REMAP_C11_C12;
..
..
@@ -438,8 +589,16 @@
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 	uint32_t SCL_HORZ_FILTER_SCALE_RATIO;
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 	uint32_t SCL_VERT_FILTER_SCALE_RATIO;
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 	uint32_t SCL_HORZ_FILTER_INIT;
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+#if defined(CONFIG_DRM_AMD_DC_SI)
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+	uint32_t SCL_HORZ_FILTER_INIT_RGB_LUMA;
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+	uint32_t SCL_HORZ_FILTER_INIT_CHROMA;
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+#endif
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 	uint32_t SCL_VERT_FILTER_INIT;
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 	uint32_t SCL_AUTOMATIC_MODE_CONTROL;
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+#if defined(CONFIG_DRM_AMD_DC_SI)
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+	uint32_t DC_LB_MEMORY_SPLIT;
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+	uint32_t DC_LB_MEM_SIZE;
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+#endif
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 	uint32_t LB_MEMORY_CTRL;
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 	uint32_t SCL_UPDATE;
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604
 	uint32_t SCL_F_SHARP_CONTROL;
..
..
@@ -456,6 +615,16 @@
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 	struct init_int_and_frac h_init;
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 	struct init_int_and_frac v_init;
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 };
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+
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+#if defined(CONFIG_DRM_AMD_DC_SI)
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+struct sclh_ratios_inits {
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+	uint32_t h_int_scale_ratio;
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+	uint32_t v_int_scale_ratio;
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+	struct init_int_and_frac h_init_luma;
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+	struct init_int_and_frac h_init_chroma;
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+	struct init_int_and_frac v_init;
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+};
627
+#endif
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628
 
460
629
 enum ram_filter_type {
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 	FILTER_TYPE_RGB_Y_VERTICAL	= 0, /* 0 - RGB/Y Vertical filter */
..
..
@@ -489,6 +658,15 @@
489
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 	const struct dce_transform_shift *xfm_shift,
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 	const struct dce_transform_mask *xfm_mask);
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660
 
661
+#if defined(CONFIG_DRM_AMD_DC_SI)
662
+void dce60_transform_construct(struct dce_transform *xfm_dce,
663
+	struct dc_context *ctx,
664
+	uint32_t inst,
665
+	const struct dce_transform_registers *regs,
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+	const struct dce_transform_shift *xfm_shift,
667
+	const struct dce_transform_mask *xfm_mask);
668
+#endif
669
+
492
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 bool dce_transform_get_optimal_number_of_taps(
493
671
 	struct transform *xfm,
494
672
 	struct scaler_data *scl_data,