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2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da 
 kernel/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
....@@ -23,6 +23,8 @@
2323  *
2424  */
2525 
26
+#include <linux/delay.h>
27
+
2628 #include "dc_bios_types.h"
2729 #include "dce_stream_encoder.h"
2830 #include "reg_helper.h"
....@@ -135,7 +137,7 @@
135137 			AFMT_GENERIC0_UPDATE, (packet_index == 0),
136138 			AFMT_GENERIC2_UPDATE, (packet_index == 2));
137139 	}
138
-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
140
+#if defined(CONFIG_DRM_AMD_DC_DCN)
139141 	if (REG(AFMT_VBI_PACKET_CONTROL1)) {
140142 		switch (packet_index) {
141143 		case 0:
....@@ -229,7 +231,7 @@
229231 				HDMI_GENERIC1_SEND, send,
230232 				HDMI_GENERIC1_LINE, line);
231233 		break;
232
-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
234
+#if defined(CONFIG_DRM_AMD_DC_DCN)
233235 	case 4:
234236 		if (REG(HDMI_GENERIC_PACKET_CONTROL2))
235237 			REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
....@@ -272,9 +274,11 @@
272274 static void dce110_stream_encoder_dp_set_stream_attribute(
273275 	struct stream_encoder *enc,
274276 	struct dc_crtc_timing *crtc_timing,
275
-	enum dc_color_space output_color_space)
277
+	enum dc_color_space output_color_space,
278
+	bool use_vsc_sdp_for_colorimetry,
279
+	uint32_t enable_sdp_splitting)
276280 {
277
-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
281
+#if defined(CONFIG_DRM_AMD_DC_DCN)
278282 	uint32_t h_active_start;
279283 	uint32_t v_active_start;
280284 	uint32_t misc0 = 0;
....@@ -288,9 +292,18 @@
288292 #endif
289293 
290294 	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
291
-
295
+	struct dc_crtc_timing hw_crtc_timing = *crtc_timing;
296
+	if (hw_crtc_timing.flags.INTERLACE) {
297
+		/*the input timing is in VESA spec format with Interlace flag =1*/
298
+		hw_crtc_timing.v_total /= 2;
299
+		hw_crtc_timing.v_border_top /= 2;
300
+		hw_crtc_timing.v_addressable /= 2;
301
+		hw_crtc_timing.v_border_bottom /= 2;
302
+		hw_crtc_timing.v_front_porch /= 2;
303
+		hw_crtc_timing.v_sync_width /= 2;
304
+	}
292305 	/* set pixel encoding */
293
-	switch (crtc_timing->pixel_encoding) {
306
+	switch (hw_crtc_timing.pixel_encoding) {
294307 	case PIXEL_ENCODING_YCBCR422:
295308 		REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
296309 				DP_PIXEL_ENCODING_TYPE_YCBCR422);
....@@ -299,8 +312,8 @@
299312 		REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
300313 				DP_PIXEL_ENCODING_TYPE_YCBCR444);
301314 
302
-		if (crtc_timing->flags.Y_ONLY)
303
-			if (crtc_timing->display_color_depth != COLOR_DEPTH_666)
315
+		if (hw_crtc_timing.flags.Y_ONLY)
316
+			if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666)
304317 				/* HW testing only, no use case yet.
305318 				 * Color depth of Y-only could be
306319 				 * 8, 10, 12, 16 bits */
....@@ -317,7 +330,7 @@
317330 		if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN)
318331 			REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);
319332 
320
-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
333
+#if defined(CONFIG_DRM_AMD_DC_DCN)
321334 		if (enc110->se_mask->DP_VID_N_MUL)
322335 			REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
323336 #endif
....@@ -328,14 +341,14 @@
328341 		break;
329342 	}
330343 
331
-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
344
+#if defined(CONFIG_DRM_AMD_DC_DCN)
332345 	if (REG(DP_MSA_MISC))
333346 		misc1 = REG_READ(DP_MSA_MISC);
334347 #endif
335348 
336349 	/* set color depth */
337350 
338
-	switch (crtc_timing->display_color_depth) {
351
+	switch (hw_crtc_timing.display_color_depth) {
339352 	case COLOR_DEPTH_666:
340353 		REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
341354 				0);
....@@ -362,8 +375,8 @@
362375 	/* set dynamic range and YCbCr range */
363376 
364377 
365
-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
366
-	switch (crtc_timing->display_color_depth) {
378
+#if defined(CONFIG_DRM_AMD_DC_DCN)
379
+	switch (hw_crtc_timing.display_color_depth) {
367380 	case COLOR_DEPTH_666:
368381 		colorimetry_bpc = 0;
369382 		break;
....@@ -401,19 +414,20 @@
401414 			misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
402415 			misc1 = misc1 & ~0x80; /* bit7 = 0*/
403416 			dynamic_range_ycbcr = 0; /*bt601*/
404
-			if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
417
+			if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
405418 				misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
406
-			else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
419
+			else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
407420 				misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
408421 			break;
409422 		case COLOR_SPACE_YCBCR709:
410423 		case COLOR_SPACE_YCBCR709_LIMITED:
424
+		case COLOR_SPACE_YCBCR709_BLACK:
411425 			misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
412426 			misc1 = misc1 & ~0x80; /* bit7 = 0*/
413427 			dynamic_range_ycbcr = 1; /*bt709*/
414
-			if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
428
+			if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
415429 				misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
416
-			else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
430
+			else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
417431 				misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
418432 			break;
419433 		case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
....@@ -441,7 +455,7 @@
441455 				DP_DYN_RANGE, dynamic_range_rgb,
442456 				DP_YCBCR_RANGE, dynamic_range_ycbcr);
443457 
444
-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
458
+#if defined(CONFIG_DRM_AMD_DC_DCN)
445459 		if (REG(DP_MSA_COLORIMETRY))
446460 			REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
447461 
....@@ -453,30 +467,30 @@
453467 	 */
454468 		if (REG(DP_MSA_TIMING_PARAM1))
455469 			REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
456
-					DP_MSA_HTOTAL, crtc_timing->h_total,
457
-					DP_MSA_VTOTAL, crtc_timing->v_total);
470
+					DP_MSA_HTOTAL, hw_crtc_timing.h_total,
471
+					DP_MSA_VTOTAL, hw_crtc_timing.v_total);
458472 #endif
459473 
460474 		/* calcuate from vesa timing parameters
461475 		 * h_active_start related to leading edge of sync
462476 		 */
463477 
464
-		h_blank = crtc_timing->h_total - crtc_timing->h_border_left -
465
-				crtc_timing->h_addressable - crtc_timing->h_border_right;
478
+		h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left -
479
+				hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right;
466480 
467
-		h_back_porch = h_blank - crtc_timing->h_front_porch -
468
-				crtc_timing->h_sync_width;
481
+		h_back_porch = h_blank - hw_crtc_timing.h_front_porch -
482
+				hw_crtc_timing.h_sync_width;
469483 
470484 		/* start at begining of left border */
471
-		h_active_start = crtc_timing->h_sync_width + h_back_porch;
485
+		h_active_start = hw_crtc_timing.h_sync_width + h_back_porch;
472486 
473487 
474
-		v_active_start = crtc_timing->v_total - crtc_timing->v_border_top -
475
-				crtc_timing->v_addressable - crtc_timing->v_border_bottom -
476
-				crtc_timing->v_front_porch;
488
+		v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top -
489
+				hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom -
490
+				hw_crtc_timing.v_front_porch;
477491 
478492 
479
-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
493
+#if defined(CONFIG_DRM_AMD_DC_DCN)
480494 		/* start at begining of left border */
481495 		if (REG(DP_MSA_TIMING_PARAM2))
482496 			REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
....@@ -486,21 +500,21 @@
486500 		if (REG(DP_MSA_TIMING_PARAM3))
487501 			REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
488502 					DP_MSA_HSYNCWIDTH,
489
-					crtc_timing->h_sync_width,
503
+					hw_crtc_timing.h_sync_width,
490504 					DP_MSA_HSYNCPOLARITY,
491
-					!crtc_timing->flags.HSYNC_POSITIVE_POLARITY,
505
+					!hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY,
492506 					DP_MSA_VSYNCWIDTH,
493
-					crtc_timing->v_sync_width,
507
+					hw_crtc_timing.v_sync_width,
494508 					DP_MSA_VSYNCPOLARITY,
495
-					!crtc_timing->flags.VSYNC_POSITIVE_POLARITY);
509
+					!hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY);
496510 
497511 		/* HWDITH include border or overscan */
498512 		if (REG(DP_MSA_TIMING_PARAM4))
499513 			REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
500
-				DP_MSA_HWIDTH, crtc_timing->h_border_left +
501
-				crtc_timing->h_addressable + crtc_timing->h_border_right,
502
-				DP_MSA_VHEIGHT, crtc_timing->v_border_top +
503
-				crtc_timing->v_addressable + crtc_timing->v_border_bottom);
514
+				DP_MSA_HWIDTH, hw_crtc_timing.h_border_left +
515
+				hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right,
516
+				DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top +
517
+				hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom);
504518 #endif
505519 	}
506520 #endif
....@@ -550,6 +564,7 @@
550564 	cntl.enable_dp_audio = enable_audio;
551565 	cntl.pixel_clock = actual_pix_clk_khz;
552566 	cntl.lanes_number = LANE_COUNT_FOUR;
567
+	cntl.color_depth = crtc_timing->display_color_depth;
553568 
554569 	if (enc110->base.bp->funcs->encoder_control(
555570 			enc110->base.bp, &cntl) != BP_RESULT_OK)
....@@ -662,7 +677,7 @@
662677 	cntl.signal = is_dual_link ?
663678 			SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
664679 	cntl.enable_dp_audio = false;
665
-	cntl.pixel_clock = crtc_timing->pix_clk_khz;
680
+	cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
666681 	cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
667682 
668683 	if (enc110->base.bp->funcs->encoder_control(
....@@ -674,7 +689,29 @@
674689 	dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
675690 }
676691 
677
-static void dce110_stream_encoder_set_mst_bandwidth(
692
+/* setup stream encoder in LVDS mode */
693
+static void dce110_stream_encoder_lvds_set_stream_attribute(
694
+	struct stream_encoder *enc,
695
+	struct dc_crtc_timing *crtc_timing)
696
+{
697
+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
698
+	struct bp_encoder_control cntl = {0};
699
+
700
+	cntl.action = ENCODER_CONTROL_SETUP;
701
+	cntl.engine_id = enc110->base.id;
702
+	cntl.signal = SIGNAL_TYPE_LVDS;
703
+	cntl.enable_dp_audio = false;
704
+	cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
705
+	cntl.lanes_number = LANE_COUNT_FOUR;
706
+
707
+	if (enc110->base.bp->funcs->encoder_control(
708
+			enc110->base.bp, &cntl) != BP_RESULT_OK)
709
+		return;
710
+
711
+	ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
712
+}
713
+
714
+static void dce110_stream_encoder_set_throttled_vcp_size(
678715 	struct stream_encoder *enc,
679716 	struct fixed31_32 avg_time_slots_per_mtp)
680717 {
....@@ -751,7 +788,7 @@
751788 		dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd);
752789 	}
753790 
754
-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
791
+#if defined(CONFIG_DRM_AMD_DC_DCN)
755792 	if (enc110->se_mask->HDMI_DB_DISABLE) {
756793 		/* for bring up, disable dp double  TODO */
757794 		if (REG(HDMI_DB_CONTROL))
....@@ -789,7 +826,7 @@
789826 		HDMI_GENERIC1_LINE, 0,
790827 		HDMI_GENERIC1_SEND, 0);
791828 
792
-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
829
+#if defined(CONFIG_DRM_AMD_DC_DCN)
793830 	/* stop generic packets 2 & 3 on HDMI */
794831 	if (REG(HDMI_GENERIC_PACKET_CONTROL2))
795832 		REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
....@@ -886,7 +923,6 @@
886923 	struct stream_encoder *enc)
887924 {
888925 	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
889
-	uint32_t retries = 0;
890926 	uint32_t  reg1 = 0;
891927 	uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
892928 
....@@ -904,30 +940,28 @@
904940 	 * (2 = start of the next vertical blank) */
905941 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
906942 	/* Larger delay to wait until VBLANK - use max retry of
907
-	* 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
908
-	* a little more because we may not trust delay accuracy.
909
-	*/
943
+	 * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
944
+	 * a little more because we may not trust delay accuracy.
945
+	 */
910946 	max_retries = DP_BLANK_MAX_RETRY * 150;
911947 
912948 	/* disable DP stream */
913949 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
914950 
915951 	/* the encoder stops sending the video stream
916
-	* at the start of the vertical blanking.
917
-	* Poll for DP_VID_STREAM_STATUS == 0
918
-	*/
952
+	 * at the start of the vertical blanking.
953
+	 * Poll for DP_VID_STREAM_STATUS == 0
954
+	 */
919955 
920956 	REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
921957 			0,
922958 			10, max_retries);
923959 
924
-	ASSERT(retries <= max_retries);
925
-
926960 	/* Tell the DP encoder to ignore timing from CRTC, must be done after
927
-	* the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
928
-	* complete, stream status will be stuck in video stream enabled state,
929
-	* i.e. DP_VID_STREAM_STATUS stuck at 1.
930
-	*/
961
+	 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
962
+	 * complete, stream status will be stuck in video stream enabled state,
963
+	 * i.e. DP_VID_STREAM_STATUS stuck at 1.
964
+	 */
931965 
932966 	REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
933967 }
....@@ -949,7 +983,7 @@
949983 
950984 		uint64_t m_vid_l = n_vid;
951985 
952
-		m_vid_l *= param->pixel_clk_khz;
986
+		m_vid_l *= param->timing.pix_clk_100hz / 10;
953987 		m_vid_l = div_u64(m_vid_l,
954988 			param->link_settings.link_rate
955989 				* LINK_RATE_REF_FREQ_IN_KHZ);
....@@ -1005,6 +1039,24 @@
10051039 	REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
10061040 }
10071041 
1042
+
1043
+static void dce110_reset_hdmi_stream_attribute(
1044
+	struct stream_encoder *enc)
1045
+{
1046
+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1047
+	if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN)
1048
+		REG_UPDATE_5(HDMI_CONTROL,
1049
+			HDMI_PACKET_GEN_VERSION, 1,
1050
+			HDMI_KEEPOUT_MODE, 1,
1051
+			HDMI_DEEP_COLOR_ENABLE, 0,
1052
+			HDMI_DATA_SCRAMBLE_EN, 0,
1053
+			HDMI_CLOCK_CHANNEL_RATE, 0);
1054
+	else
1055
+		REG_UPDATE_3(HDMI_CONTROL,
1056
+			HDMI_PACKET_GEN_VERSION, 1,
1057
+			HDMI_KEEPOUT_MODE, 1,
1058
+			HDMI_DEEP_COLOR_ENABLE, 0);
1059
+}
10081060 
10091061 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
10101062 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
....@@ -1092,19 +1144,6 @@
10921144 		uint32_t RC_RLC_FLC:1;
10931145 		uint32_t RRC_FRC:1;
10941146 	} channels;
1095
-};
1096
-
1097
-struct audio_clock_info {
1098
-	/* pixel clock frequency*/
1099
-	uint32_t pixel_clock_in_10khz;
1100
-	/* N - 32KHz audio */
1101
-	uint32_t n_32khz;
1102
-	/* CTS - 32KHz audio*/
1103
-	uint32_t cts_32khz;
1104
-	uint32_t n_44khz;
1105
-	uint32_t cts_44khz;
1106
-	uint32_t n_48khz;
1107
-	uint32_t cts_48khz;
11081147 };
11091148 
11101149 /* 25.2MHz/1.001*/
....@@ -1232,13 +1271,13 @@
12321271 
12331272 static void get_audio_clock_info(
12341273 	enum dc_color_depth color_depth,
1235
-	uint32_t crtc_pixel_clock_in_khz,
1236
-	uint32_t actual_pixel_clock_in_khz,
1274
+	uint32_t crtc_pixel_clock_100Hz,
1275
+	uint32_t actual_pixel_clock_100Hz,
12371276 	struct audio_clock_info *audio_clock_info)
12381277 {
12391278 	const struct audio_clock_info *clock_info;
12401279 	uint32_t index;
1241
-	uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10;
1280
+	uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100;
12421281 	uint32_t audio_array_size;
12431282 
12441283 	switch (color_depth) {
....@@ -1275,16 +1314,16 @@
12751314 	}
12761315 
12771316 	/* not found */
1278
-	if (actual_pixel_clock_in_khz == 0)
1279
-		actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz;
1317
+	if (actual_pixel_clock_100Hz == 0)
1318
+		actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz;
12801319 
12811320 	/* See HDMI spec  the table entry under
12821321 	 *  pixel clock of "Other". */
12831322 	audio_clock_info->pixel_clock_in_10khz =
1284
-			actual_pixel_clock_in_khz / 10;
1285
-	audio_clock_info->cts_32khz = actual_pixel_clock_in_khz;
1286
-	audio_clock_info->cts_44khz = actual_pixel_clock_in_khz;
1287
-	audio_clock_info->cts_48khz = actual_pixel_clock_in_khz;
1323
+			actual_pixel_clock_100Hz / 100;
1324
+	audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10;
1325
+	audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10;
1326
+	audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10;
12881327 
12891328 	audio_clock_info->n_32khz = 4096;
12901329 	audio_clock_info->n_44khz = 6272;
....@@ -1298,7 +1337,6 @@
12981337 {
12991338 	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
13001339 
1301
-	uint32_t speakers = 0;
13021340 	uint32_t channels = 0;
13031341 
13041342 	ASSERT(audio_info);
....@@ -1306,7 +1344,6 @@
13061344 		/* This should not happen.it does so we don't get BSOD*/
13071345 		return;
13081346 
1309
-	speakers = audio_info->flags.info.ALLSPEAKERS;
13101347 	channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
13111348 
13121349 	/* setup the audio stream source select (audio -> dig mapping) */
....@@ -1350,14 +1387,14 @@
13501387 
13511388 	/* Program audio clock sample/regeneration parameters */
13521389 	get_audio_clock_info(crtc_info->color_depth,
1353
-			     crtc_info->requested_pixel_clock,
1354
-			     crtc_info->calculated_pixel_clock,
1390
+			     crtc_info->requested_pixel_clock_100Hz,
1391
+			     crtc_info->calculated_pixel_clock_100Hz,
13551392 			     &audio_clock_info);
13561393 	DC_LOG_HW_AUDIO(
1357
-			"\n%s:Input::requested_pixel_clock = %d"	\
1358
-			"calculated_pixel_clock = %d \n", __func__,	\
1359
-			crtc_info->requested_pixel_clock,		\
1360
-			crtc_info->calculated_pixel_clock);
1394
+			"\n%s:Input::requested_pixel_clock_100Hz = %d"	\
1395
+			"calculated_pixel_clock_100Hz = %d \n", __func__,	\
1396
+			crtc_info->requested_pixel_clock_100Hz,		\
1397
+			crtc_info->calculated_pixel_clock_100Hz);
13611398 
13621399 	/* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
13631400 	REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
....@@ -1556,6 +1593,25 @@
15561593 	REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
15571594 }
15581595 
1596
+static void dig_connect_to_otg(
1597
+	struct stream_encoder *enc,
1598
+	int tg_inst)
1599
+{
1600
+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1601
+
1602
+	REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
1603
+}
1604
+
1605
+static unsigned int dig_source_otg(
1606
+	struct stream_encoder *enc)
1607
+{
1608
+	uint32_t tg_inst = 0;
1609
+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1610
+
1611
+	REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst);
1612
+
1613
+	return tg_inst;
1614
+}
15591615 
15601616 static const struct stream_encoder_funcs dce110_str_enc_funcs = {
15611617 	.dp_set_stream_attribute =
....@@ -1564,8 +1620,10 @@
15641620 		dce110_stream_encoder_hdmi_set_stream_attribute,
15651621 	.dvi_set_stream_attribute =
15661622 		dce110_stream_encoder_dvi_set_stream_attribute,
1567
-	.set_mst_bandwidth =
1568
-		dce110_stream_encoder_set_mst_bandwidth,
1623
+	.lvds_set_stream_attribute =
1624
+		dce110_stream_encoder_lvds_set_stream_attribute,
1625
+	.set_throttled_vcp_size =
1626
+		dce110_stream_encoder_set_throttled_vcp_size,
15691627 	.update_hdmi_info_packets =
15701628 		dce110_stream_encoder_update_hdmi_info_packets,
15711629 	.stop_hdmi_info_packets =
....@@ -1588,7 +1646,9 @@
15881646 	.hdmi_audio_disable = dce110_se_hdmi_audio_disable,
15891647 	.setup_stereo_sync  = setup_stereo_sync,
15901648 	.set_avmute = dce110_stream_encoder_set_avmute,
1591
-
1649
+	.dig_connect_to_otg  = dig_connect_to_otg,
1650
+	.hdmi_reset_stream_attribute = dce110_reset_hdmi_stream_attribute,
1651
+	.dig_source_otg = dig_source_otg,
15921652 };
15931653 
15941654 void dce110_stream_encoder_construct(