add wifi6 8852be driver

hc

2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da

 kernel/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
..
..
@@ -58,6 +58,31 @@
58
58
 	SRI(DVMM_PTE_CONTROL, DCP, id),\
59
59
 	SRI(DVMM_PTE_ARB_CONTROL, DCP, id)
60
60
 
61
+#if defined(CONFIG_DRM_AMD_DC_SI)
62
+#define MI_DCE6_REG_LIST(id)\
63
+	SRI(GRPH_ENABLE, DCP, id),\
64
+	SRI(GRPH_CONTROL, DCP, id),\
65
+	SRI(GRPH_X_START, DCP, id),\
66
+	SRI(GRPH_Y_START, DCP, id),\
67
+	SRI(GRPH_X_END, DCP, id),\
68
+	SRI(GRPH_Y_END, DCP, id),\
69
+	SRI(GRPH_PITCH, DCP, id),\
70
+	SRI(GRPH_SWAP_CNTL, DCP, id),\
71
+	SRI(PRESCALE_GRPH_CONTROL, DCP, id),\
72
+	SRI(GRPH_UPDATE, DCP, id),\
73
+	SRI(GRPH_FLIP_CONTROL, DCP, id),\
74
+	SRI(GRPH_PRIMARY_SURFACE_ADDRESS, DCP, id),\
75
+	SRI(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, DCP, id),\
76
+	SRI(GRPH_SECONDARY_SURFACE_ADDRESS, DCP, id),\
77
+	SRI(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, DCP, id),\
78
+	SRI(DPG_PIPE_ARBITRATION_CONTROL1, DMIF_PG, id),\
79
+	SRI(DPG_PIPE_ARBITRATION_CONTROL3, DMIF_PG, id),\
80
+	SRI(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, DMIF_PG, id),\
81
+	SRI(DPG_PIPE_URGENCY_CONTROL, DMIF_PG, id),\
82
+	SRI(DPG_PIPE_STUTTER_CONTROL, DMIF_PG, id),\
83
+	SRI(DMIF_BUFFER_CONTROL, PIPE, id)
84
+#endif
85
+
61
86
 #define MI_DCE8_REG_LIST(id)\
62
87
 	MI_DCE_BASE_REG_LIST(id),\
63
88
 	SRI(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, DMIF_PG, id)
..
..
@@ -104,6 +129,9 @@
104
129
 	uint32_t GRPH_SECONDARY_SURFACE_ADDRESS_HIGH;
105
130
 	/* DMIF_PG */
106
131
 	uint32_t DPG_PIPE_ARBITRATION_CONTROL1;
132
+#if defined(CONFIG_DRM_AMD_DC_SI)
133
+	uint32_t DPG_PIPE_ARBITRATION_CONTROL3;
134
+#endif
107
135
 	uint32_t DPG_WATERMARK_MASK_CONTROL;
108
136
 	uint32_t DPG_PIPE_URGENCY_CONTROL;
109
137
 	uint32_t DPG_PIPE_URGENT_LEVEL_CONTROL;
..
..
@@ -125,6 +153,18 @@
125
153
 /* Set_Filed_for_Block */
126
154
 #define SFB(blk_name, reg_name, field_name, post_fix)\
127
155
 	.field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
156
+
157
+#if defined(CONFIG_DRM_AMD_DC_SI)
158
+#define MI_GFX6_TILE_MASK_SH_LIST(mask_sh, blk)\
159
+	SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
160
+	SFB(blk, GRPH_CONTROL, GRPH_BANK_WIDTH, mask_sh),\
161
+	SFB(blk, GRPH_CONTROL, GRPH_BANK_HEIGHT, mask_sh),\
162
+	SFB(blk, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, mask_sh),\
163
+	SFB(blk, GRPH_CONTROL, GRPH_TILE_SPLIT, mask_sh),\
164
+	SFB(blk, GRPH_CONTROL, GRPH_PIPE_CONFIG, mask_sh),\
165
+	SFB(blk, GRPH_CONTROL, GRPH_ARRAY_MODE, mask_sh),\
166
+	SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh)
167
+#endif
128
168
 
129
169
 #define MI_GFX8_TILE_MASK_SH_LIST(mask_sh, blk)\
130
170
 	SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
..
..
@@ -162,6 +202,32 @@
162
202
 	SFB(blk, GRPH_UPDATE, GRPH_UPDATE_LOCK, mask_sh),\
163
203
 	SFB(blk, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN, mask_sh)
164
204
 
205
+#if defined(CONFIG_DRM_AMD_DC_SI)
206
+#define MI_DCP_MASK_SH_LIST_DCE6(mask_sh, blk)\
207
+	SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\
208
+	SFB(blk, GRPH_CONTROL, GRPH_DEPTH, mask_sh),\
209
+	SFB(blk, GRPH_CONTROL, GRPH_FORMAT, mask_sh),\
210
+	SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
211
+	SFB(blk, GRPH_X_START, GRPH_X_START, mask_sh),\
212
+	SFB(blk, GRPH_Y_START, GRPH_Y_START, mask_sh),\
213
+	SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\
214
+	SFB(blk, GRPH_Y_END, GRPH_Y_END, mask_sh),\
215
+	SFB(blk, GRPH_PITCH, GRPH_PITCH, mask_sh),\
216
+	SFB(blk, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, mask_sh),\
217
+	SFB(blk, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, mask_sh),\
218
+	SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_SELECT, mask_sh),\
219
+	SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_R_SIGN, mask_sh),\
220
+	SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_G_SIGN, mask_sh),\
221
+	SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_B_SIGN, mask_sh),\
222
+	SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
223
+	SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_SURFACE_ADDRESS, mask_sh),\
224
+	SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
225
+	SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS, GRPH_PRIMARY_SURFACE_ADDRESS, mask_sh),\
226
+	SFB(blk, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING, mask_sh),\
227
+	SFB(blk, GRPH_UPDATE, GRPH_UPDATE_LOCK, mask_sh),\
228
+	SFB(blk, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN, mask_sh)
229
+#endif
230
+
165
231
 #define MI_DCP_DCE11_MASK_SH_LIST(mask_sh, blk)\
166
232
 	SFB(blk, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, mask_sh)
167
233
 
..
..
@@ -171,6 +237,33 @@
171
237
 	SFB(blk, DVMM_PTE_CONTROL, DVMM_MIN_PTE_BEFORE_FLIP, mask_sh),\
172
238
 	SFB(blk, DVMM_PTE_ARB_CONTROL, DVMM_PTE_REQ_PER_CHUNK, mask_sh),\
173
239
 	SFB(blk, DVMM_PTE_ARB_CONTROL, DVMM_MAX_PTE_REQ_OUTSTANDING, mask_sh)
240
+
241
+#if defined(CONFIG_DRM_AMD_DC_SI)
242
+#define MI_DMIF_PG_MASK_SH_LIST_DCE6(mask_sh, blk)\
243
+	SFB(blk, DPG_PIPE_ARBITRATION_CONTROL1, PIXEL_DURATION, mask_sh),\
244
+	SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, mask_sh),\
245
+	SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, mask_sh),\
246
+	SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE, mask_sh),\
247
+	SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_IGNORE_FBC, mask_sh),\
248
+	SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\
249
+	SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh)
250
+
251
+#define MI_DMIF_PG_MASK_SH_DCE6(mask_sh, blk)\
252
+	SFB(blk, DPG_PIPE_ARBITRATION_CONTROL3, URGENCY_WATERMARK_MASK, mask_sh),\
253
+	SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, mask_sh),\
254
+	SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\
255
+	SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
256
+	SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_ENABLE, mask_sh),\
257
+	SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
258
+	SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\
259
+	SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_WATERMARK, mask_sh)
260
+
261
+#define MI_DCE6_MASK_SH_LIST(mask_sh)\
262
+	MI_DCP_MASK_SH_LIST_DCE6(mask_sh, ),\
263
+	MI_DMIF_PG_MASK_SH_LIST_DCE6(mask_sh, ),\
264
+	MI_DMIF_PG_MASK_SH_DCE6(mask_sh, ),\
265
+	MI_GFX6_TILE_MASK_SH_LIST(mask_sh, )
266
+#endif
174
267
 
175
268
 #define MI_DMIF_PG_MASK_SH_LIST(mask_sh, blk)\
176
269
 	SFB(blk, DPG_PIPE_ARBITRATION_CONTROL1, PIXEL_DURATION, mask_sh),\
..
..
@@ -345,6 +438,16 @@
345
438
 	const struct dce_mem_input_shift *mi_shift,
346
439
 	const struct dce_mem_input_mask *mi_mask);
347
440
 
441
+#if defined(CONFIG_DRM_AMD_DC_SI)
442
+void dce60_mem_input_construct(
443
+	struct dce_mem_input *dce_mi,
444
+	struct dc_context *ctx,
445
+	int inst,
446
+	const struct dce_mem_input_registers *regs,
447
+	const struct dce_mem_input_shift *mi_shift,
448
+	const struct dce_mem_input_mask *mi_mask);
449
+#endif
450
+
348
451
 void dce112_mem_input_construct(
349
452
 	struct dce_mem_input *dce_mi,
350
453
 	struct dc_context *ctx,