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2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da 
 kernel/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
....@@ -148,7 +148,7 @@
148148 			pte->min_pte_before_flip_horiz_scan;
149149 
150150 	REG_UPDATE(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT,
151
-			GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, 0xff);
151
+			GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, 0x7f);
152152 
153153 	REG_UPDATE_3(DVMM_PTE_CONTROL,
154154 			DVMM_PAGE_WIDTH, page_width,
....@@ -157,7 +157,7 @@
157157 
158158 	REG_UPDATE_2(DVMM_PTE_ARB_CONTROL,
159159 			DVMM_PTE_REQ_PER_CHUNK, pte->pte_req_per_chunk,
160
-			DVMM_MAX_PTE_REQ_OUTSTANDING, 0xff);
160
+			DVMM_MAX_PTE_REQ_OUTSTANDING, 0x7f);
161161 }
162162 
163163 static void program_urgency_watermark(
....@@ -173,6 +173,22 @@
173173 		URGENCY_LOW_WATERMARK, urgency_low_wm,
174174 		URGENCY_HIGH_WATERMARK, urgency_high_wm);
175175 }
176
+
177
+#if defined(CONFIG_DRM_AMD_DC_SI)
178
+static void dce60_program_urgency_watermark(
179
+	struct dce_mem_input *dce_mi,
180
+	uint32_t wm_select,
181
+	uint32_t urgency_low_wm,
182
+	uint32_t urgency_high_wm)
183
+{
184
+	REG_UPDATE(DPG_PIPE_ARBITRATION_CONTROL3,
185
+		URGENCY_WATERMARK_MASK, wm_select);
186
+
187
+	REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0,
188
+		URGENCY_LOW_WATERMARK, urgency_low_wm,
189
+		URGENCY_HIGH_WATERMARK, urgency_high_wm);
190
+}
191
+#endif
176192 
177193 static void dce120_program_urgency_watermark(
178194 	struct dce_mem_input *dce_mi,
....@@ -192,6 +208,25 @@
192208 		URGENT_LEVEL_HIGH_WATERMARK, urgency_high_wm);
193209 
194210 }
211
+
212
+#if defined(CONFIG_DRM_AMD_DC_SI)
213
+static void dce60_program_nbp_watermark(
214
+	struct dce_mem_input *dce_mi,
215
+	uint32_t wm_select,
216
+	uint32_t nbp_wm)
217
+{
218
+	REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
219
+		NB_PSTATE_CHANGE_WATERMARK_MASK, wm_select);
220
+
221
+	REG_UPDATE_3(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
222
+		NB_PSTATE_CHANGE_ENABLE, 1,
223
+		NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, 1,
224
+		NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, 1);
225
+
226
+	REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
227
+		NB_PSTATE_CHANGE_WATERMARK, nbp_wm);
228
+}
229
+#endif
195230 
196231 static void program_nbp_watermark(
197232 	struct dce_mem_input *dce_mi,
....@@ -224,6 +259,20 @@
224259 				PSTATE_CHANGE_WATERMARK, nbp_wm);
225260 	}
226261 }
262
+
263
+#if defined(CONFIG_DRM_AMD_DC_SI)
264
+static void dce60_program_stutter_watermark(
265
+	struct dce_mem_input *dce_mi,
266
+	uint32_t wm_select,
267
+	uint32_t stutter_mark)
268
+{
269
+	REG_UPDATE(DPG_PIPE_STUTTER_CONTROL,
270
+		STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, wm_select);
271
+
272
+	REG_UPDATE(DPG_PIPE_STUTTER_CONTROL,
273
+		STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark);
274
+}
275
+#endif
227276 
228277 static void dce120_program_stutter_watermark(
229278 	struct dce_mem_input *dce_mi,
....@@ -285,6 +334,34 @@
285334 	program_stutter_watermark(dce_mi, 2, stutter_exit.a_mark); /* set a */
286335 	program_stutter_watermark(dce_mi, 1, stutter_exit.d_mark); /* set d */
287336 }
337
+
338
+#if defined(CONFIG_DRM_AMD_DC_SI)
339
+static void dce60_mi_program_display_marks(
340
+	struct mem_input *mi,
341
+	struct dce_watermarks nbp,
342
+	struct dce_watermarks stutter_exit,
343
+	struct dce_watermarks stutter_enter,
344
+	struct dce_watermarks urgent,
345
+	uint32_t total_dest_line_time_ns)
346
+{
347
+	struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
348
+	uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;
349
+
350
+	dce60_program_urgency_watermark(dce_mi, 2, /* set a */
351
+			urgent.a_mark, total_dest_line_time_ns);
352
+	dce60_program_urgency_watermark(dce_mi, 1, /* set d */
353
+			urgent.d_mark, total_dest_line_time_ns);
354
+
355
+	REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,
356
+		STUTTER_ENABLE, stutter_en,
357
+		STUTTER_IGNORE_FBC, 1);
358
+	dce60_program_nbp_watermark(dce_mi, 2, nbp.a_mark); /* set a */
359
+	dce60_program_nbp_watermark(dce_mi, 1, nbp.d_mark); /* set d */
360
+
361
+	dce60_program_stutter_watermark(dce_mi, 2, stutter_exit.a_mark); /* set a */
362
+	dce60_program_stutter_watermark(dce_mi, 1, stutter_exit.d_mark); /* set d */
363
+}
364
+#endif
288365 
289366 static void dce112_mi_program_display_marks(struct mem_input *mi,
290367 	struct dce_watermarks nbp,
....@@ -369,7 +446,7 @@
369446 		 */
370447 	}
371448 
372
-	if (dce_mi->masks->GRPH_ARRAY_MODE) { /* GFX8 */
449
+	if (dce_mi->masks->GRPH_MICRO_TILE_MODE) { /* GFX8 */
373450 		REG_UPDATE_9(GRPH_CONTROL,
374451 				GRPH_NUM_BANKS, info->gfx8.num_banks,
375452 				GRPH_BANK_WIDTH, info->gfx8.bank_width,
....@@ -385,16 +462,33 @@
385462 				GRPH_Z, 0);
386463 				*/
387464 	}
465
+
466
+	if (dce_mi->masks->GRPH_ARRAY_MODE) { /* GFX6 but reuses gfx8 struct */
467
+		REG_UPDATE_8(GRPH_CONTROL,
468
+				GRPH_NUM_BANKS, info->gfx8.num_banks,
469
+				GRPH_BANK_WIDTH, info->gfx8.bank_width,
470
+				GRPH_BANK_HEIGHT, info->gfx8.bank_height,
471
+				GRPH_MACRO_TILE_ASPECT, info->gfx8.tile_aspect,
472
+				GRPH_TILE_SPLIT, info->gfx8.tile_split,
473
+				/* DCE6 has no GRPH_MICRO_TILE_MODE mask */
474
+				GRPH_PIPE_CONFIG, info->gfx8.pipe_config,
475
+				GRPH_ARRAY_MODE, info->gfx8.array_mode,
476
+				GRPH_COLOR_EXPANSION_MODE, 1);
477
+		/* 01 - DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP: zero expansion for YCbCr */
478
+		/*
479
+				GRPH_Z, 0);
480
+				*/
481
+	}
388482 }
389483 
390484 
391485 static void program_size_and_rotation(
392486 	struct dce_mem_input *dce_mi,
393487 	enum dc_rotation_angle rotation,
394
-	const union plane_size *plane_size)
488
+	const struct plane_size *plane_size)
395489 {
396
-	const struct rect *in_rect = &plane_size->grph.surface_size;
397
-	struct rect hw_rect = plane_size->grph.surface_size;
490
+	const struct rect *in_rect = &plane_size->surface_size;
491
+	struct rect hw_rect = plane_size->surface_size;
398492 	const uint32_t rotation_angles[ROTATION_ANGLE_COUNT] = {
399493 			[ROTATION_ANGLE_0] = 0,
400494 			[ROTATION_ANGLE_90] = 1,
....@@ -423,11 +517,41 @@
423517 			GRPH_Y_END, hw_rect.height);
424518 
425519 	REG_SET(GRPH_PITCH, 0,
426
-			GRPH_PITCH, plane_size->grph.surface_pitch);
520
+			GRPH_PITCH, plane_size->surface_pitch);
427521 
428522 	REG_SET(HW_ROTATION, 0,
429523 			GRPH_ROTATION_ANGLE, rotation_angles[rotation]);
430524 }
525
+
526
+#if defined(CONFIG_DRM_AMD_DC_SI)
527
+static void dce60_program_size(
528
+	struct dce_mem_input *dce_mi,
529
+	enum dc_rotation_angle rotation, /* not used in DCE6 */
530
+	const struct plane_size *plane_size)
531
+{
532
+	struct rect hw_rect = plane_size->surface_size;
533
+	/* DCE6 has no HW rotation, skip rotation_angles declaration */
534
+
535
+	/* DCE6 has no HW rotation, skip ROTATION_ANGLE_* processing */
536
+
537
+	REG_SET(GRPH_X_START, 0,
538
+			GRPH_X_START, hw_rect.x);
539
+
540
+	REG_SET(GRPH_Y_START, 0,
541
+			GRPH_Y_START, hw_rect.y);
542
+
543
+	REG_SET(GRPH_X_END, 0,
544
+			GRPH_X_END, hw_rect.width);
545
+
546
+	REG_SET(GRPH_Y_END, 0,
547
+			GRPH_Y_END, hw_rect.height);
548
+
549
+	REG_SET(GRPH_PITCH, 0,
550
+			GRPH_PITCH, plane_size->surface_pitch);
551
+
552
+	/* DCE6 has no HW_ROTATION register, skip setting rotation_angles */
553
+}
554
+#endif
431555 
432556 static void program_grph_pixel_format(
433557 	struct dce_mem_input *dce_mi,
....@@ -479,7 +603,7 @@
479603 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
480604 		sign = 1;
481605 		floating = 1;
482
-		/* no break */
606
+		fallthrough;
483607 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: /* shouldn't this get float too? */
484608 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
485609 		grph_depth = 3;
....@@ -505,7 +629,7 @@
505629 	struct mem_input *mi,
506630 	enum surface_pixel_format format,
507631 	union dc_tiling_info *tiling_info,
508
-	union plane_size *plane_size,
632
+	struct plane_size *plane_size,
509633 	enum dc_rotation_angle rotation,
510634 	struct dc_plane_dcc_param *dcc,
511635 	bool horizontal_mirror)
....@@ -520,6 +644,28 @@
520644 		format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
521645 		program_grph_pixel_format(dce_mi, format);
522646 }
647
+
648
+#if defined(CONFIG_DRM_AMD_DC_SI)
649
+static void dce60_mi_program_surface_config(
650
+	struct mem_input *mi,
651
+	enum surface_pixel_format format,
652
+	union dc_tiling_info *tiling_info,
653
+	struct plane_size *plane_size,
654
+	enum dc_rotation_angle rotation, /* not used in DCE6 */
655
+	struct dc_plane_dcc_param *dcc,
656
+	bool horizontal_mirror)
657
+{
658
+	struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
659
+	REG_UPDATE(GRPH_ENABLE, GRPH_ENABLE, 1);
660
+
661
+	program_tiling(dce_mi, tiling_info);
662
+	dce60_program_size(dce_mi, rotation, plane_size);
663
+
664
+	if (format >= SURFACE_PIXEL_FORMAT_GRPH_BEGIN &&
665
+		format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
666
+		program_grph_pixel_format(dce_mi, format);
667
+}
668
+#endif
523669 
524670 static uint32_t get_dmif_switch_time_us(
525671 	uint32_t h_total,
....@@ -606,11 +752,11 @@
606752 	}
607753 
608754 	if (dce_mi->wa.single_head_rdreq_dmif_limit) {
609
-		uint32_t eanble =  (total_stream_num > 1) ? 0 :
755
+		uint32_t enable =  (total_stream_num > 1) ? 0 :
610756 				dce_mi->wa.single_head_rdreq_dmif_limit;
611757 
612758 		REG_UPDATE(MC_HUB_RDREQ_DMIF_LIMIT,
613
-				ENABLE, eanble);
759
+				ENABLE, enable);
614760 	}
615761 }
616762 
....@@ -636,11 +782,11 @@
636782 			10, 3500);
637783 
638784 	if (dce_mi->wa.single_head_rdreq_dmif_limit) {
639
-		uint32_t eanble =  (total_stream_num > 1) ? 0 :
785
+		uint32_t enable =  (total_stream_num > 1) ? 0 :
640786 				dce_mi->wa.single_head_rdreq_dmif_limit;
641787 
642788 		REG_UPDATE(MC_HUB_RDREQ_DMIF_LIMIT,
643
-				ENABLE, eanble);
789
+				ENABLE, enable);
644790 	}
645791 }
646792 
....@@ -741,6 +887,20 @@
741887 	.mem_input_is_flip_pending = dce_mi_is_flip_pending
742888 };
743889 
890
+#if defined(CONFIG_DRM_AMD_DC_SI)
891
+static const struct mem_input_funcs dce60_mi_funcs = {
892
+	.mem_input_program_display_marks = dce60_mi_program_display_marks,
893
+	.allocate_mem_input = dce_mi_allocate_dmif,
894
+	.free_mem_input = dce_mi_free_dmif,
895
+	.mem_input_program_surface_flip_and_addr =
896
+			dce_mi_program_surface_flip_and_addr,
897
+	.mem_input_program_pte_vm = dce_mi_program_pte_vm,
898
+	.mem_input_program_surface_config =
899
+			dce60_mi_program_surface_config,
900
+	.mem_input_is_flip_pending = dce_mi_is_flip_pending
901
+};
902
+#endif
903
+
744904 static const struct mem_input_funcs dce112_mi_funcs = {
745905 	.mem_input_program_display_marks = dce112_mi_program_display_marks,
746906 	.allocate_mem_input = dce_mi_allocate_dmif,
....@@ -783,6 +943,20 @@
783943 	dce_mi->masks = mi_mask;
784944 }
785945 
946
+#if defined(CONFIG_DRM_AMD_DC_SI)
947
+void dce60_mem_input_construct(
948
+	struct dce_mem_input *dce_mi,
949
+	struct dc_context *ctx,
950
+	int inst,
951
+	const struct dce_mem_input_registers *regs,
952
+	const struct dce_mem_input_shift *mi_shift,
953
+	const struct dce_mem_input_mask *mi_mask)
954
+{
955
+	dce_mem_input_construct(dce_mi, ctx, inst, regs, mi_shift, mi_mask);
956
+	dce_mi->base.funcs = &dce60_mi_funcs;
957
+}
958
+#endif
959
+
786960 void dce112_mem_input_construct(
787961 	struct dce_mem_input *dce_mi,
788962 	struct dc_context *ctx,