.. | .. |
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55 | 55 | static void init_dac_encoder_control(struct bios_parser *bp); |
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56 | 56 | static void init_dac_output_control(struct bios_parser *bp); |
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57 | 57 | static void init_set_crtc_timing(struct bios_parser *bp); |
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58 | | -static void init_select_crtc_source(struct bios_parser *bp); |
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59 | 58 | static void init_enable_crtc(struct bios_parser *bp); |
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60 | 59 | static void init_enable_crtc_mem_req(struct bios_parser *bp); |
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61 | 60 | static void init_external_encoder_control(struct bios_parser *bp); |
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.. | .. |
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73 | 72 | init_dac_encoder_control(bp); |
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74 | 73 | init_dac_output_control(bp); |
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75 | 74 | init_set_crtc_timing(bp); |
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76 | | - init_select_crtc_source(bp); |
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77 | 75 | init_enable_crtc(bp); |
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78 | 76 | init_enable_crtc_mem_req(bp); |
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79 | 77 | init_program_clock(bp); |
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.. | .. |
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247 | 245 | cntl->enable_dp_audio); |
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248 | 246 | params.ucLaneNum = (uint8_t)(cntl->lanes_number); |
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249 | 247 | |
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| 248 | + switch (cntl->color_depth) { |
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| 249 | + case COLOR_DEPTH_888: |
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| 250 | + params.ucBitPerColor = PANEL_8BIT_PER_COLOR; |
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| 251 | + break; |
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| 252 | + case COLOR_DEPTH_101010: |
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| 253 | + params.ucBitPerColor = PANEL_10BIT_PER_COLOR; |
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| 254 | + break; |
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| 255 | + case COLOR_DEPTH_121212: |
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| 256 | + params.ucBitPerColor = PANEL_12BIT_PER_COLOR; |
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| 257 | + break; |
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| 258 | + case COLOR_DEPTH_161616: |
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| 259 | + params.ucBitPerColor = PANEL_16BIT_PER_COLOR; |
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| 260 | + break; |
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| 261 | + default: |
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| 262 | + break; |
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| 263 | + } |
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| 264 | + |
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250 | 265 | if (EXEC_BIOS_CMD_TABLE(DIGxEncoderControl, params)) |
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251 | 266 | result = BP_RESULT_OK; |
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252 | 267 | |
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.. | .. |
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275 | 290 | cntl->signal, |
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276 | 291 | cntl->enable_dp_audio)); |
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277 | 292 | params.ucLaneNum = (uint8_t)(cntl->lanes_number); |
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| 293 | + |
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| 294 | + switch (cntl->color_depth) { |
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| 295 | + case COLOR_DEPTH_888: |
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| 296 | + params.ucBitPerColor = PANEL_8BIT_PER_COLOR; |
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| 297 | + break; |
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| 298 | + case COLOR_DEPTH_101010: |
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| 299 | + params.ucBitPerColor = PANEL_10BIT_PER_COLOR; |
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| 300 | + break; |
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| 301 | + case COLOR_DEPTH_121212: |
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| 302 | + params.ucBitPerColor = PANEL_12BIT_PER_COLOR; |
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| 303 | + break; |
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| 304 | + case COLOR_DEPTH_161616: |
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| 305 | + params.ucBitPerColor = PANEL_16BIT_PER_COLOR; |
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| 306 | + break; |
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| 307 | + default: |
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| 308 | + break; |
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| 309 | + } |
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278 | 310 | |
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279 | 311 | if (EXEC_BIOS_CMD_TABLE(DIGxEncoderControl, params)) |
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280 | 312 | result = BP_RESULT_OK; |
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.. | .. |
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964 | 996 | allocation.sPCLKInput.ucPostDiv = |
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965 | 997 | (uint8_t)bp_params->pixel_clock_post_divider; |
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966 | 998 | |
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967 | | - /* We need to convert from KHz units into 10KHz units */ |
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| 999 | + /* We need to convert from 100Hz units into 10KHz units */ |
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968 | 1000 | allocation.sPCLKInput.usPixelClock = |
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969 | | - cpu_to_le16((uint16_t)(bp_params->target_pixel_clock / 10)); |
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| 1001 | + cpu_to_le16((uint16_t)(bp_params->target_pixel_clock_100hz / 100)); |
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970 | 1002 | |
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971 | 1003 | params = (PIXEL_CLOCK_PARAMETERS_V3 *)&allocation.sPCLKInput; |
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972 | 1004 | params->ucTransmitterId = |
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.. | .. |
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1042 | 1074 | (uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom( |
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1043 | 1075 | bp_params->signal_type, false); |
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1044 | 1076 | |
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1045 | | - /* We need to convert from KHz units into 10KHz units */ |
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| 1077 | + /* We need to convert from 100Hz units into 10KHz units */ |
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1046 | 1078 | clk.sPCLKInput.usPixelClock = |
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1047 | | - cpu_to_le16((uint16_t)(bp_params->target_pixel_clock / 10)); |
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| 1079 | + cpu_to_le16((uint16_t)(bp_params->target_pixel_clock_100hz / 100)); |
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1048 | 1080 | |
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1049 | 1081 | if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL) |
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1050 | 1082 | clk.sPCLKInput.ucMiscInfo |= |
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.. | .. |
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1059 | 1091 | * driver choose program it itself, i.e. here we program it |
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1060 | 1092 | * to 888 by default. |
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1061 | 1093 | */ |
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| 1094 | + if (bp_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) |
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| 1095 | + switch (bp_params->color_depth) { |
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| 1096 | + case TRANSMITTER_COLOR_DEPTH_30: |
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| 1097 | + /* yes this is correct, the atom define is wrong */ |
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| 1098 | + clk.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP; |
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| 1099 | + break; |
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| 1100 | + case TRANSMITTER_COLOR_DEPTH_36: |
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| 1101 | + /* yes this is correct, the atom define is wrong */ |
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| 1102 | + clk.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; |
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| 1103 | + break; |
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| 1104 | + default: |
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| 1105 | + break; |
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| 1106 | + } |
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1062 | 1107 | |
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1063 | 1108 | if (EXEC_BIOS_CMD_TABLE(SetPixelClock, clk)) |
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1064 | 1109 | result = BP_RESULT_OK; |
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.. | .. |
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1118 | 1163 | (uint8_t) bp->cmd_helper->encoder_mode_bp_to_atom( |
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1119 | 1164 | bp_params->signal_type, false); |
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1120 | 1165 | |
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1121 | | - /* We need to convert from KHz units into 10KHz units */ |
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| 1166 | + /* We need to convert from 100 Hz units into 10KHz units */ |
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1122 | 1167 | clk.sPCLKInput.ulCrtcPclkFreq.ulPixelClock = |
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1123 | | - cpu_to_le32(bp_params->target_pixel_clock / 10); |
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| 1168 | + cpu_to_le32(bp_params->target_pixel_clock_100hz / 100); |
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1124 | 1169 | |
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1125 | 1170 | if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL) { |
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1126 | 1171 | clk.sPCLKInput.ucMiscInfo |= |
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.. | .. |
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1137 | 1182 | * driver choose program it itself, i.e. here we pass required |
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1138 | 1183 | * target rate that includes deep color. |
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1139 | 1184 | */ |
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| 1185 | + if (bp_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) |
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| 1186 | + switch (bp_params->color_depth) { |
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| 1187 | + case TRANSMITTER_COLOR_DEPTH_30: |
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| 1188 | + clk.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6; |
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| 1189 | + break; |
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| 1190 | + case TRANSMITTER_COLOR_DEPTH_36: |
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| 1191 | + clk.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6; |
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| 1192 | + break; |
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| 1193 | + case TRANSMITTER_COLOR_DEPTH_48: |
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| 1194 | + clk.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; |
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| 1195 | + break; |
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| 1196 | + default: |
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| 1197 | + break; |
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| 1198 | + } |
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1140 | 1199 | |
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1141 | 1200 | if (EXEC_BIOS_CMD_TABLE(SetPixelClock, clk)) |
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1142 | 1201 | result = BP_RESULT_OK; |
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.. | .. |
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1182 | 1241 | clk.ucTransmitterID = bp->cmd_helper->encoder_id_to_atom(dal_graphics_object_id_get_encoder_id(bp_params->encoder_object_id)); |
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1183 | 1242 | clk.ucEncoderMode = (uint8_t) bp->cmd_helper->encoder_mode_bp_to_atom(bp_params->signal_type, false); |
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1184 | 1243 | |
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1185 | | - /* We need to convert from KHz units into 10KHz units */ |
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1186 | | - clk.ulPixelClock = cpu_to_le32(bp_params->target_pixel_clock * 10); |
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| 1244 | + clk.ulPixelClock = cpu_to_le32(bp_params->target_pixel_clock_100hz); |
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1187 | 1245 | |
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1188 | 1246 | clk.ucDeepColorRatio = (uint8_t) bp->cmd_helper->transmitter_color_depth_to_atom(bp_params->color_depth); |
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1189 | 1247 | |
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.. | .. |
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1880 | 1938 | * but it is 4 either from Edid data (spec CEA 861) |
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1881 | 1939 | * or CEA timing table. |
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1882 | 1940 | */ |
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1883 | | - params.usV_SyncOffset = |
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1884 | | - cpu_to_le16(le16_to_cpu(params.usV_SyncOffset) + 1); |
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1885 | | - |
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| 1941 | + le16_add_cpu(¶ms.usV_SyncOffset, 1); |
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1886 | 1942 | } |
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1887 | 1943 | } |
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1888 | 1944 | |
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.. | .. |
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1891 | 1947 | cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_DOUBLE_CLOCK_MODE); |
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1892 | 1948 | |
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1893 | 1949 | if (EXEC_BIOS_CMD_TABLE(SetCRTC_UsingDTDTiming, params)) |
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1894 | | - result = BP_RESULT_OK; |
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1895 | | - |
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1896 | | - return result; |
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1897 | | -} |
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1898 | | - |
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1899 | | -/******************************************************************************* |
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1900 | | - ******************************************************************************** |
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1901 | | - ** |
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1902 | | - ** SELECT CRTC SOURCE |
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1903 | | - ** |
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1904 | | - ******************************************************************************** |
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1905 | | - *******************************************************************************/ |
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1906 | | - |
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1907 | | -static enum bp_result select_crtc_source_v2( |
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1908 | | - struct bios_parser *bp, |
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1909 | | - struct bp_crtc_source_select *bp_params); |
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1910 | | -static enum bp_result select_crtc_source_v3( |
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1911 | | - struct bios_parser *bp, |
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1912 | | - struct bp_crtc_source_select *bp_params); |
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1913 | | - |
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1914 | | -static void init_select_crtc_source(struct bios_parser *bp) |
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1915 | | -{ |
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1916 | | - switch (BIOS_CMD_TABLE_PARA_REVISION(SelectCRTC_Source)) { |
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1917 | | - case 2: |
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1918 | | - bp->cmd_tbl.select_crtc_source = select_crtc_source_v2; |
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1919 | | - break; |
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1920 | | - case 3: |
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1921 | | - bp->cmd_tbl.select_crtc_source = select_crtc_source_v3; |
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1922 | | - break; |
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1923 | | - default: |
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1924 | | - dm_output_to_console("Don't select_crtc_source enable_crtc for v%d\n", |
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1925 | | - BIOS_CMD_TABLE_PARA_REVISION(SelectCRTC_Source)); |
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1926 | | - bp->cmd_tbl.select_crtc_source = NULL; |
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1927 | | - break; |
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1928 | | - } |
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1929 | | -} |
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1930 | | - |
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1931 | | -static enum bp_result select_crtc_source_v2( |
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1932 | | - struct bios_parser *bp, |
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1933 | | - struct bp_crtc_source_select *bp_params) |
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1934 | | -{ |
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1935 | | - enum bp_result result = BP_RESULT_FAILURE; |
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1936 | | - SELECT_CRTC_SOURCE_PARAMETERS_V2 params; |
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1937 | | - uint8_t atom_controller_id; |
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1938 | | - uint32_t atom_engine_id; |
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1939 | | - enum signal_type s = bp_params->signal; |
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1940 | | - |
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1941 | | - memset(¶ms, 0, sizeof(params)); |
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1942 | | - |
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1943 | | - /* set controller id */ |
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1944 | | - if (bp->cmd_helper->controller_id_to_atom( |
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1945 | | - bp_params->controller_id, &atom_controller_id)) |
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1946 | | - params.ucCRTC = atom_controller_id; |
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1947 | | - else |
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1948 | | - return BP_RESULT_FAILURE; |
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1949 | | - |
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1950 | | - /* set encoder id */ |
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1951 | | - if (bp->cmd_helper->engine_bp_to_atom( |
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1952 | | - bp_params->engine_id, &atom_engine_id)) |
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1953 | | - params.ucEncoderID = (uint8_t)atom_engine_id; |
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1954 | | - else |
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1955 | | - return BP_RESULT_FAILURE; |
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1956 | | - |
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1957 | | - if (SIGNAL_TYPE_EDP == s || |
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1958 | | - (SIGNAL_TYPE_DISPLAY_PORT == s && |
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1959 | | - SIGNAL_TYPE_LVDS == bp_params->sink_signal)) |
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1960 | | - s = SIGNAL_TYPE_LVDS; |
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1961 | | - |
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1962 | | - params.ucEncodeMode = |
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1963 | | - (uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom( |
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1964 | | - s, bp_params->enable_dp_audio); |
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1965 | | - |
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1966 | | - if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params)) |
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1967 | | - result = BP_RESULT_OK; |
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1968 | | - |
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1969 | | - return result; |
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1970 | | -} |
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1971 | | - |
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1972 | | -static enum bp_result select_crtc_source_v3( |
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1973 | | - struct bios_parser *bp, |
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1974 | | - struct bp_crtc_source_select *bp_params) |
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1975 | | -{ |
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1976 | | - bool result = BP_RESULT_FAILURE; |
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1977 | | - SELECT_CRTC_SOURCE_PARAMETERS_V3 params; |
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1978 | | - uint8_t atom_controller_id; |
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1979 | | - uint32_t atom_engine_id; |
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1980 | | - enum signal_type s = bp_params->signal; |
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1981 | | - |
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1982 | | - memset(¶ms, 0, sizeof(params)); |
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1983 | | - |
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1984 | | - if (bp->cmd_helper->controller_id_to_atom(bp_params->controller_id, |
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1985 | | - &atom_controller_id)) |
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1986 | | - params.ucCRTC = atom_controller_id; |
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1987 | | - else |
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1988 | | - return result; |
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1989 | | - |
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1990 | | - if (bp->cmd_helper->engine_bp_to_atom(bp_params->engine_id, |
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1991 | | - &atom_engine_id)) |
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1992 | | - params.ucEncoderID = (uint8_t)atom_engine_id; |
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1993 | | - else |
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1994 | | - return result; |
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1995 | | - |
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1996 | | - if (SIGNAL_TYPE_EDP == s || |
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1997 | | - (SIGNAL_TYPE_DISPLAY_PORT == s && |
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1998 | | - SIGNAL_TYPE_LVDS == bp_params->sink_signal)) |
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1999 | | - s = SIGNAL_TYPE_LVDS; |
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2000 | | - |
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2001 | | - params.ucEncodeMode = |
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2002 | | - bp->cmd_helper->encoder_mode_bp_to_atom( |
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2003 | | - s, bp_params->enable_dp_audio); |
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2004 | | - /* Needed for VBIOS Random Spatial Dithering feature */ |
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2005 | | - params.ucDstBpc = (uint8_t)(bp_params->display_output_bit_depth); |
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2006 | | - |
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2007 | | - if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params)) |
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2008 | 1950 | result = BP_RESULT_OK; |
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2009 | 1951 | |
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2010 | 1952 | return result; |
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.. | .. |
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2164 | 2106 | /* We need to convert from KHz units into 10KHz units */ |
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2165 | 2107 | params.sPCLKInput.ucPpll = (uint8_t) atom_pll_id; |
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2166 | 2108 | params.sPCLKInput.usPixelClock = |
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2167 | | - cpu_to_le16((uint16_t) (bp_params->target_pixel_clock / 10)); |
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| 2109 | + cpu_to_le16((uint16_t) (bp_params->target_pixel_clock_100hz / 100)); |
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2168 | 2110 | params.sPCLKInput.ucCRTC = (uint8_t) ATOM_CRTC_INVALID; |
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2169 | 2111 | |
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2170 | 2112 | if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC) |
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.. | .. |
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2196 | 2138 | /* We need to convert from KHz units into 10KHz units */ |
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2197 | 2139 | params.sPCLKInput.ucPpll = (uint8_t)atom_pll_id; |
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2198 | 2140 | params.sPCLKInput.ulDispEngClkFreq = |
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2199 | | - cpu_to_le32(bp_params->target_pixel_clock / 10); |
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| 2141 | + cpu_to_le32(bp_params->target_pixel_clock_100hz / 100); |
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2200 | 2142 | |
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2201 | 2143 | if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC) |
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2202 | 2144 | params.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; |
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2203 | 2145 | |
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| 2146 | + if (bp_params->flags.SET_DISPCLK_DFS_BYPASS) |
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| 2147 | + params.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_DPREFCLK_BYPASS; |
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| 2148 | + |
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2204 | 2149 | if (EXEC_BIOS_CMD_TABLE(SetPixelClock, params)) { |
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2205 | 2150 | /* True display clock is returned by VBIOS if DFS bypass |
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2206 | 2151 | * is enabled. */ |
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