hc
2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da
kernel/drivers/gpu/drm/amd/display/dc/bios/command_table.c
....@@ -55,7 +55,6 @@
5555 static void init_dac_encoder_control(struct bios_parser *bp);
5656 static void init_dac_output_control(struct bios_parser *bp);
5757 static void init_set_crtc_timing(struct bios_parser *bp);
58
-static void init_select_crtc_source(struct bios_parser *bp);
5958 static void init_enable_crtc(struct bios_parser *bp);
6059 static void init_enable_crtc_mem_req(struct bios_parser *bp);
6160 static void init_external_encoder_control(struct bios_parser *bp);
....@@ -73,7 +72,6 @@
7372 init_dac_encoder_control(bp);
7473 init_dac_output_control(bp);
7574 init_set_crtc_timing(bp);
76
- init_select_crtc_source(bp);
7775 init_enable_crtc(bp);
7876 init_enable_crtc_mem_req(bp);
7977 init_program_clock(bp);
....@@ -247,6 +245,23 @@
247245 cntl->enable_dp_audio);
248246 params.ucLaneNum = (uint8_t)(cntl->lanes_number);
249247
248
+ switch (cntl->color_depth) {
249
+ case COLOR_DEPTH_888:
250
+ params.ucBitPerColor = PANEL_8BIT_PER_COLOR;
251
+ break;
252
+ case COLOR_DEPTH_101010:
253
+ params.ucBitPerColor = PANEL_10BIT_PER_COLOR;
254
+ break;
255
+ case COLOR_DEPTH_121212:
256
+ params.ucBitPerColor = PANEL_12BIT_PER_COLOR;
257
+ break;
258
+ case COLOR_DEPTH_161616:
259
+ params.ucBitPerColor = PANEL_16BIT_PER_COLOR;
260
+ break;
261
+ default:
262
+ break;
263
+ }
264
+
250265 if (EXEC_BIOS_CMD_TABLE(DIGxEncoderControl, params))
251266 result = BP_RESULT_OK;
252267
....@@ -275,6 +290,23 @@
275290 cntl->signal,
276291 cntl->enable_dp_audio));
277292 params.ucLaneNum = (uint8_t)(cntl->lanes_number);
293
+
294
+ switch (cntl->color_depth) {
295
+ case COLOR_DEPTH_888:
296
+ params.ucBitPerColor = PANEL_8BIT_PER_COLOR;
297
+ break;
298
+ case COLOR_DEPTH_101010:
299
+ params.ucBitPerColor = PANEL_10BIT_PER_COLOR;
300
+ break;
301
+ case COLOR_DEPTH_121212:
302
+ params.ucBitPerColor = PANEL_12BIT_PER_COLOR;
303
+ break;
304
+ case COLOR_DEPTH_161616:
305
+ params.ucBitPerColor = PANEL_16BIT_PER_COLOR;
306
+ break;
307
+ default:
308
+ break;
309
+ }
278310
279311 if (EXEC_BIOS_CMD_TABLE(DIGxEncoderControl, params))
280312 result = BP_RESULT_OK;
....@@ -964,9 +996,9 @@
964996 allocation.sPCLKInput.ucPostDiv =
965997 (uint8_t)bp_params->pixel_clock_post_divider;
966998
967
- /* We need to convert from KHz units into 10KHz units */
999
+ /* We need to convert from 100Hz units into 10KHz units */
9681000 allocation.sPCLKInput.usPixelClock =
969
- cpu_to_le16((uint16_t)(bp_params->target_pixel_clock / 10));
1001
+ cpu_to_le16((uint16_t)(bp_params->target_pixel_clock_100hz / 100));
9701002
9711003 params = (PIXEL_CLOCK_PARAMETERS_V3 *)&allocation.sPCLKInput;
9721004 params->ucTransmitterId =
....@@ -1042,9 +1074,9 @@
10421074 (uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
10431075 bp_params->signal_type, false);
10441076
1045
- /* We need to convert from KHz units into 10KHz units */
1077
+ /* We need to convert from 100Hz units into 10KHz units */
10461078 clk.sPCLKInput.usPixelClock =
1047
- cpu_to_le16((uint16_t)(bp_params->target_pixel_clock / 10));
1079
+ cpu_to_le16((uint16_t)(bp_params->target_pixel_clock_100hz / 100));
10481080
10491081 if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL)
10501082 clk.sPCLKInput.ucMiscInfo |=
....@@ -1059,6 +1091,19 @@
10591091 * driver choose program it itself, i.e. here we program it
10601092 * to 888 by default.
10611093 */
1094
+ if (bp_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A)
1095
+ switch (bp_params->color_depth) {
1096
+ case TRANSMITTER_COLOR_DEPTH_30:
1097
+ /* yes this is correct, the atom define is wrong */
1098
+ clk.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP;
1099
+ break;
1100
+ case TRANSMITTER_COLOR_DEPTH_36:
1101
+ /* yes this is correct, the atom define is wrong */
1102
+ clk.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
1103
+ break;
1104
+ default:
1105
+ break;
1106
+ }
10621107
10631108 if (EXEC_BIOS_CMD_TABLE(SetPixelClock, clk))
10641109 result = BP_RESULT_OK;
....@@ -1118,9 +1163,9 @@
11181163 (uint8_t) bp->cmd_helper->encoder_mode_bp_to_atom(
11191164 bp_params->signal_type, false);
11201165
1121
- /* We need to convert from KHz units into 10KHz units */
1166
+ /* We need to convert from 100 Hz units into 10KHz units */
11221167 clk.sPCLKInput.ulCrtcPclkFreq.ulPixelClock =
1123
- cpu_to_le32(bp_params->target_pixel_clock / 10);
1168
+ cpu_to_le32(bp_params->target_pixel_clock_100hz / 100);
11241169
11251170 if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL) {
11261171 clk.sPCLKInput.ucMiscInfo |=
....@@ -1137,6 +1182,20 @@
11371182 * driver choose program it itself, i.e. here we pass required
11381183 * target rate that includes deep color.
11391184 */
1185
+ if (bp_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A)
1186
+ switch (bp_params->color_depth) {
1187
+ case TRANSMITTER_COLOR_DEPTH_30:
1188
+ clk.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6;
1189
+ break;
1190
+ case TRANSMITTER_COLOR_DEPTH_36:
1191
+ clk.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6;
1192
+ break;
1193
+ case TRANSMITTER_COLOR_DEPTH_48:
1194
+ clk.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
1195
+ break;
1196
+ default:
1197
+ break;
1198
+ }
11401199
11411200 if (EXEC_BIOS_CMD_TABLE(SetPixelClock, clk))
11421201 result = BP_RESULT_OK;
....@@ -1182,8 +1241,7 @@
11821241 clk.ucTransmitterID = bp->cmd_helper->encoder_id_to_atom(dal_graphics_object_id_get_encoder_id(bp_params->encoder_object_id));
11831242 clk.ucEncoderMode = (uint8_t) bp->cmd_helper->encoder_mode_bp_to_atom(bp_params->signal_type, false);
11841243
1185
- /* We need to convert from KHz units into 10KHz units */
1186
- clk.ulPixelClock = cpu_to_le32(bp_params->target_pixel_clock * 10);
1244
+ clk.ulPixelClock = cpu_to_le32(bp_params->target_pixel_clock_100hz);
11871245
11881246 clk.ucDeepColorRatio = (uint8_t) bp->cmd_helper->transmitter_color_depth_to_atom(bp_params->color_depth);
11891247
....@@ -1880,9 +1938,7 @@
18801938 * but it is 4 either from Edid data (spec CEA 861)
18811939 * or CEA timing table.
18821940 */
1883
- params.usV_SyncOffset =
1884
- cpu_to_le16(le16_to_cpu(params.usV_SyncOffset) + 1);
1885
-
1941
+ le16_add_cpu(&params.usV_SyncOffset, 1);
18861942 }
18871943 }
18881944
....@@ -1891,120 +1947,6 @@
18911947 cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_DOUBLE_CLOCK_MODE);
18921948
18931949 if (EXEC_BIOS_CMD_TABLE(SetCRTC_UsingDTDTiming, params))
1894
- result = BP_RESULT_OK;
1895
-
1896
- return result;
1897
-}
1898
-
1899
-/*******************************************************************************
1900
- ********************************************************************************
1901
- **
1902
- ** SELECT CRTC SOURCE
1903
- **
1904
- ********************************************************************************
1905
- *******************************************************************************/
1906
-
1907
-static enum bp_result select_crtc_source_v2(
1908
- struct bios_parser *bp,
1909
- struct bp_crtc_source_select *bp_params);
1910
-static enum bp_result select_crtc_source_v3(
1911
- struct bios_parser *bp,
1912
- struct bp_crtc_source_select *bp_params);
1913
-
1914
-static void init_select_crtc_source(struct bios_parser *bp)
1915
-{
1916
- switch (BIOS_CMD_TABLE_PARA_REVISION(SelectCRTC_Source)) {
1917
- case 2:
1918
- bp->cmd_tbl.select_crtc_source = select_crtc_source_v2;
1919
- break;
1920
- case 3:
1921
- bp->cmd_tbl.select_crtc_source = select_crtc_source_v3;
1922
- break;
1923
- default:
1924
- dm_output_to_console("Don't select_crtc_source enable_crtc for v%d\n",
1925
- BIOS_CMD_TABLE_PARA_REVISION(SelectCRTC_Source));
1926
- bp->cmd_tbl.select_crtc_source = NULL;
1927
- break;
1928
- }
1929
-}
1930
-
1931
-static enum bp_result select_crtc_source_v2(
1932
- struct bios_parser *bp,
1933
- struct bp_crtc_source_select *bp_params)
1934
-{
1935
- enum bp_result result = BP_RESULT_FAILURE;
1936
- SELECT_CRTC_SOURCE_PARAMETERS_V2 params;
1937
- uint8_t atom_controller_id;
1938
- uint32_t atom_engine_id;
1939
- enum signal_type s = bp_params->signal;
1940
-
1941
- memset(&params, 0, sizeof(params));
1942
-
1943
- /* set controller id */
1944
- if (bp->cmd_helper->controller_id_to_atom(
1945
- bp_params->controller_id, &atom_controller_id))
1946
- params.ucCRTC = atom_controller_id;
1947
- else
1948
- return BP_RESULT_FAILURE;
1949
-
1950
- /* set encoder id */
1951
- if (bp->cmd_helper->engine_bp_to_atom(
1952
- bp_params->engine_id, &atom_engine_id))
1953
- params.ucEncoderID = (uint8_t)atom_engine_id;
1954
- else
1955
- return BP_RESULT_FAILURE;
1956
-
1957
- if (SIGNAL_TYPE_EDP == s ||
1958
- (SIGNAL_TYPE_DISPLAY_PORT == s &&
1959
- SIGNAL_TYPE_LVDS == bp_params->sink_signal))
1960
- s = SIGNAL_TYPE_LVDS;
1961
-
1962
- params.ucEncodeMode =
1963
- (uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
1964
- s, bp_params->enable_dp_audio);
1965
-
1966
- if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params))
1967
- result = BP_RESULT_OK;
1968
-
1969
- return result;
1970
-}
1971
-
1972
-static enum bp_result select_crtc_source_v3(
1973
- struct bios_parser *bp,
1974
- struct bp_crtc_source_select *bp_params)
1975
-{
1976
- bool result = BP_RESULT_FAILURE;
1977
- SELECT_CRTC_SOURCE_PARAMETERS_V3 params;
1978
- uint8_t atom_controller_id;
1979
- uint32_t atom_engine_id;
1980
- enum signal_type s = bp_params->signal;
1981
-
1982
- memset(&params, 0, sizeof(params));
1983
-
1984
- if (bp->cmd_helper->controller_id_to_atom(bp_params->controller_id,
1985
- &atom_controller_id))
1986
- params.ucCRTC = atom_controller_id;
1987
- else
1988
- return result;
1989
-
1990
- if (bp->cmd_helper->engine_bp_to_atom(bp_params->engine_id,
1991
- &atom_engine_id))
1992
- params.ucEncoderID = (uint8_t)atom_engine_id;
1993
- else
1994
- return result;
1995
-
1996
- if (SIGNAL_TYPE_EDP == s ||
1997
- (SIGNAL_TYPE_DISPLAY_PORT == s &&
1998
- SIGNAL_TYPE_LVDS == bp_params->sink_signal))
1999
- s = SIGNAL_TYPE_LVDS;
2000
-
2001
- params.ucEncodeMode =
2002
- bp->cmd_helper->encoder_mode_bp_to_atom(
2003
- s, bp_params->enable_dp_audio);
2004
- /* Needed for VBIOS Random Spatial Dithering feature */
2005
- params.ucDstBpc = (uint8_t)(bp_params->display_output_bit_depth);
2006
-
2007
- if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params))
20081950 result = BP_RESULT_OK;
20091951
20101952 return result;
....@@ -2164,7 +2106,7 @@
21642106 /* We need to convert from KHz units into 10KHz units */
21652107 params.sPCLKInput.ucPpll = (uint8_t) atom_pll_id;
21662108 params.sPCLKInput.usPixelClock =
2167
- cpu_to_le16((uint16_t) (bp_params->target_pixel_clock / 10));
2109
+ cpu_to_le16((uint16_t) (bp_params->target_pixel_clock_100hz / 100));
21682110 params.sPCLKInput.ucCRTC = (uint8_t) ATOM_CRTC_INVALID;
21692111
21702112 if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC)
....@@ -2196,11 +2138,14 @@
21962138 /* We need to convert from KHz units into 10KHz units */
21972139 params.sPCLKInput.ucPpll = (uint8_t)atom_pll_id;
21982140 params.sPCLKInput.ulDispEngClkFreq =
2199
- cpu_to_le32(bp_params->target_pixel_clock / 10);
2141
+ cpu_to_le32(bp_params->target_pixel_clock_100hz / 100);
22002142
22012143 if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC)
22022144 params.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
22032145
2146
+ if (bp_params->flags.SET_DISPCLK_DFS_BYPASS)
2147
+ params.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_DPREFCLK_BYPASS;
2148
+
22042149 if (EXEC_BIOS_CMD_TABLE(SetPixelClock, params)) {
22052150 /* True display clock is returned by VBIOS if DFS bypass
22062151 * is enabled. */