.. | .. |
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26 | 26 | #ifndef __AMDGPU_DM_H__ |
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27 | 27 | #define __AMDGPU_DM_H__ |
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28 | 28 | |
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29 | | -#include <drm/drmP.h> |
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30 | 29 | #include <drm/drm_atomic.h> |
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| 30 | +#include <drm/drm_connector.h> |
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| 31 | +#include <drm/drm_crtc.h> |
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| 32 | +#include <drm/drm_dp_mst_helper.h> |
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| 33 | +#include <drm/drm_plane.h> |
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31 | 34 | |
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32 | 35 | /* |
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33 | 36 | * This file contains the definition for amdgpu_display_manager |
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.. | .. |
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40 | 43 | */ |
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41 | 44 | |
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42 | 45 | #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 |
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| 46 | + |
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| 47 | +#define AMDGPU_DM_MAX_CRTC 6 |
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| 48 | + |
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43 | 49 | /* |
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44 | 50 | #include "include/amdgpu_dal_power_if.h" |
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45 | 51 | #include "amdgpu_dm_irq.h" |
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.. | .. |
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47 | 53 | |
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48 | 54 | #include "irq_types.h" |
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49 | 55 | #include "signal_types.h" |
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| 56 | +#include "amdgpu_dm_crc.h" |
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50 | 57 | |
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51 | 58 | /* Forward declarations */ |
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52 | 59 | struct amdgpu_device; |
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53 | 60 | struct drm_device; |
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54 | 61 | struct amdgpu_dm_irq_handler_data; |
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55 | 62 | struct dc; |
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56 | | - |
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57 | | -struct amdgpu_dm_prev_state { |
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58 | | - struct drm_framebuffer *fb; |
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59 | | - int32_t x; |
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60 | | - int32_t y; |
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61 | | - struct drm_display_mode mode; |
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62 | | -}; |
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| 63 | +struct amdgpu_bo; |
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| 64 | +struct dmub_srv; |
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63 | 65 | |
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64 | 66 | struct common_irq_params { |
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65 | 67 | struct amdgpu_device *adev; |
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66 | 68 | enum dc_irq_source irq_src; |
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67 | 69 | }; |
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68 | 70 | |
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69 | | -struct irq_list_head { |
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70 | | - struct list_head head; |
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71 | | - /* In case this interrupt needs post-processing, 'work' will be queued*/ |
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72 | | - struct work_struct work; |
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73 | | -}; |
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74 | | - |
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75 | | -struct dm_comressor_info { |
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| 71 | +/** |
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| 72 | + * struct dm_compressor_info - Buffer info used by frame buffer compression |
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| 73 | + * @cpu_addr: MMIO cpu addr |
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| 74 | + * @bo_ptr: Pointer to the buffer object |
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| 75 | + * @gpu_addr: MMIO gpu addr |
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| 76 | + */ |
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| 77 | +struct dm_compressor_info { |
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76 | 78 | void *cpu_addr; |
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77 | 79 | struct amdgpu_bo *bo_ptr; |
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78 | 80 | uint64_t gpu_addr; |
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79 | 81 | }; |
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80 | 82 | |
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| 83 | +/** |
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| 84 | + * struct amdgpu_dm_backlight_caps - Information about backlight |
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| 85 | + * |
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| 86 | + * Describe the backlight support for ACPI or eDP AUX. |
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| 87 | + */ |
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| 88 | +struct amdgpu_dm_backlight_caps { |
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| 89 | + /** |
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| 90 | + * @ext_caps: Keep the data struct with all the information about the |
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| 91 | + * display support for HDR. |
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| 92 | + */ |
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| 93 | + union dpcd_sink_ext_caps *ext_caps; |
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| 94 | + /** |
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| 95 | + * @aux_min_input_signal: Min brightness value supported by the display |
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| 96 | + */ |
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| 97 | + u32 aux_min_input_signal; |
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| 98 | + /** |
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| 99 | + * @aux_max_input_signal: Max brightness value supported by the display |
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| 100 | + * in nits. |
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| 101 | + */ |
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| 102 | + u32 aux_max_input_signal; |
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| 103 | + /** |
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| 104 | + * @min_input_signal: minimum possible input in range 0-255. |
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| 105 | + */ |
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| 106 | + int min_input_signal; |
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| 107 | + /** |
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| 108 | + * @max_input_signal: maximum possible input in range 0-255. |
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| 109 | + */ |
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| 110 | + int max_input_signal; |
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| 111 | + /** |
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| 112 | + * @caps_valid: true if these values are from the ACPI interface. |
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| 113 | + */ |
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| 114 | + bool caps_valid; |
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| 115 | + /** |
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| 116 | + * @aux_support: Describes if the display supports AUX backlight. |
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| 117 | + */ |
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| 118 | + bool aux_support; |
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| 119 | +}; |
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81 | 120 | |
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| 121 | +/** |
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| 122 | + * struct amdgpu_display_manager - Central amdgpu display manager device |
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| 123 | + * |
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| 124 | + * @dc: Display Core control structure |
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| 125 | + * @adev: AMDGPU base driver structure |
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| 126 | + * @ddev: DRM base driver structure |
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| 127 | + * @display_indexes_num: Max number of display streams supported |
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| 128 | + * @irq_handler_list_table_lock: Synchronizes access to IRQ tables |
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| 129 | + * @backlight_dev: Backlight control device |
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| 130 | + * @backlight_link: Link on which to control backlight |
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| 131 | + * @backlight_caps: Capabilities of the backlight device |
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| 132 | + * @freesync_module: Module handling freesync calculations |
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| 133 | + * @hdcp_workqueue: AMDGPU content protection queue |
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| 134 | + * @fw_dmcu: Reference to DMCU firmware |
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| 135 | + * @dmcu_fw_version: Version of the DMCU firmware |
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| 136 | + * @soc_bounding_box: SOC bounding box values provided by gpu_info FW |
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| 137 | + * @cached_state: Caches device atomic state for suspend/resume |
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| 138 | + * @cached_dc_state: Cached state of content streams |
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| 139 | + * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info |
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| 140 | + * @force_timing_sync: set via debugfs. When set, indicates that all connected |
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| 141 | + * displays will be forced to synchronize. |
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| 142 | + */ |
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82 | 143 | struct amdgpu_display_manager { |
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83 | | - struct dal *dal; |
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| 144 | + |
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84 | 145 | struct dc *dc; |
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| 146 | + |
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| 147 | + /** |
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| 148 | + * @dmub_srv: |
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| 149 | + * |
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| 150 | + * DMUB service, used for controlling the DMUB on hardware |
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| 151 | + * that supports it. The pointer to the dmub_srv will be |
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| 152 | + * NULL on hardware that does not support it. |
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| 153 | + */ |
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| 154 | + struct dmub_srv *dmub_srv; |
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| 155 | + |
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| 156 | + /** |
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| 157 | + * @dmub_fb_info: |
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| 158 | + * |
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| 159 | + * Framebuffer regions for the DMUB. |
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| 160 | + */ |
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| 161 | + struct dmub_srv_fb_info *dmub_fb_info; |
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| 162 | + |
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| 163 | + /** |
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| 164 | + * @dmub_fw: |
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| 165 | + * |
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| 166 | + * DMUB firmware, required on hardware that has DMUB support. |
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| 167 | + */ |
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| 168 | + const struct firmware *dmub_fw; |
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| 169 | + |
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| 170 | + /** |
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| 171 | + * @dmub_bo: |
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| 172 | + * |
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| 173 | + * Buffer object for the DMUB. |
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| 174 | + */ |
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| 175 | + struct amdgpu_bo *dmub_bo; |
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| 176 | + |
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| 177 | + /** |
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| 178 | + * @dmub_bo_gpu_addr: |
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| 179 | + * |
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| 180 | + * GPU virtual address for the DMUB buffer object. |
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| 181 | + */ |
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| 182 | + u64 dmub_bo_gpu_addr; |
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| 183 | + |
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| 184 | + /** |
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| 185 | + * @dmub_bo_cpu_addr: |
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| 186 | + * |
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| 187 | + * CPU address for the DMUB buffer object. |
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| 188 | + */ |
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| 189 | + void *dmub_bo_cpu_addr; |
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| 190 | + |
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| 191 | + /** |
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| 192 | + * @dmcub_fw_version: |
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| 193 | + * |
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| 194 | + * DMCUB firmware version. |
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| 195 | + */ |
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| 196 | + uint32_t dmcub_fw_version; |
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| 197 | + |
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| 198 | + /** |
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| 199 | + * @cgs_device: |
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| 200 | + * |
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| 201 | + * The Common Graphics Services device. It provides an interface for |
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| 202 | + * accessing registers. |
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| 203 | + */ |
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85 | 204 | struct cgs_device *cgs_device; |
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86 | 205 | |
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87 | | - struct amdgpu_device *adev; /*AMD base driver*/ |
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88 | | - struct drm_device *ddev; /*DRM base driver*/ |
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| 206 | + struct amdgpu_device *adev; |
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| 207 | + struct drm_device *ddev; |
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89 | 208 | u16 display_indexes_num; |
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90 | 209 | |
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91 | | - struct amdgpu_dm_prev_state prev_state; |
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92 | | - |
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93 | | - /* |
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94 | | - * 'irq_source_handler_table' holds a list of handlers |
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95 | | - * per (DAL) IRQ source. |
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| 210 | + /** |
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| 211 | + * @atomic_obj: |
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96 | 212 | * |
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97 | | - * Each IRQ source may need to be handled at different contexts. |
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98 | | - * By 'context' we mean, for example: |
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99 | | - * - The ISR context, which is the direct interrupt handler. |
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100 | | - * - The 'deferred' context - this is the post-processing of the |
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101 | | - * interrupt, but at a lower priority. |
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| 213 | + * In combination with &dm_atomic_state it helps manage |
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| 214 | + * global atomic state that doesn't map cleanly into existing |
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| 215 | + * drm resources, like &dc_context. |
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| 216 | + */ |
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| 217 | + struct drm_private_obj atomic_obj; |
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| 218 | + |
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| 219 | + /** |
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| 220 | + * @dc_lock: |
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| 221 | + * |
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| 222 | + * Guards access to DC functions that can issue register write |
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| 223 | + * sequences. |
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| 224 | + */ |
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| 225 | + struct mutex dc_lock; |
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| 226 | + |
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| 227 | + /** |
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| 228 | + * @audio_lock: |
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| 229 | + * |
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| 230 | + * Guards access to audio instance changes. |
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| 231 | + */ |
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| 232 | + struct mutex audio_lock; |
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| 233 | + |
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| 234 | + /** |
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| 235 | + * @audio_component: |
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| 236 | + * |
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| 237 | + * Used to notify ELD changes to sound driver. |
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| 238 | + */ |
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| 239 | + struct drm_audio_component *audio_component; |
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| 240 | + |
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| 241 | + /** |
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| 242 | + * @audio_registered: |
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| 243 | + * |
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| 244 | + * True if the audio component has been registered |
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| 245 | + * successfully, false otherwise. |
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| 246 | + */ |
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| 247 | + bool audio_registered; |
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| 248 | + |
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| 249 | + /** |
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| 250 | + * @irq_handler_list_low_tab: |
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| 251 | + * |
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| 252 | + * Low priority IRQ handler table. |
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| 253 | + * |
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| 254 | + * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ |
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| 255 | + * source. Low priority IRQ handlers are deferred to a workqueue to be |
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| 256 | + * processed. Hence, they can sleep. |
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102 | 257 | * |
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103 | 258 | * Note that handlers are called in the same order as they were |
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104 | 259 | * registered (FIFO). |
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105 | 260 | */ |
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106 | | - struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; |
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| 261 | + struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; |
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| 262 | + |
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| 263 | + /** |
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| 264 | + * @irq_handler_list_high_tab: |
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| 265 | + * |
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| 266 | + * High priority IRQ handler table. |
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| 267 | + * |
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| 268 | + * It is a n*m table, same as &irq_handler_list_low_tab. However, |
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| 269 | + * handlers in this table are not deferred and are called immediately. |
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| 270 | + */ |
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107 | 271 | struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; |
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108 | 272 | |
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| 273 | + /** |
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| 274 | + * @pflip_params: |
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| 275 | + * |
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| 276 | + * Page flip IRQ parameters, passed to registered handlers when |
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| 277 | + * triggered. |
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| 278 | + */ |
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109 | 279 | struct common_irq_params |
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110 | 280 | pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; |
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111 | 281 | |
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| 282 | + /** |
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| 283 | + * @vblank_params: |
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| 284 | + * |
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| 285 | + * Vertical blanking IRQ parameters, passed to registered handlers when |
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| 286 | + * triggered. |
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| 287 | + */ |
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112 | 288 | struct common_irq_params |
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113 | 289 | vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; |
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114 | 290 | |
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115 | | - /* this spin lock synchronizes access to 'irq_handler_list_table' */ |
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| 291 | + /** |
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| 292 | + * @vupdate_params: |
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| 293 | + * |
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| 294 | + * Vertical update IRQ parameters, passed to registered handlers when |
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| 295 | + * triggered. |
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| 296 | + */ |
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| 297 | + struct common_irq_params |
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| 298 | + vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; |
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| 299 | + |
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116 | 300 | spinlock_t irq_handler_list_table_lock; |
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117 | 301 | |
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118 | 302 | struct backlight_device *backlight_dev; |
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119 | 303 | |
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120 | 304 | const struct dc_link *backlight_link; |
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121 | | - |
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122 | | - struct work_struct mst_hotplug_work; |
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| 305 | + struct amdgpu_dm_backlight_caps backlight_caps; |
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123 | 306 | |
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124 | 307 | struct mod_freesync *freesync_module; |
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| 308 | +#ifdef CONFIG_DRM_AMD_DC_HDCP |
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| 309 | + struct hdcp_workqueue *hdcp_workqueue; |
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| 310 | +#endif |
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| 311 | + |
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| 312 | + struct drm_atomic_state *cached_state; |
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| 313 | + struct dc_state *cached_dc_state; |
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| 314 | + |
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| 315 | + struct dm_compressor_info compressor; |
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| 316 | + |
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| 317 | + const struct firmware *fw_dmcu; |
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| 318 | + uint32_t dmcu_fw_version; |
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| 319 | + /** |
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| 320 | + * @soc_bounding_box: |
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| 321 | + * |
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| 322 | + * gpu_info FW provided soc bounding box struct or 0 if not |
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| 323 | + * available in FW |
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| 324 | + */ |
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| 325 | + const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; |
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125 | 326 | |
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126 | 327 | /** |
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127 | | - * Caches device atomic state for suspend/resume |
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| 328 | + * @mst_encoders: |
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| 329 | + * |
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| 330 | + * fake encoders used for DP MST. |
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128 | 331 | */ |
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129 | | - struct drm_atomic_state *cached_state; |
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| 332 | + struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; |
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| 333 | + bool force_timing_sync; |
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| 334 | +}; |
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130 | 335 | |
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131 | | - struct dm_comressor_info compressor; |
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| 336 | +enum dsc_clock_force_state { |
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| 337 | + DSC_CLK_FORCE_DEFAULT = 0, |
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| 338 | + DSC_CLK_FORCE_ENABLE, |
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| 339 | + DSC_CLK_FORCE_DISABLE, |
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| 340 | +}; |
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| 341 | + |
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| 342 | +struct dsc_preferred_settings { |
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| 343 | + enum dsc_clock_force_state dsc_force_enable; |
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| 344 | + uint32_t dsc_num_slices_v; |
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| 345 | + uint32_t dsc_num_slices_h; |
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| 346 | + uint32_t dsc_bits_per_pixel; |
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132 | 347 | }; |
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133 | 348 | |
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134 | 349 | struct amdgpu_dm_connector { |
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.. | .. |
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157 | 372 | struct amdgpu_dm_dp_aux dm_dp_aux; |
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158 | 373 | struct drm_dp_mst_port *port; |
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159 | 374 | struct amdgpu_dm_connector *mst_port; |
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160 | | - struct amdgpu_encoder *mst_encoder; |
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| 375 | + struct drm_dp_aux *dsc_aux; |
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161 | 376 | |
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162 | 377 | /* TODO see if we can merge with ddc_bus or make a dm_connector */ |
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163 | 378 | struct amdgpu_i2c_adapter *i2c; |
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.. | .. |
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167 | 382 | int max_vfreq ; |
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168 | 383 | int pixel_clock_mhz; |
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169 | 384 | |
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170 | | - /*freesync caps*/ |
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171 | | - struct mod_freesync_caps caps; |
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| 385 | + /* Audio instance - protected by audio_lock. */ |
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| 386 | + int audio_inst; |
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172 | 387 | |
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173 | 388 | struct mutex hpd_lock; |
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174 | 389 | |
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175 | 390 | bool fake_enable; |
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| 391 | +#ifdef CONFIG_DEBUG_FS |
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| 392 | + uint32_t debugfs_dpcd_address; |
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| 393 | + uint32_t debugfs_dpcd_size; |
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| 394 | +#endif |
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| 395 | + bool force_yuv420_output; |
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| 396 | + struct dsc_preferred_settings dsc_settings; |
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176 | 397 | }; |
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177 | 398 | |
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178 | 399 | #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) |
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.. | .. |
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187 | 408 | struct dm_plane_state { |
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188 | 409 | struct drm_plane_state base; |
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189 | 410 | struct dc_plane_state *dc_state; |
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| 411 | + uint64_t tiling_flags; |
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| 412 | + bool tmz_surface; |
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190 | 413 | }; |
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191 | 414 | |
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192 | 415 | struct dm_crtc_state { |
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193 | 416 | struct drm_crtc_state base; |
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194 | 417 | struct dc_stream_state *stream; |
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195 | 418 | |
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| 419 | + bool cm_has_degamma; |
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| 420 | + bool cm_is_degamma_srgb; |
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| 421 | + |
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| 422 | + int update_type; |
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| 423 | + int active_planes; |
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| 424 | + |
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196 | 425 | int crc_skip_count; |
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197 | | - bool crc_enabled; |
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| 426 | + enum amdgpu_dm_pipe_crc_source crc_src; |
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| 427 | + |
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| 428 | + bool freesync_timing_changed; |
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| 429 | + bool freesync_vrr_info_changed; |
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| 430 | + |
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| 431 | + bool vrr_supported; |
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| 432 | + struct mod_freesync_config freesync_config; |
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| 433 | + struct dc_info_packet vrr_infopacket; |
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| 434 | + |
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| 435 | + int abm_level; |
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198 | 436 | }; |
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199 | 437 | |
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200 | | -#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) |
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| 438 | +#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) |
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201 | 439 | |
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202 | 440 | struct dm_atomic_state { |
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203 | | - struct drm_atomic_state base; |
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| 441 | + struct drm_private_state base; |
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204 | 442 | |
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205 | 443 | struct dc_state *context; |
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206 | 444 | }; |
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.. | .. |
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213 | 451 | enum amdgpu_rmx_type scaling; |
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214 | 452 | uint8_t underscan_vborder; |
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215 | 453 | uint8_t underscan_hborder; |
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216 | | - uint8_t max_bpc; |
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217 | 454 | bool underscan_enable; |
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218 | | - struct mod_freesync_user_enable user_enable; |
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219 | 455 | bool freesync_capable; |
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| 456 | + uint8_t abm_level; |
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| 457 | + int vcpi_slots; |
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| 458 | + uint64_t pbn; |
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220 | 459 | }; |
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221 | 460 | |
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222 | 461 | #define to_dm_connector_state(x)\ |
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.. | .. |
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249 | 488 | void dm_restore_drm_connector_state(struct drm_device *dev, |
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250 | 489 | struct drm_connector *connector); |
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251 | 490 | |
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252 | | -void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector, |
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253 | | - struct edid *edid); |
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| 491 | +void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, |
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| 492 | + struct edid *edid); |
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254 | 493 | |
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255 | | -void |
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256 | | -amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector); |
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257 | | - |
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258 | | -/* amdgpu_dm_crc.c */ |
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259 | | -#ifdef CONFIG_DEBUG_FS |
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260 | | -int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name); |
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261 | | -void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc); |
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262 | | -#else |
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263 | | -#define amdgpu_dm_crtc_set_crc_source NULL |
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264 | | -#define amdgpu_dm_crtc_handle_crc_irq(x) |
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265 | | -#endif |
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| 494 | +void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); |
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266 | 495 | |
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267 | 496 | #define MAX_COLOR_LUT_ENTRIES 4096 |
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268 | 497 | /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ |
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269 | 498 | #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 |
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270 | 499 | |
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271 | 500 | void amdgpu_dm_init_color_mod(void); |
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272 | | -int amdgpu_dm_set_degamma_lut(struct drm_crtc_state *crtc_state, |
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273 | | - struct dc_plane_state *dc_plane_state); |
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274 | | -void amdgpu_dm_set_ctm(struct dm_crtc_state *crtc); |
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275 | | -int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc); |
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| 501 | +int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); |
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| 502 | +int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); |
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| 503 | +int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, |
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| 504 | + struct dc_plane_state *dc_plane_state); |
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| 505 | + |
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| 506 | +void amdgpu_dm_update_connector_after_detect( |
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| 507 | + struct amdgpu_dm_connector *aconnector); |
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276 | 508 | |
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277 | 509 | extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; |
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278 | 510 | |
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