add wifi6 8852be driver

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2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da

 kernel/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
..
..
@@ -30,6 +30,7 @@
30
30
 #include "gc/gc_9_0_offset.h"
31
31
 #include "gc/gc_9_0_sh_mask.h"
32
32
 #include "sdma0/sdma0_4_0_sh_mask.h"
33
+#include "amdgpu_amdkfd.h"
33
34
 
34
35
 static inline struct v9_mqd *get_mqd(void *mqd)
35
36
 {
..
..
@@ -45,7 +46,7 @@
45
46
 			struct queue_properties *q)
46
47
 {
47
48
 	struct v9_mqd *m;
48
-	uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */
49
+	uint32_t se_mask[KFD_MAX_NUM_SE] = {0};
49
50
 
50
51
 	if (q->cu_mask_count == 0)
51
52
 		return;
..
..
@@ -58,48 +59,84 @@
58
59
 	m->compute_static_thread_mgmt_se1 = se_mask[1];
59
60
 	m->compute_static_thread_mgmt_se2 = se_mask[2];
60
61
 	m->compute_static_thread_mgmt_se3 = se_mask[3];
62
+	m->compute_static_thread_mgmt_se4 = se_mask[4];
63
+	m->compute_static_thread_mgmt_se5 = se_mask[5];
64
+	m->compute_static_thread_mgmt_se6 = se_mask[6];
65
+	m->compute_static_thread_mgmt_se7 = se_mask[7];
61
66
 
62
-	pr_debug("update cu mask to %#x %#x %#x %#x\n",
67
+	pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n",
63
68
 		m->compute_static_thread_mgmt_se0,
64
69
 		m->compute_static_thread_mgmt_se1,
65
70
 		m->compute_static_thread_mgmt_se2,
66
-		m->compute_static_thread_mgmt_se3);
71
+		m->compute_static_thread_mgmt_se3,
72
+		m->compute_static_thread_mgmt_se4,
73
+		m->compute_static_thread_mgmt_se5,
74
+		m->compute_static_thread_mgmt_se6,
75
+		m->compute_static_thread_mgmt_se7);
67
76
 }
68
77
 
69
-static int init_mqd(struct mqd_manager *mm, void **mqd,
70
-			struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
71
-			struct queue_properties *q)
78
+static void set_priority(struct v9_mqd *m, struct queue_properties *q)
79
+{
80
+	m->cp_hqd_pipe_priority = pipe_priority_map[q->priority];
81
+	m->cp_hqd_queue_priority = q->priority;
82
+}
83
+
84
+static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd,
85
+		struct queue_properties *q)
72
86
 {
73
87
 	int retval;
74
-	uint64_t addr;
75
-	struct v9_mqd *m;
76
-	struct kfd_dev *kfd = mm->dev;
88
+	struct kfd_mem_obj *mqd_mem_obj = NULL;
77
89
 
78
-	*mqd_mem_obj = NULL;
79
-	/* From V9,  for CWSR, the control stack is located on the next page
80
-	 * boundary after the mqd, we will use the gtt allocation function
81
-	 * instead of sub-allocation function.
90
+	/* For V9 only, due to a HW bug, the control stack of a user mode
91
+	 * compute queue needs to be allocated just behind the page boundary
92
+	 * of its regular MQD buffer. So we allocate an enlarged MQD buffer:
93
+	 * the first page of the buffer serves as the regular MQD buffer
94
+	 * purpose and the remaining is for control stack. Although the two
95
+	 * parts are in the same buffer object, they need different memory
96
+	 * types: MQD part needs UC (uncached) as usual, while control stack
97
+	 * needs NC (non coherent), which is different from the UC type which
98
+	 * is used when control stack is allocated in user space.
99
+	 *
100
+	 * Because of all those, we use the gtt allocation function instead
101
+	 * of sub-allocation function for this enlarged MQD buffer. Moreover,
102
+	 * in order to achieve two memory types in a single buffer object, we
103
+	 * pass a special bo flag AMDGPU_GEM_CREATE_CP_MQD_GFX9 to instruct
104
+	 * amdgpu memory functions to do so.
82
105
 	 */
83
106
 	if (kfd->cwsr_enabled && (q->type == KFD_QUEUE_TYPE_COMPUTE)) {
84
-		*mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
85
-		if (!*mqd_mem_obj)
86
-			return -ENOMEM;
87
-		retval = kfd->kfd2kgd->init_gtt_mem_allocation(kfd->kgd,
107
+		mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
108
+		if (!mqd_mem_obj)
109
+			return NULL;
110
+		retval = amdgpu_amdkfd_alloc_gtt_mem(kfd->kgd,
88
111
 			ALIGN(q->ctl_stack_size, PAGE_SIZE) +
89
112
 				ALIGN(sizeof(struct v9_mqd), PAGE_SIZE),
90
-			&((*mqd_mem_obj)->gtt_mem),
91
-			&((*mqd_mem_obj)->gpu_addr),
92
-			(void *)&((*mqd_mem_obj)->cpu_ptr), true);
93
-	} else
94
-		retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct v9_mqd),
95
-				mqd_mem_obj);
96
-	if (retval) {
97
-		kfree(*mqd_mem_obj);
98
-		return -ENOMEM;
113
+			&(mqd_mem_obj->gtt_mem),
114
+			&(mqd_mem_obj->gpu_addr),
115
+			(void *)&(mqd_mem_obj->cpu_ptr), true);
116
+
117
+		if (retval) {
118
+			kfree(mqd_mem_obj);
119
+			return NULL;
120
+		}
121
+	} else {
122
+		retval = kfd_gtt_sa_allocate(kfd, sizeof(struct v9_mqd),
123
+				&mqd_mem_obj);
124
+		if (retval)
125
+			return NULL;
99
126
 	}
100
127
 
101
-	m = (struct v9_mqd *) (*mqd_mem_obj)->cpu_ptr;
102
-	addr = (*mqd_mem_obj)->gpu_addr;
128
+	return mqd_mem_obj;
129
+}
130
+
131
+static void init_mqd(struct mqd_manager *mm, void **mqd,
132
+			struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
133
+			struct queue_properties *q)
134
+{
135
+	uint64_t addr;
136
+	struct v9_mqd *m;
137
+
138
+	m = (struct v9_mqd *) mqd_mem_obj->cpu_ptr;
139
+	addr = mqd_mem_obj->gpu_addr;
103
140
 
104
141
 	memset(m, 0, sizeof(struct v9_mqd));
105
142
 
..
..
@@ -109,6 +146,10 @@
109
146
 	m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF;
110
147
 	m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF;
111
148
 	m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF;
149
+	m->compute_static_thread_mgmt_se4 = 0xFFFFFFFF;
150
+	m->compute_static_thread_mgmt_se5 = 0xFFFFFFFF;
151
+	m->compute_static_thread_mgmt_se6 = 0xFFFFFFFF;
152
+	m->compute_static_thread_mgmt_se7 = 0xFFFFFFFF;
112
153
 
113
154
 	m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |
114
155
 			0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;
..
..
@@ -120,10 +161,7 @@
120
161
 
121
162
 	m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT |
122
163
 			1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT |
123
-			10 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT;
124
-
125
-	m->cp_hqd_pipe_priority = 1;
126
-	m->cp_hqd_queue_priority = 15;
164
+			1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT;
127
165
 
128
166
 	if (q->format == KFD_QUEUE_FORMAT_AQL) {
129
167
 		m->cp_hqd_aql_control =
..
..
@@ -151,9 +189,7 @@
151
189
 	*mqd = m;
152
190
 	if (gart_addr)
153
191
 		*gart_addr = addr;
154
-	retval = mm->update_mqd(mm, m, q);
155
-
156
-	return retval;
192
+	mm->update_mqd(mm, m, q);
157
193
 }
158
194
 
159
195
 static int load_mqd(struct mqd_manager *mm, void *mqd,
..
..
@@ -168,7 +204,15 @@
168
204
 					  wptr_shift, 0, mms);
169
205
 }
170
206
 
171
-static int update_mqd(struct mqd_manager *mm, void *mqd,
207
+static int hiq_load_mqd_kiq(struct mqd_manager *mm, void *mqd,
208
+			    uint32_t pipe_id, uint32_t queue_id,
209
+			    struct queue_properties *p, struct mm_struct *mms)
210
+{
211
+	return mm->dev->kfd2kgd->hiq_mqd_load(mm->dev->kgd, mqd, pipe_id,
212
+					      queue_id, p->doorbell_off);
213
+}
214
+
215
+static void update_mqd(struct mqd_manager *mm, void *mqd,
172
216
 		      struct queue_properties *q)
173
217
 {
174
218
 	struct v9_mqd *m;
..
..
@@ -227,13 +271,9 @@
227
271
 		m->cp_hqd_ctx_save_control = 0;
228
272
 
229
273
 	update_cu_mask(mm, mqd, q);
274
+	set_priority(m, q);
230
275
 
231
-	q->is_active = (q->queue_size > 0 &&
232
-			q->queue_address != 0 &&
233
-			q->queue_percent > 0 &&
234
-			!q->is_evicted);
235
-
236
-	return 0;
276
+	q->is_active = QUEUE_IS_ACTIVE(*q);
237
277
 }
238
278
 
239
279
 
..
..
@@ -247,13 +287,13 @@
247
287
 		pipe_id, queue_id);
248
288
 }
249
289
 
250
-static void uninit_mqd(struct mqd_manager *mm, void *mqd,
290
+static void free_mqd(struct mqd_manager *mm, void *mqd,
251
291
 			struct kfd_mem_obj *mqd_mem_obj)
252
292
 {
253
293
 	struct kfd_dev *kfd = mm->dev;
254
294
 
255
295
 	if (mqd_mem_obj->gtt_mem) {
256
-		kfd->kfd2kgd->free_gtt_mem(kfd->kgd, mqd_mem_obj->gtt_mem);
296
+		amdgpu_amdkfd_free_gtt_mem(kfd->kgd, mqd_mem_obj->gtt_mem);
257
297
 		kfree(mqd_mem_obj);
258
298
 	} else {
259
299
 		kfd_gtt_sa_free(mm->dev, mqd_mem_obj);
..
..
@@ -269,71 +309,58 @@
269
309
 		pipe_id, queue_id);
270
310
 }
271
311
 
272
-static int init_mqd_hiq(struct mqd_manager *mm, void **mqd,
273
-			struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
312
+static int get_wave_state(struct mqd_manager *mm, void *mqd,
313
+			  void __user *ctl_stack,
314
+			  u32 *ctl_stack_used_size,
315
+			  u32 *save_area_used_size)
316
+{
317
+	struct v9_mqd *m;
318
+
319
+	/* Control stack is located one page after MQD. */
320
+	void *mqd_ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE);
321
+
322
+	m = get_mqd(mqd);
323
+
324
+	*ctl_stack_used_size = m->cp_hqd_cntl_stack_size -
325
+		m->cp_hqd_cntl_stack_offset;
326
+	*save_area_used_size = m->cp_hqd_wg_state_offset -
327
+		m->cp_hqd_cntl_stack_size;
328
+
329
+	if (copy_to_user(ctl_stack, mqd_ctl_stack, m->cp_hqd_cntl_stack_size))
330
+		return -EFAULT;
331
+
332
+	return 0;
333
+}
334
+
335
+static void init_mqd_hiq(struct mqd_manager *mm, void **mqd,
336
+			struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
274
337
 			struct queue_properties *q)
275
338
 {
276
339
 	struct v9_mqd *m;
277
-	int retval = init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q);
278
340
 
279
-	if (retval != 0)
280
-		return retval;
341
+	init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q);
281
342
 
282
343
 	m = get_mqd(*mqd);
283
344
 
284
345
 	m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT |
285
346
 			1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT;
286
-
287
-	return retval;
288
347
 }
289
348
 
290
-static int update_mqd_hiq(struct mqd_manager *mm, void *mqd,
291
-			struct queue_properties *q)
292
-{
293
-	struct v9_mqd *m;
294
-	int retval = update_mqd(mm, mqd, q);
295
-
296
-	if (retval != 0)
297
-		return retval;
298
-
299
-	/* TODO: what's the point? update_mqd already does this. */
300
-	m = get_mqd(mqd);
301
-	m->cp_hqd_vmid = q->vmid;
302
-	return retval;
303
-}
304
-
305
-static int init_mqd_sdma(struct mqd_manager *mm, void **mqd,
306
-		struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
349
+static void init_mqd_sdma(struct mqd_manager *mm, void **mqd,
350
+		struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
307
351
 		struct queue_properties *q)
308
352
 {
309
-	int retval;
310
353
 	struct v9_sdma_mqd *m;
311
354
 
312
-
313
-	retval = kfd_gtt_sa_allocate(mm->dev,
314
-			sizeof(struct v9_sdma_mqd),
315
-			mqd_mem_obj);
316
-
317
-	if (retval != 0)
318
-		return -ENOMEM;
319
-
320
-	m = (struct v9_sdma_mqd *) (*mqd_mem_obj)->cpu_ptr;
355
+	m = (struct v9_sdma_mqd *) mqd_mem_obj->cpu_ptr;
321
356
 
322
357
 	memset(m, 0, sizeof(struct v9_sdma_mqd));
323
358
 
324
359
 	*mqd = m;
325
360
 	if (gart_addr)
326
-		*gart_addr = (*mqd_mem_obj)->gpu_addr;
361
+		*gart_addr = mqd_mem_obj->gpu_addr;
327
362
 
328
-	retval = mm->update_mqd(mm, m, q);
329
-
330
-	return retval;
331
-}
332
-
333
-static void uninit_mqd_sdma(struct mqd_manager *mm, void *mqd,
334
-		struct kfd_mem_obj *mqd_mem_obj)
335
-{
336
-	kfd_gtt_sa_free(mm->dev, mqd_mem_obj);
363
+	mm->update_mqd(mm, m, q);
337
364
 }
338
365
 
339
366
 static int load_mqd_sdma(struct mqd_manager *mm, void *mqd,
..
..
@@ -347,7 +374,7 @@
347
374
 
348
375
 #define SDMA_RLC_DUMMY_DEFAULT 0xf
349
376
 
350
-static int update_mqd_sdma(struct mqd_manager *mm, void *mqd,
377
+static void update_mqd_sdma(struct mqd_manager *mm, void *mqd,
351
378
 		struct queue_properties *q)
352
379
 {
353
380
 	struct v9_sdma_mqd *m;
..
..
@@ -370,12 +397,7 @@
370
397
 	m->sdma_queue_id = q->sdma_queue_id;
371
398
 	m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT;
372
399
 
373
-	q->is_active = (q->queue_size > 0 &&
374
-			q->queue_address != 0 &&
375
-			q->queue_percent > 0 &&
376
-			!q->is_evicted);
377
-
378
-	return 0;
400
+	q->is_active = QUEUE_IS_ACTIVE(*q);
379
401
 }
380
402
 
381
403
 /*
..
..
@@ -431,35 +453,54 @@
431
453
 
432
454
 	switch (type) {
433
455
 	case KFD_MQD_TYPE_CP:
434
-	case KFD_MQD_TYPE_COMPUTE:
456
+		mqd->allocate_mqd = allocate_mqd;
435
457
 		mqd->init_mqd = init_mqd;
436
-		mqd->uninit_mqd = uninit_mqd;
458
+		mqd->free_mqd = free_mqd;
437
459
 		mqd->load_mqd = load_mqd;
438
460
 		mqd->update_mqd = update_mqd;
439
461
 		mqd->destroy_mqd = destroy_mqd;
440
462
 		mqd->is_occupied = is_occupied;
463
+		mqd->get_wave_state = get_wave_state;
464
+		mqd->mqd_size = sizeof(struct v9_mqd);
441
465
 #if defined(CONFIG_DEBUG_FS)
442
466
 		mqd->debugfs_show_mqd = debugfs_show_mqd;
443
467
 #endif
444
468
 		break;
445
469
 	case KFD_MQD_TYPE_HIQ:
470
+		mqd->allocate_mqd = allocate_hiq_mqd;
446
471
 		mqd->init_mqd = init_mqd_hiq;
447
-		mqd->uninit_mqd = uninit_mqd;
448
-		mqd->load_mqd = load_mqd;
449
-		mqd->update_mqd = update_mqd_hiq;
472
+		mqd->free_mqd = free_mqd_hiq_sdma;
473
+		mqd->load_mqd = hiq_load_mqd_kiq;
474
+		mqd->update_mqd = update_mqd;
450
475
 		mqd->destroy_mqd = destroy_mqd;
451
476
 		mqd->is_occupied = is_occupied;
477
+		mqd->mqd_size = sizeof(struct v9_mqd);
478
+#if defined(CONFIG_DEBUG_FS)
479
+		mqd->debugfs_show_mqd = debugfs_show_mqd;
480
+#endif
481
+		break;
482
+	case KFD_MQD_TYPE_DIQ:
483
+		mqd->allocate_mqd = allocate_mqd;
484
+		mqd->init_mqd = init_mqd_hiq;
485
+		mqd->free_mqd = free_mqd;
486
+		mqd->load_mqd = load_mqd;
487
+		mqd->update_mqd = update_mqd;
488
+		mqd->destroy_mqd = destroy_mqd;
489
+		mqd->is_occupied = is_occupied;
490
+		mqd->mqd_size = sizeof(struct v9_mqd);
452
491
 #if defined(CONFIG_DEBUG_FS)
453
492
 		mqd->debugfs_show_mqd = debugfs_show_mqd;
454
493
 #endif
455
494
 		break;
456
495
 	case KFD_MQD_TYPE_SDMA:
496
+		mqd->allocate_mqd = allocate_sdma_mqd;
457
497
 		mqd->init_mqd = init_mqd_sdma;
458
-		mqd->uninit_mqd = uninit_mqd_sdma;
498
+		mqd->free_mqd = free_mqd_hiq_sdma;
459
499
 		mqd->load_mqd = load_mqd_sdma;
460
500
 		mqd->update_mqd = update_mqd_sdma;
461
501
 		mqd->destroy_mqd = destroy_mqd_sdma;
462
502
 		mqd->is_occupied = is_occupied_sdma;
503
+		mqd->mqd_size = sizeof(struct v9_sdma_mqd);
463
504
 #if defined(CONFIG_DEBUG_FS)
464
505
 		mqd->debugfs_show_mqd = debugfs_show_mqd_sdma;
465
506
 #endif