.. | .. |
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24 | 24 | #include "soc15.h" |
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25 | 25 | |
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26 | 26 | #include "soc15_common.h" |
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27 | | -#include "soc15_hw_ip.h" |
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28 | 27 | #include "vega10_ip_offset.h" |
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29 | 28 | |
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30 | 29 | int vega10_reg_base_init(struct amdgpu_device *adev) |
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.. | .. |
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56 | 55 | return 0; |
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57 | 56 | } |
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58 | 57 | |
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| 58 | +void vega10_doorbell_index_init(struct amdgpu_device *adev) |
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| 59 | +{ |
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| 60 | + adev->doorbell_index.kiq = AMDGPU_DOORBELL64_KIQ; |
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| 61 | + adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL64_MEC_RING0; |
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| 62 | + adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL64_MEC_RING1; |
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| 63 | + adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL64_MEC_RING2; |
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| 64 | + adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL64_MEC_RING3; |
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| 65 | + adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL64_MEC_RING4; |
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| 66 | + adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL64_MEC_RING5; |
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| 67 | + adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL64_MEC_RING6; |
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| 68 | + adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL64_MEC_RING7; |
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| 69 | + adev->doorbell_index.userqueue_start = AMDGPU_DOORBELL64_USERQUEUE_START; |
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| 70 | + adev->doorbell_index.userqueue_end = AMDGPU_DOORBELL64_USERQUEUE_END; |
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| 71 | + adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL64_GFX_RING0; |
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| 72 | + adev->doorbell_index.sdma_engine[0] = AMDGPU_DOORBELL64_sDMA_ENGINE0; |
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| 73 | + adev->doorbell_index.sdma_engine[1] = AMDGPU_DOORBELL64_sDMA_ENGINE1; |
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| 74 | + adev->doorbell_index.ih = AMDGPU_DOORBELL64_IH; |
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| 75 | + adev->doorbell_index.uvd_vce.uvd_ring0_1 = AMDGPU_DOORBELL64_UVD_RING0_1; |
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| 76 | + adev->doorbell_index.uvd_vce.uvd_ring2_3 = AMDGPU_DOORBELL64_UVD_RING2_3; |
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| 77 | + adev->doorbell_index.uvd_vce.uvd_ring4_5 = AMDGPU_DOORBELL64_UVD_RING4_5; |
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| 78 | + adev->doorbell_index.uvd_vce.uvd_ring6_7 = AMDGPU_DOORBELL64_UVD_RING6_7; |
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| 79 | + adev->doorbell_index.uvd_vce.vce_ring0_1 = AMDGPU_DOORBELL64_VCE_RING0_1; |
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| 80 | + adev->doorbell_index.uvd_vce.vce_ring2_3 = AMDGPU_DOORBELL64_VCE_RING2_3; |
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| 81 | + adev->doorbell_index.uvd_vce.vce_ring4_5 = AMDGPU_DOORBELL64_VCE_RING4_5; |
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| 82 | + adev->doorbell_index.uvd_vce.vce_ring6_7 = AMDGPU_DOORBELL64_VCE_RING6_7; |
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| 83 | + adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_DOORBELL64_VCN0_1; |
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| 84 | + adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_DOORBELL64_VCN2_3; |
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| 85 | + adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_DOORBELL64_VCN4_5; |
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| 86 | + adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_DOORBELL64_VCN6_7; |
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| 87 | + |
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| 88 | + adev->doorbell_index.first_non_cp = AMDGPU_DOORBELL64_FIRST_NON_CP; |
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| 89 | + adev->doorbell_index.last_non_cp = AMDGPU_DOORBELL64_LAST_NON_CP; |
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| 90 | + |
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| 91 | + /* In unit of dword doorbell */ |
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| 92 | + adev->doorbell_index.max_assignment = AMDGPU_DOORBELL64_MAX_ASSIGNMENT << 1; |
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| 93 | + adev->doorbell_index.sdma_doorbell_range = 4; |
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| 94 | +} |
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59 | 95 | |
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