add wifi6 8852be driver

hc

2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da

 kernel/drivers/gpu/drm/amd/amdgpu/soc15_common.h
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@@ -35,6 +35,9 @@
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 #define RREG32_SOC15(ip, inst, reg) \
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 	RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
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+#define RREG32_SOC15_NO_KIQ(ip, inst, reg) \
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+	RREG32_NO_KIQ(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
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+
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 #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \
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 	RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset)
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..
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@@ -47,22 +50,86 @@
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 #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
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 	WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value)
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-#define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask, ret) \
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+#define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \
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+({	int ret = 0;						\
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 	do {							\
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+		uint32_t old_ = 0;				\
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 		uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
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 		uint32_t loop = adev->usec_timeout;		\
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 		ret = 0;					\
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 		while ((tmp_ & (mask)) != (expected_value)) {	\
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-			udelay(2);				\
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+			if (old_ != tmp_) {			\
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+				loop = adev->usec_timeout;	\
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+				old_ = tmp_;			\
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+			} else					\
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+				udelay(1);			\
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 			tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
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 			loop--;					\
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 			if (!loop) {				\
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+				DRM_WARN("Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n", \
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+					  inst, #reg, (unsigned)expected_value, (unsigned)(tmp_ & (mask))); \
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 				ret = -ETIMEDOUT;		\
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 				break;				\
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 			}					\
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 		}						\
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+	} while (0);						\
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+	ret;							\
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+})
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+
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+#define WREG32_RLC(reg, value) \
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+	do {							\
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+		if (amdgpu_sriov_fullaccess(adev)) {    \
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+			uint32_t i = 0;	\
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+			uint32_t retries = 50000;	\
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+			uint32_t r0 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0;	\
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+			uint32_t r1 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1;	\
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+			uint32_t spare_int = adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT;	\
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+			WREG32(r0, value);	\
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+			WREG32(r1, (reg | 0x80000000));	\
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+			WREG32(spare_int, 0x1);	\
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+			for (i = 0; i < retries; i++) {	\
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+				u32 tmp = RREG32(r1);	\
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+				if (!(tmp & 0x80000000))	\
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+					break;	\
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+				udelay(10);	\
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+			}	\
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+			if (i >= retries)	\
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+				pr_err("timeout: rlcg program reg:0x%05x failed !\n", reg);	\
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+		} else {	\
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+			WREG32(reg, value); \
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+		}	\
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 	} while (0)
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+#define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \
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+	do {							\
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+		uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\
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+		if (amdgpu_sriov_fullaccess(adev)) {    \
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+			uint32_t r2 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2;	\
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+			uint32_t r3 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3;	\
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+			uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;   \
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+			uint32_t grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;   \
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+			if (target_reg == grbm_cntl) \
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+				WREG32(r2, value);	\
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+			else if (target_reg == grbm_idx) \
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+				WREG32(r3, value);	\
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+			WREG32(target_reg, value);	\
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+		} else {	\
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+			WREG32(target_reg, value); \
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+		}	\
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+	} while (0)
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+
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+#define WREG32_SOC15_RLC(ip, inst, reg, value) \
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+	do {							\
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+			uint32_t target_reg = adev->reg_offset[GC_HWIP][0][reg##_BASE_IDX] + reg;\
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+			WREG32_RLC(target_reg, value); \
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+	} while (0)
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+
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+#define WREG32_FIELD15_RLC(ip, idx, reg, field, val)   \
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+    WREG32_RLC((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \
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+    (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \
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+    & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
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+
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+#define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \
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+    WREG32_RLC(((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset), value)
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+
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 #endif
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-
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-