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2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da 
 kernel/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
....@@ -31,6 +31,9 @@
3131 #define GFX_CMD_RESERVED_MASK       0x7FF00000
3232 #define GFX_CMD_RESPONSE_MASK       0x80000000
3333 
34
+/* USBC PD FW version retrieval command */
35
+#define C2PMSG_CMD_GFX_USB_PD_FW_VER 0x2000000
36
+
3437 /* TEE Gfx Command IDs for the register interface.
3538 *  Command ID must be between 0x00010000 and 0x000F0000.
3639 */
....@@ -43,6 +46,9 @@
4346     GFX_CTRL_CMD_ID_ENABLE_INT      = 0x00050000,   /* enable PSP-to-Gfx interrupt */
4447     GFX_CTRL_CMD_ID_DISABLE_INT     = 0x00060000,   /* disable PSP-to-Gfx interrupt */
4548     GFX_CTRL_CMD_ID_MODE1_RST       = 0x00070000,   /* trigger the Mode 1 reset */
49
+    GFX_CTRL_CMD_ID_GBR_IH_SET      = 0x00080000,   /* set Gbr IH_RB_CNTL registers */
50
+    GFX_CTRL_CMD_ID_CONSUME_CMD     = 0x00090000,   /* send interrupt to psp for updating write pointer of vf */
51
+    GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING = 0x000C0000, /* destroy GPCOM ring */
4652 
4753     GFX_CTRL_CMD_ID_MAX             = 0x000F0000,   /* max command ID */
4854 };
....@@ -77,7 +83,6 @@
7783 */
7884 #define GFX_FLAG_RESPONSE               0x80000000
7985 
80
-
8186 /* TEE Gfx Command IDs for the ring buffer interface. */
8287 enum psp_gfx_cmd_id
8388 {
....@@ -89,9 +94,14 @@
8994     GFX_CMD_ID_LOAD_IP_FW   = 0x00000006,   /* load HW IP FW */
9095     GFX_CMD_ID_DESTROY_TMR  = 0x00000007,   /* destroy TMR region */
9196     GFX_CMD_ID_SAVE_RESTORE = 0x00000008,   /* save/restore HW IP FW */
92
-
97
+    GFX_CMD_ID_SETUP_VMR    = 0x00000009,   /* setup VMR region */
98
+    GFX_CMD_ID_DESTROY_VMR  = 0x0000000A,   /* destroy VMR region */
99
+    GFX_CMD_ID_PROG_REG     = 0x0000000B,   /* program regs */
100
+    GFX_CMD_ID_CLEAR_VF_FW  = 0x0000000D,   /* Clear VF FW, to be used on VF shutdown. */
101
+    /* IDs upto 0x1F are reserved for older programs (Raven, Vega 10/12/20) */
102
+    GFX_CMD_ID_LOAD_TOC     = 0x00000020,   /* Load TOC and obtain TMR size */
103
+    GFX_CMD_ID_AUTOLOAD_RLC = 0x00000021,   /* Indicates all graphics fw loaded, start RLC autoload */
93104 };
94
-
95105 
96106 /* Command to load Trusted Application binary into PSP OS. */
97107 struct psp_gfx_cmd_load_ta
....@@ -164,32 +174,67 @@
164174 
165175 
166176 /* FW types for GFX_CMD_ID_LOAD_IP_FW command. Limit 31. */
167
-enum psp_gfx_fw_type
168
-{
169
-    GFX_FW_TYPE_NONE        = 0,
170
-    GFX_FW_TYPE_CP_ME       = 1,
171
-    GFX_FW_TYPE_CP_PFP      = 2,
172
-    GFX_FW_TYPE_CP_CE       = 3,
173
-    GFX_FW_TYPE_CP_MEC      = 4,
174
-    GFX_FW_TYPE_CP_MEC_ME1  = 5,
175
-    GFX_FW_TYPE_CP_MEC_ME2  = 6,
176
-    GFX_FW_TYPE_RLC_V       = 7,
177
-    GFX_FW_TYPE_RLC_G       = 8,
178
-    GFX_FW_TYPE_SDMA0       = 9,
179
-    GFX_FW_TYPE_SDMA1       = 10,
180
-    GFX_FW_TYPE_DMCU_ERAM   = 11,
181
-    GFX_FW_TYPE_DMCU_ISR    = 12,
182
-    GFX_FW_TYPE_VCN         = 13,
183
-    GFX_FW_TYPE_UVD         = 14,
184
-    GFX_FW_TYPE_VCE         = 15,
185
-    GFX_FW_TYPE_ISP         = 16,
186
-    GFX_FW_TYPE_ACP         = 17,
187
-    GFX_FW_TYPE_SMU         = 18,
188
-    GFX_FW_TYPE_MMSCH       = 19,
189
-    GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM        = 20,
190
-    GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM        = 21,
191
-    GFX_FW_TYPE_RLC_RESTORE_LIST_CNTL           = 22,
192
-    GFX_FW_TYPE_MAX         = 23
177
+enum psp_gfx_fw_type {
178
+	GFX_FW_TYPE_NONE        = 0,    /* */
179
+	GFX_FW_TYPE_CP_ME       = 1,    /* CP-ME                    VG + RV */
180
+	GFX_FW_TYPE_CP_PFP      = 2,    /* CP-PFP                   VG + RV */
181
+	GFX_FW_TYPE_CP_CE       = 3,    /* CP-CE                    VG + RV */
182
+	GFX_FW_TYPE_CP_MEC      = 4,    /* CP-MEC FW                VG + RV */
183
+	GFX_FW_TYPE_CP_MEC_ME1  = 5,    /* CP-MEC Jump Table 1      VG + RV */
184
+	GFX_FW_TYPE_CP_MEC_ME2  = 6,    /* CP-MEC Jump Table 2      VG      */
185
+	GFX_FW_TYPE_RLC_V       = 7,    /* RLC-V                    VG      */
186
+	GFX_FW_TYPE_RLC_G       = 8,    /* RLC-G                    VG + RV */
187
+	GFX_FW_TYPE_SDMA0       = 9,    /* SDMA0                    VG + RV */
188
+	GFX_FW_TYPE_SDMA1       = 10,   /* SDMA1                    VG      */
189
+	GFX_FW_TYPE_DMCU_ERAM   = 11,   /* DMCU-ERAM                VG + RV */
190
+	GFX_FW_TYPE_DMCU_ISR    = 12,   /* DMCU-ISR                 VG + RV */
191
+	GFX_FW_TYPE_VCN         = 13,   /* VCN                           RV */
192
+	GFX_FW_TYPE_UVD         = 14,   /* UVD                      VG      */
193
+	GFX_FW_TYPE_VCE         = 15,   /* VCE                      VG      */
194
+	GFX_FW_TYPE_ISP         = 16,   /* ISP                           RV */
195
+	GFX_FW_TYPE_ACP         = 17,   /* ACP                           RV */
196
+	GFX_FW_TYPE_SMU         = 18,   /* SMU                      VG      */
197
+	GFX_FW_TYPE_MMSCH       = 19,   /* MMSCH                    VG      */
198
+	GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM        = 20,   /* RLC GPM                  VG + RV */
199
+	GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM        = 21,   /* RLC SRM                  VG + RV */
200
+	GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL       = 22,   /* RLC CNTL                 VG + RV */
201
+	GFX_FW_TYPE_UVD1        = 23,   /* UVD1                     VG-20   */
202
+	GFX_FW_TYPE_TOC         = 24,   /* TOC                      NV-10   */
203
+	GFX_FW_TYPE_RLC_P                           = 25,   /* RLC P                    NV      */
204
+	GFX_FW_TYPE_RLC_IRAM                        = 26,   /* RLC_IRAM                 NV      */
205
+	GFX_FW_TYPE_GLOBAL_TAP_DELAYS               = 27,   /* GLOBAL TAP DELAYS        NV      */
206
+	GFX_FW_TYPE_SE0_TAP_DELAYS                  = 28,   /* SE0 TAP DELAYS           NV      */
207
+	GFX_FW_TYPE_SE1_TAP_DELAYS                  = 29,   /* SE1 TAP DELAYS           NV      */
208
+	GFX_FW_TYPE_GLOBAL_SE0_SE1_SKEW_DELAYS      = 30,   /* GLOBAL SE0/1 SKEW DELAYS NV      */
209
+	GFX_FW_TYPE_SDMA0_JT                        = 31,   /* SDMA0 JT                 NV      */
210
+	GFX_FW_TYPE_SDMA1_JT                        = 32,   /* SDNA1 JT                 NV      */
211
+	GFX_FW_TYPE_CP_MES                          = 33,   /* CP MES                   NV      */
212
+	GFX_FW_TYPE_MES_STACK                       = 34,   /* MES STACK                NV      */
213
+	GFX_FW_TYPE_RLC_SRM_DRAM_SR                 = 35,   /* RLC SRM DRAM             NV      */
214
+	GFX_FW_TYPE_RLCG_SCRATCH_SR                 = 36,   /* RLCG SCRATCH             NV      */
215
+	GFX_FW_TYPE_RLCP_SCRATCH_SR                 = 37,   /* RLCP SCRATCH             NV      */
216
+	GFX_FW_TYPE_RLCV_SCRATCH_SR                 = 38,   /* RLCV SCRATCH             NV      */
217
+	GFX_FW_TYPE_RLX6_DRAM_SR                    = 39,   /* RLX6 DRAM                NV      */
218
+	GFX_FW_TYPE_SDMA0_PG_CONTEXT                = 40,   /* SDMA0 PG CONTEXT         NV      */
219
+	GFX_FW_TYPE_SDMA1_PG_CONTEXT                = 41,   /* SDMA1 PG CONTEXT         NV      */
220
+	GFX_FW_TYPE_GLOBAL_MUX_SELECT_RAM           = 42,   /* GLOBAL MUX SEL RAM       NV      */
221
+	GFX_FW_TYPE_SE0_MUX_SELECT_RAM              = 43,   /* SE0 MUX SEL RAM          NV      */
222
+	GFX_FW_TYPE_SE1_MUX_SELECT_RAM              = 44,   /* SE1 MUX SEL RAM          NV      */
223
+	GFX_FW_TYPE_ACCUM_CTRL_RAM                  = 45,   /* ACCUM CTRL RAM           NV      */
224
+	GFX_FW_TYPE_RLCP_CAM                        = 46,   /* RLCP CAM                 NV      */
225
+	GFX_FW_TYPE_RLC_SPP_CAM_EXT                 = 47,   /* RLC SPP CAM EXT          NV      */
226
+	GFX_FW_TYPE_RLC_DRAM_BOOT                   = 48,   /* RLC DRAM BOOT            NV      */
227
+	GFX_FW_TYPE_VCN0_RAM                        = 49,   /* VCN_RAM                  NV + RN */
228
+	GFX_FW_TYPE_VCN1_RAM                        = 50,   /* VCN_RAM                  NV + RN */
229
+	GFX_FW_TYPE_DMUB                            = 51,   /* DMUB                          RN */
230
+	GFX_FW_TYPE_SDMA2                           = 52,   /* SDMA2                    MI      */
231
+	GFX_FW_TYPE_SDMA3                           = 53,   /* SDMA3                    MI      */
232
+	GFX_FW_TYPE_SDMA4                           = 54,   /* SDMA4                    MI      */
233
+	GFX_FW_TYPE_SDMA5                           = 55,   /* SDMA5                    MI      */
234
+	GFX_FW_TYPE_SDMA6                           = 56,   /* SDMA6                    MI      */
235
+	GFX_FW_TYPE_SDMA7                           = 57,   /* SDMA7                    MI      */
236
+	GFX_FW_TYPE_VCN1                            = 58,   /* VCN1                     MI      */
237
+	GFX_FW_TYPE_MAX
193238 };
194239 
195240 /* Command to load HW IP FW. */
....@@ -212,6 +257,20 @@
212257     enum psp_gfx_fw_type    fw_type;              /* FW type */
213258 };
214259 
260
+/* Command to setup register program */
261
+struct psp_gfx_cmd_reg_prog {
262
+	uint32_t	reg_value;
263
+	uint32_t	reg_id;
264
+};
265
+
266
+/* Command to load TOC */
267
+struct psp_gfx_cmd_load_toc
268
+{
269
+    uint32_t        toc_phy_addr_lo;        /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */
270
+    uint32_t        toc_phy_addr_hi;        /* bits [63:32] of GPU Virtual address of FW location */
271
+    uint32_t        toc_size;               /* FW buffer size in bytes */
272
+};
273
+
215274 /* All GFX ring buffer commands. */
216275 union psp_gfx_commands
217276 {
....@@ -221,8 +280,10 @@
221280     struct psp_gfx_cmd_setup_tmr        cmd_setup_tmr;
222281     struct psp_gfx_cmd_load_ip_fw       cmd_load_ip_fw;
223282     struct psp_gfx_cmd_save_restore_ip_fw cmd_save_restore_ip_fw;
283
+    struct psp_gfx_cmd_reg_prog       cmd_setup_reg_prog;
284
+    struct psp_gfx_cmd_setup_tmr        cmd_setup_vmr;
285
+    struct psp_gfx_cmd_load_toc         cmd_load_toc;
224286 };
225
-
226287 
227288 /* Structure of GFX Response buffer.
228289 * For GPCOM I/F it is part of GFX_CMD_RESP buffer, for RBI
....@@ -230,12 +291,13 @@
230291 */
231292 struct psp_gfx_resp
232293 {
233
-    uint32_t    status;             /* +0  status of command execution */
234
-    uint32_t    session_id;         /* +4  session ID in response to LoadTa command */
235
-    uint32_t    fw_addr_lo;         /* +8  bits [31:0] of FW address within TMR (in response to cmd_load_ip_fw command) */
236
-    uint32_t    fw_addr_hi;         /* +12 bits [63:32] of FW address within TMR (in response to cmd_load_ip_fw command) */
294
+    uint32_t	status;		/* +0  status of command execution */
295
+    uint32_t	session_id;	/* +4  session ID in response to LoadTa command */
296
+    uint32_t	fw_addr_lo;	/* +8  bits [31:0] of FW address within TMR (in response to cmd_load_ip_fw command) */
297
+    uint32_t	fw_addr_hi;	/* +12 bits [63:32] of FW address within TMR (in response to cmd_load_ip_fw command) */
298
+    uint32_t	tmr_size;	/* +16 size of the TMR to be reserved including MM fw and Gfx fw in response to cmd_load_toc command */
237299 
238
-    uint32_t    reserved[4];
300
+    uint32_t	reserved[3];
239301 
240302     /* total 32 bytes */
241303 };
....@@ -291,4 +353,11 @@
291353                 /* total 64 bytes */
292354 };
293355 
356
+#define PSP_ERR_UNKNOWN_COMMAND 0x00000100
357
+
358
+enum tee_error_code {
359
+    TEE_SUCCESS                         = 0x00000000,
360
+    TEE_ERROR_NOT_SUPPORTED             = 0xFFFF000A,
361
+};
362
+
294363 #endif /* _PSP_TEE_GFX_IF_H_ */