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1 | | -/* |
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2 | | - * Copyright (C) 2017 Socionext Inc. |
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3 | | - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
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4 | | - * |
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5 | | - * This program is free software; you can redistribute it and/or modify |
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6 | | - * it under the terms of the GNU General Public License version 2 as |
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7 | | - * published by the Free Software Foundation. |
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8 | | - * |
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9 | | - * This program is distributed in the hope that it will be useful, |
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10 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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11 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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12 | | - * GNU General Public License for more details. |
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13 | | - */ |
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| 1 | +// SPDX-License-Identifier: GPL-2.0 |
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| 2 | +// |
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| 3 | +// Copyright (C) 2017 Socionext Inc. |
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| 4 | +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
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14 | 5 | |
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15 | | -#include <linux/bitops.h> |
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| 6 | +#include <linux/bits.h> |
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16 | 7 | #include <linux/gpio/driver.h> |
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17 | 8 | #include <linux/irq.h> |
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18 | 9 | #include <linux/irqdomain.h> |
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.. | .. |
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23 | 14 | #include <linux/platform_device.h> |
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24 | 15 | #include <linux/spinlock.h> |
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25 | 16 | #include <dt-bindings/gpio/uniphier-gpio.h> |
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26 | | - |
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27 | | -#define UNIPHIER_GPIO_BANK_MASK \ |
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28 | | - GENMASK((UNIPHIER_GPIO_LINES_PER_BANK) - 1, 0) |
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29 | 17 | |
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30 | 18 | #define UNIPHIER_GPIO_IRQ_MAX_NUM 24 |
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31 | 19 | |
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.. | .. |
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42 | 30 | struct irq_domain *domain; |
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43 | 31 | void __iomem *regs; |
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44 | 32 | spinlock_t lock; |
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45 | | - u32 saved_vals[0]; |
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| 33 | + u32 saved_vals[]; |
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46 | 34 | }; |
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47 | 35 | |
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48 | 36 | static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank) |
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.. | .. |
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122 | 110 | static int uniphier_gpio_get_direction(struct gpio_chip *chip, |
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123 | 111 | unsigned int offset) |
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124 | 112 | { |
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125 | | - return uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DIR); |
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| 113 | + if (uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DIR)) |
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| 114 | + return GPIO_LINE_DIRECTION_IN; |
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| 115 | + |
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| 116 | + return GPIO_LINE_DIRECTION_OUT; |
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126 | 117 | } |
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127 | 118 | |
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128 | 119 | static int uniphier_gpio_direction_input(struct gpio_chip *chip, |
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.. | .. |
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156 | 147 | static void uniphier_gpio_set_multiple(struct gpio_chip *chip, |
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157 | 148 | unsigned long *mask, unsigned long *bits) |
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158 | 149 | { |
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159 | | - unsigned int bank, shift, bank_mask, bank_bits; |
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160 | | - int i; |
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| 150 | + unsigned long i, bank, bank_mask, bank_bits; |
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161 | 151 | |
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162 | | - for (i = 0; i < chip->ngpio; i += UNIPHIER_GPIO_LINES_PER_BANK) { |
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| 152 | + for_each_set_clump8(i, bank_mask, mask, chip->ngpio) { |
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163 | 153 | bank = i / UNIPHIER_GPIO_LINES_PER_BANK; |
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164 | | - shift = i % BITS_PER_LONG; |
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165 | | - bank_mask = (mask[BIT_WORD(i)] >> shift) & |
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166 | | - UNIPHIER_GPIO_BANK_MASK; |
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167 | | - bank_bits = bits[BIT_WORD(i)] >> shift; |
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| 154 | + bank_bits = bitmap_get_value8(bits, i); |
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168 | 155 | |
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169 | 156 | uniphier_gpio_bank_write(chip, bank, UNIPHIER_GPIO_PORT_DATA, |
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170 | 157 | bank_mask, bank_bits); |
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.. | .. |
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355 | 342 | struct uniphier_gpio_priv *priv; |
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356 | 343 | struct gpio_chip *chip; |
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357 | 344 | struct irq_chip *irq_chip; |
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358 | | - struct resource *regs; |
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359 | 345 | unsigned int nregs; |
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360 | 346 | u32 ngpios; |
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361 | 347 | int ret; |
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.. | .. |
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379 | 365 | if (!priv) |
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380 | 366 | return -ENOMEM; |
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381 | 367 | |
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382 | | - regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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383 | | - priv->regs = devm_ioremap_resource(dev, regs); |
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| 368 | + priv->regs = devm_platform_ioremap_resource(pdev, 0); |
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384 | 369 | if (IS_ERR(priv->regs)) |
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385 | 370 | return PTR_ERR(priv->regs); |
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386 | 371 | |
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