.. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0 |
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1 | 2 | /* |
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2 | 3 | * GPIO interface for Intel Sodaville SoCs. |
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3 | 4 | * |
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4 | 5 | * Copyright (c) 2010, 2011 Intel Corporation |
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5 | 6 | * |
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6 | 7 | * Author: Hans J. Koch <hjk@linutronix.de> |
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7 | | - * |
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8 | | - * This program is free software; you can redistribute it and/or modify |
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9 | | - * it under the terms of the GNU General Public License 2 as published |
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10 | | - * by the Free Software Foundation. |
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11 | | - * |
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12 | 8 | */ |
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13 | 9 | |
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14 | 10 | #include <linux/errno.h> |
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| 11 | +#include <linux/gpio/driver.h> |
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15 | 12 | #include <linux/init.h> |
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| 13 | +#include <linux/interrupt.h> |
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16 | 14 | #include <linux/io.h> |
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17 | 15 | #include <linux/irq.h> |
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18 | | -#include <linux/interrupt.h> |
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19 | 16 | #include <linux/kernel.h> |
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| 17 | +#include <linux/of_irq.h> |
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20 | 18 | #include <linux/pci.h> |
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21 | 19 | #include <linux/platform_device.h> |
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22 | | -#include <linux/of_irq.h> |
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23 | | -#include <linux/gpio/driver.h> |
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24 | 20 | |
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25 | 21 | #define DRV_NAME "sdv_gpio" |
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26 | 22 | #define SDV_NUM_PUB_GPIOS 12 |
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.. | .. |
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80 | 76 | static irqreturn_t sdv_gpio_pub_irq_handler(int irq, void *data) |
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81 | 77 | { |
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82 | 78 | struct sdv_gpio_chip_data *sd = data; |
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83 | | - u32 irq_stat = readl(sd->gpio_pub_base + GPSTR); |
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| 79 | + unsigned long irq_stat = readl(sd->gpio_pub_base + GPSTR); |
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| 80 | + int irq_bit; |
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84 | 81 | |
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85 | 82 | irq_stat &= readl(sd->gpio_pub_base + GPIO_INT); |
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86 | 83 | if (!irq_stat) |
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87 | 84 | return IRQ_NONE; |
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88 | 85 | |
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89 | | - while (irq_stat) { |
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90 | | - u32 irq_bit = __fls(irq_stat); |
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91 | | - |
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92 | | - irq_stat &= ~BIT(irq_bit); |
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| 86 | + for_each_set_bit(irq_bit, &irq_stat, 32) |
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93 | 87 | generic_handle_irq(irq_find_mapping(sd->id, irq_bit)); |
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94 | | - } |
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95 | 88 | |
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96 | 89 | return IRQ_HANDLED; |
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97 | 90 | } |
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.. | .. |
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155 | 148 | * we unmask & ACK the IRQ before the source of the interrupt is gone |
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156 | 149 | * then the interrupt is active again. |
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157 | 150 | */ |
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158 | | - sd->gc = irq_alloc_generic_chip("sdv-gpio", 1, sd->irq_base, |
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159 | | - sd->gpio_pub_base, handle_fasteoi_irq); |
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| 151 | + sd->gc = devm_irq_alloc_generic_chip(&pdev->dev, "sdv-gpio", 1, |
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| 152 | + sd->irq_base, |
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| 153 | + sd->gpio_pub_base, |
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| 154 | + handle_fasteoi_irq); |
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160 | 155 | if (!sd->gc) |
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161 | 156 | return -ENOMEM; |
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162 | 157 | |
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.. | .. |
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186 | 181 | const struct pci_device_id *pci_id) |
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187 | 182 | { |
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188 | 183 | struct sdv_gpio_chip_data *sd; |
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189 | | - unsigned long addr; |
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190 | | - const void *prop; |
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191 | | - int len; |
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192 | 184 | int ret; |
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193 | 185 | u32 mux_val; |
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194 | 186 | |
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195 | | - sd = kzalloc(sizeof(struct sdv_gpio_chip_data), GFP_KERNEL); |
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| 187 | + sd = devm_kzalloc(&pdev->dev, sizeof(*sd), GFP_KERNEL); |
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196 | 188 | if (!sd) |
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197 | 189 | return -ENOMEM; |
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198 | | - ret = pci_enable_device(pdev); |
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| 190 | + |
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| 191 | + ret = pcim_enable_device(pdev); |
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199 | 192 | if (ret) { |
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200 | 193 | dev_err(&pdev->dev, "can't enable device.\n"); |
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201 | | - goto done; |
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| 194 | + return ret; |
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202 | 195 | } |
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203 | 196 | |
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204 | | - ret = pci_request_region(pdev, GPIO_BAR, DRV_NAME); |
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| 197 | + ret = pcim_iomap_regions(pdev, 1 << GPIO_BAR, DRV_NAME); |
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205 | 198 | if (ret) { |
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206 | 199 | dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", GPIO_BAR); |
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207 | | - goto disable_pci; |
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| 200 | + return ret; |
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208 | 201 | } |
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209 | 202 | |
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210 | | - addr = pci_resource_start(pdev, GPIO_BAR); |
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211 | | - if (!addr) { |
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212 | | - ret = -ENODEV; |
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213 | | - goto release_reg; |
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214 | | - } |
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215 | | - sd->gpio_pub_base = ioremap(addr, pci_resource_len(pdev, GPIO_BAR)); |
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| 203 | + sd->gpio_pub_base = pcim_iomap_table(pdev)[GPIO_BAR]; |
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216 | 204 | |
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217 | | - prop = of_get_property(pdev->dev.of_node, "intel,muxctl", &len); |
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218 | | - if (prop && len == 4) { |
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219 | | - mux_val = of_read_number(prop, 1); |
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| 205 | + ret = of_property_read_u32(pdev->dev.of_node, "intel,muxctl", &mux_val); |
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| 206 | + if (!ret) |
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220 | 207 | writel(mux_val, sd->gpio_pub_base + GPMUXCTL); |
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221 | | - } |
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222 | 208 | |
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223 | 209 | ret = bgpio_init(&sd->chip, &pdev->dev, 4, |
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224 | 210 | sd->gpio_pub_base + GPINR, sd->gpio_pub_base + GPOUTR, |
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225 | 211 | NULL, sd->gpio_pub_base + GPOER, NULL, 0); |
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226 | 212 | if (ret) |
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227 | | - goto unmap; |
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| 213 | + return ret; |
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| 214 | + |
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228 | 215 | sd->chip.ngpio = SDV_NUM_PUB_GPIOS; |
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229 | 216 | |
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230 | | - ret = gpiochip_add_data(&sd->chip, sd); |
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| 217 | + ret = devm_gpiochip_add_data(&pdev->dev, &sd->chip, sd); |
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231 | 218 | if (ret < 0) { |
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232 | 219 | dev_err(&pdev->dev, "gpiochip_add() failed.\n"); |
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233 | | - goto unmap; |
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| 220 | + return ret; |
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234 | 221 | } |
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235 | 222 | |
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236 | 223 | ret = sdv_register_irqsupport(sd, pdev); |
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237 | 224 | if (ret) |
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238 | | - goto unmap; |
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| 225 | + return ret; |
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239 | 226 | |
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240 | 227 | pci_set_drvdata(pdev, sd); |
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241 | 228 | dev_info(&pdev->dev, "Sodaville GPIO driver registered.\n"); |
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242 | 229 | return 0; |
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243 | | - |
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244 | | -unmap: |
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245 | | - iounmap(sd->gpio_pub_base); |
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246 | | -release_reg: |
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247 | | - pci_release_region(pdev, GPIO_BAR); |
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248 | | -disable_pci: |
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249 | | - pci_disable_device(pdev); |
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250 | | -done: |
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251 | | - kfree(sd); |
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252 | | - return ret; |
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253 | 230 | } |
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254 | 231 | |
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255 | 232 | static const struct pci_device_id sdv_gpio_pci_ids[] = { |
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