.. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0 |
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1 | 2 | /* |
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2 | 3 | * Intel MID GPIO driver |
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3 | 4 | * |
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4 | 5 | * Copyright (c) 2008-2014,2016 Intel Corporation. |
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5 | | - * |
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6 | | - * This program is free software; you can redistribute it and/or modify |
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7 | | - * it under the terms of the GNU General Public License version 2 as |
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8 | | - * published by the Free Software Foundation. |
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9 | | - * |
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10 | | - * This program is distributed in the hope that it will be useful, |
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11 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 | | - * GNU General Public License for more details. |
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14 | 6 | */ |
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15 | 7 | |
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16 | 8 | /* Supports: |
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.. | .. |
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20 | 12 | */ |
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21 | 13 | |
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22 | 14 | #include <linux/delay.h> |
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| 15 | +#include <linux/gpio/driver.h> |
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23 | 16 | #include <linux/init.h> |
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24 | 17 | #include <linux/interrupt.h> |
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25 | 18 | #include <linux/io.h> |
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26 | | -#include <linux/gpio/driver.h> |
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27 | 19 | #include <linux/kernel.h> |
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28 | | -#include <linux/module.h> |
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29 | 20 | #include <linux/pci.h> |
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30 | 21 | #include <linux/platform_device.h> |
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31 | 22 | #include <linux/pm_runtime.h> |
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.. | .. |
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273 | 264 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7), |
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274 | 265 | .driver_data = (kernel_ulong_t)&gpio_cloverview_core, |
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275 | 266 | }, |
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276 | | - { 0 } |
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| 267 | + { } |
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277 | 268 | }; |
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278 | | -MODULE_DEVICE_TABLE(pci, intel_gpio_ids); |
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279 | 269 | |
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280 | 270 | static void intel_mid_irq_handler(struct irq_desc *desc) |
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281 | 271 | { |
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.. | .. |
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303 | 293 | chip->irq_eoi(data); |
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304 | 294 | } |
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305 | 295 | |
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306 | | -static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv) |
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| 296 | +static int intel_mid_irq_init_hw(struct gpio_chip *chip) |
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307 | 297 | { |
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| 298 | + struct intel_mid_gpio *priv = gpiochip_get_data(chip); |
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308 | 299 | void __iomem *reg; |
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309 | 300 | unsigned base; |
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310 | 301 | |
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.. | .. |
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319 | 310 | reg = gpio_reg(&priv->chip, base, GEDR); |
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320 | 311 | writel(~0, reg); |
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321 | 312 | } |
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| 313 | + |
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| 314 | + return 0; |
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322 | 315 | } |
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323 | 316 | |
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324 | 317 | static int __maybe_unused intel_gpio_runtime_idle(struct device *dev) |
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.. | .. |
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339 | 332 | u32 gpio_base; |
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340 | 333 | u32 irq_base; |
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341 | 334 | int retval; |
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| 335 | + struct gpio_irq_chip *girq; |
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342 | 336 | struct intel_mid_gpio_ddata *ddata = |
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343 | 337 | (struct intel_mid_gpio_ddata *)id->driver_data; |
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344 | 338 | |
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.. | .. |
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379 | 373 | |
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380 | 374 | spin_lock_init(&priv->lock); |
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381 | 375 | |
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| 376 | + girq = &priv->chip.irq; |
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| 377 | + girq->chip = &intel_mid_irqchip; |
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| 378 | + girq->init_hw = intel_mid_irq_init_hw; |
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| 379 | + girq->parent_handler = intel_mid_irq_handler; |
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| 380 | + girq->num_parents = 1; |
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| 381 | + girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents, |
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| 382 | + sizeof(*girq->parents), |
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| 383 | + GFP_KERNEL); |
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| 384 | + if (!girq->parents) |
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| 385 | + return -ENOMEM; |
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| 386 | + girq->parents[0] = pdev->irq; |
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| 387 | + girq->first = irq_base; |
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| 388 | + girq->default_type = IRQ_TYPE_NONE; |
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| 389 | + girq->handler = handle_simple_irq; |
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| 390 | + |
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382 | 391 | pci_set_drvdata(pdev, priv); |
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| 392 | + |
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383 | 393 | retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv); |
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384 | 394 | if (retval) { |
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385 | 395 | dev_err(&pdev->dev, "gpiochip_add error %d\n", retval); |
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386 | 396 | return retval; |
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387 | 397 | } |
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388 | | - |
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389 | | - retval = gpiochip_irqchip_add(&priv->chip, |
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390 | | - &intel_mid_irqchip, |
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391 | | - irq_base, |
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392 | | - handle_simple_irq, |
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393 | | - IRQ_TYPE_NONE); |
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394 | | - if (retval) { |
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395 | | - dev_err(&pdev->dev, |
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396 | | - "could not connect irqchip to gpiochip\n"); |
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397 | | - return retval; |
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398 | | - } |
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399 | | - |
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400 | | - intel_mid_irq_init_hw(priv); |
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401 | | - |
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402 | | - gpiochip_set_chained_irqchip(&priv->chip, |
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403 | | - &intel_mid_irqchip, |
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404 | | - pdev->irq, |
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405 | | - intel_mid_irq_handler); |
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406 | 398 | |
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407 | 399 | pm_runtime_put_noidle(&pdev->dev); |
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408 | 400 | pm_runtime_allow(&pdev->dev); |
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