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1 | | -/* |
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2 | | - This file is provided under a dual BSD/GPLv2 license. When using or |
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3 | | - redistributing this file, you may do so under either license. |
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4 | | - |
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5 | | - GPL LICENSE SUMMARY |
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6 | | - Copyright(c) 2014 Intel Corporation. |
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7 | | - This program is free software; you can redistribute it and/or modify |
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8 | | - it under the terms of version 2 of the GNU General Public License as |
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9 | | - published by the Free Software Foundation. |
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10 | | - |
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11 | | - This program is distributed in the hope that it will be useful, but |
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12 | | - WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | | - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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14 | | - General Public License for more details. |
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15 | | - |
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16 | | - Contact Information: |
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17 | | - qat-linux@intel.com |
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18 | | - |
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19 | | - BSD LICENSE |
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20 | | - Copyright(c) 2014 Intel Corporation. |
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21 | | - Redistribution and use in source and binary forms, with or without |
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22 | | - modification, are permitted provided that the following conditions |
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23 | | - are met: |
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24 | | - |
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25 | | - * Redistributions of source code must retain the above copyright |
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26 | | - notice, this list of conditions and the following disclaimer. |
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27 | | - * Redistributions in binary form must reproduce the above copyright |
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28 | | - notice, this list of conditions and the following disclaimer in |
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29 | | - the documentation and/or other materials provided with the |
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30 | | - distribution. |
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31 | | - * Neither the name of Intel Corporation nor the names of its |
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32 | | - contributors may be used to endorse or promote products derived |
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33 | | - from this software without specific prior written permission. |
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34 | | - |
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35 | | - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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36 | | - "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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37 | | - LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
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38 | | - A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
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39 | | - OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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40 | | - SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
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41 | | - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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42 | | - DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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43 | | - THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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44 | | - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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45 | | - OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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46 | | -*/ |
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| 1 | +/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */ |
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| 2 | +/* Copyright(c) 2014 - 2020 Intel Corporation */ |
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47 | 3 | #ifndef ADF_ACCEL_DEVICES_H_ |
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48 | 4 | #define ADF_ACCEL_DEVICES_H_ |
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49 | 5 | #include <linux/interrupt.h> |
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.. | .. |
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59 | 15 | #define ADF_C62XVF_DEVICE_NAME "c6xxvf" |
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60 | 16 | #define ADF_C3XXX_DEVICE_NAME "c3xxx" |
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61 | 17 | #define ADF_C3XXXVF_DEVICE_NAME "c3xxxvf" |
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62 | | -#define ADF_DH895XCC_PCI_DEVICE_ID 0x435 |
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63 | | -#define ADF_DH895XCCIOV_PCI_DEVICE_ID 0x443 |
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64 | | -#define ADF_C62X_PCI_DEVICE_ID 0x37c8 |
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65 | | -#define ADF_C62XIOV_PCI_DEVICE_ID 0x37c9 |
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66 | | -#define ADF_C3XXX_PCI_DEVICE_ID 0x19e2 |
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67 | | -#define ADF_C3XXXIOV_PCI_DEVICE_ID 0x19e3 |
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68 | 18 | #define ADF_ERRSOU3 (0x3A000 + 0x0C) |
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69 | 19 | #define ADF_ERRSOU5 (0x3A000 + 0xD8) |
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70 | 20 | #define ADF_DEVICE_FUSECTL_OFFSET 0x40 |
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.. | .. |
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103 | 53 | struct pci_dev *pci_dev; |
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104 | 54 | struct adf_accel_msix msix_entries; |
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105 | 55 | struct adf_bar pci_bars[ADF_PCI_MAX_BARS]; |
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106 | | - uint8_t revid; |
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107 | | - uint8_t sku; |
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| 56 | + u8 revid; |
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| 57 | + u8 sku; |
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108 | 58 | } __packed; |
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109 | 59 | |
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110 | 60 | enum dev_state { |
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.. | .. |
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144 | 94 | struct adf_hw_device_class { |
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145 | 95 | const char *name; |
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146 | 96 | const enum adf_device_type type; |
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147 | | - uint32_t instances; |
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| 97 | + u32 instances; |
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148 | 98 | } __packed; |
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149 | 99 | |
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150 | 100 | struct adf_cfg_device_data; |
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.. | .. |
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154 | 104 | |
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155 | 105 | struct adf_hw_device_data { |
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156 | 106 | struct adf_hw_device_class *dev_class; |
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157 | | - uint32_t (*get_accel_mask)(uint32_t fuse); |
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158 | | - uint32_t (*get_ae_mask)(uint32_t fuse); |
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159 | | - uint32_t (*get_sram_bar_id)(struct adf_hw_device_data *self); |
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160 | | - uint32_t (*get_misc_bar_id)(struct adf_hw_device_data *self); |
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161 | | - uint32_t (*get_etr_bar_id)(struct adf_hw_device_data *self); |
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162 | | - uint32_t (*get_num_aes)(struct adf_hw_device_data *self); |
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163 | | - uint32_t (*get_num_accels)(struct adf_hw_device_data *self); |
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164 | | - uint32_t (*get_pf2vf_offset)(uint32_t i); |
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165 | | - uint32_t (*get_vintmsk_offset)(uint32_t i); |
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| 107 | + u32 (*get_accel_mask)(u32 fuse); |
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| 108 | + u32 (*get_ae_mask)(u32 fuse); |
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| 109 | + u32 (*get_sram_bar_id)(struct adf_hw_device_data *self); |
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| 110 | + u32 (*get_misc_bar_id)(struct adf_hw_device_data *self); |
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| 111 | + u32 (*get_etr_bar_id)(struct adf_hw_device_data *self); |
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| 112 | + u32 (*get_num_aes)(struct adf_hw_device_data *self); |
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| 113 | + u32 (*get_num_accels)(struct adf_hw_device_data *self); |
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| 114 | + u32 (*get_pf2vf_offset)(u32 i); |
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| 115 | + u32 (*get_vintmsk_offset)(u32 i); |
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166 | 116 | enum dev_sku_info (*get_sku)(struct adf_hw_device_data *self); |
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167 | 117 | int (*alloc_irq)(struct adf_accel_dev *accel_dev); |
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168 | 118 | void (*free_irq)(struct adf_accel_dev *accel_dev); |
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.. | .. |
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173 | 123 | int (*init_arb)(struct adf_accel_dev *accel_dev); |
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174 | 124 | void (*exit_arb)(struct adf_accel_dev *accel_dev); |
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175 | 125 | void (*get_arb_mapping)(struct adf_accel_dev *accel_dev, |
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176 | | - const uint32_t **cfg); |
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| 126 | + const u32 **cfg); |
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177 | 127 | void (*disable_iov)(struct adf_accel_dev *accel_dev); |
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178 | 128 | void (*enable_ints)(struct adf_accel_dev *accel_dev); |
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179 | 129 | int (*enable_vf2pf_comms)(struct adf_accel_dev *accel_dev); |
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180 | 130 | void (*reset_device)(struct adf_accel_dev *accel_dev); |
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181 | 131 | const char *fw_name; |
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182 | 132 | const char *fw_mmp_name; |
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183 | | - uint32_t fuses; |
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184 | | - uint32_t accel_capabilities_mask; |
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185 | | - uint32_t instance_id; |
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186 | | - uint16_t accel_mask; |
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187 | | - uint16_t ae_mask; |
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188 | | - uint16_t tx_rings_mask; |
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189 | | - uint8_t tx_rx_gap; |
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190 | | - uint8_t num_banks; |
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191 | | - uint8_t num_accel; |
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192 | | - uint8_t num_logical_accel; |
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193 | | - uint8_t num_engines; |
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194 | | - uint8_t min_iov_compat_ver; |
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| 133 | + u32 fuses; |
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| 134 | + u32 accel_capabilities_mask; |
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| 135 | + u32 instance_id; |
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| 136 | + u16 accel_mask; |
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| 137 | + u16 ae_mask; |
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| 138 | + u16 tx_rings_mask; |
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| 139 | + u8 tx_rx_gap; |
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| 140 | + u8 num_banks; |
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| 141 | + u8 num_accel; |
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| 142 | + u8 num_logical_accel; |
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| 143 | + u8 num_engines; |
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| 144 | + u8 min_iov_compat_ver; |
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195 | 145 | } __packed; |
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196 | 146 | |
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197 | 147 | /* CSR write macro */ |
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.. | .. |
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248 | 198 | struct tasklet_struct pf2vf_bh_tasklet; |
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249 | 199 | struct mutex vf2pf_lock; /* protect CSR access */ |
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250 | 200 | struct completion iov_msg_completion; |
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251 | | - uint8_t compatible; |
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252 | | - uint8_t pf_version; |
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| 201 | + u8 compatible; |
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| 202 | + u8 pf_version; |
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253 | 203 | } vf; |
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254 | 204 | }; |
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255 | 205 | bool is_vf; |
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