add wifi6 8852be driver

hc

2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da

 kernel/drivers/clk/socfpga/clk-gate.c
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..
@@ -1,19 +1,9 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  *  Copyright 2011-2012 Calxeda, Inc.
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  *  Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
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  *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; either version 2 of the License, or
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- * (at your option) any later version.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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- *
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  * Based from clk-highbank.c
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- *
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  */
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 #include <linux/slab.h>
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 #include <linux/clk-provider.h>
..
..
@@ -40,22 +30,23 @@
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 {
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 	u32 l4_src;
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 	u32 perpll_src;
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+	const char *name = clk_hw_get_name(hwclk);
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-	if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
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+	if (streq(name, SOCFPGA_L4_MP_CLK)) {
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 		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
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 		return l4_src &= 0x1;
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 	}
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-	if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
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+	if (streq(name, SOCFPGA_L4_SP_CLK)) {
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 		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
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 		return !!(l4_src & 2);
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 	}
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43
 
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 	perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
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-	if (streq(hwclk->init->name, SOCFPGA_MMC_CLK))
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+	if (streq(name, SOCFPGA_MMC_CLK))
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 		return perpll_src &= 0x3;
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-	if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
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-			streq(hwclk->init->name, SOCFPGA_NAND_X_CLK))
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-			return (perpll_src >> 2) & 3;
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+	if (streq(name, SOCFPGA_NAND_CLK) ||
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+	    streq(name, SOCFPGA_NAND_X_CLK))
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+		return (perpll_src >> 2) & 3;
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50
 
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 	/* QSPI clock */
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 	return (perpll_src >> 4) & 3;
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..
@@ -65,24 +56,25 @@
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 static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
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 {
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 	u32 src_reg;
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+	const char *name = clk_hw_get_name(hwclk);
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-	if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
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+	if (streq(name, SOCFPGA_L4_MP_CLK)) {
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 		src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
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 		src_reg &= ~0x1;
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 		src_reg |= parent;
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 		writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
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-	} else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
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+	} else if (streq(name, SOCFPGA_L4_SP_CLK)) {
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 		src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
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 		src_reg &= ~0x2;
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 		src_reg |= (parent << 1);
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 		writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
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 	} else {
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 		src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
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-		if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) {
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+		if (streq(name, SOCFPGA_MMC_CLK)) {
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 			src_reg &= ~0x3;
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 			src_reg |= parent;
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-		} else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
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-			streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) {
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+		} else if (streq(name, SOCFPGA_NAND_CLK) ||
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+			streq(name, SOCFPGA_NAND_X_CLK)) {
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 			src_reg &= ~0xC;
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 			src_reg |= (parent << 2);
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 		} else {/* QSPI clock */
..
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@@ -176,23 +168,30 @@
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 	.set_parent = socfpga_clk_set_parent,
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 };
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170
 
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-static void __init __socfpga_gate_init(struct device_node *node,
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-	const struct clk_ops *ops)
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+void __init socfpga_gate_init(struct device_node *node)
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 {
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 	u32 clk_gate[2];
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 	u32 div_reg[3];
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 	u32 clk_phase[2];
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 	u32 fixed_div;
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-	struct clk *clk;
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+	struct clk_hw *hw_clk;
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 	struct socfpga_gate_clk *socfpga_clk;
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 	const char *clk_name = node->name;
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 	const char *parent_name[SOCFPGA_MAX_PARENTS];
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-	struct clk_init_data init = {};
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+	struct clk_init_data init;
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+	struct clk_ops *ops;
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 	int rc;
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+	int err;
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 	socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
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 	if (WARN_ON(!socfpga_clk))
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 		return;
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+
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+	ops = kmemdup(&gateclk_ops, sizeof(gateclk_ops), GFP_KERNEL);
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+	if (WARN_ON(!ops)) {
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+		kfree(socfpga_clk);
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+		return;
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+	}
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 	rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
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 	if (rc)
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@@ -202,8 +201,8 @@
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 		socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
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 		socfpga_clk->hw.bit_idx = clk_gate[1];
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-		gateclk_ops.enable = clk_gate_ops.enable;
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-		gateclk_ops.disable = clk_gate_ops.disable;
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+		ops->enable = clk_gate_ops.enable;
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+		ops->disable = clk_gate_ops.disable;
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 	}
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 	rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
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@@ -234,20 +233,23 @@
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 	init.flags = 0;
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234
 
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 	init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
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+	if (init.num_parents < 2) {
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+		ops->get_parent = NULL;
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+		ops->set_parent = NULL;
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+	}
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+
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 	init.parent_names = parent_name;
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 	socfpga_clk->hw.hw.init = &init;
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-	clk = clk_register(NULL, &socfpga_clk->hw.hw);
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-	if (WARN_ON(IS_ERR(clk))) {
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+	hw_clk = &socfpga_clk->hw.hw;
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+
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+	err = clk_hw_register(NULL, hw_clk);
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+	if (err) {
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+		kfree(ops);
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 		kfree(socfpga_clk);
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 		return;
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 	}
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-	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
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+	rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);
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 	if (WARN_ON(rc))
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 		return;
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-}
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-
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-void __init socfpga_gate_init(struct device_node *node)
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-{
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-	__socfpga_gate_init(node, &gateclk_ops);
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 }