kernel/drivers/clk/rockchip/regmap/clk-regmap-fractional-divider.c
.. .. @@ -47,6 +47,16 @@ 47 47 struct clk_hw *p_parent; 48 48 unsigned long scale; 49 49 50 + if (!rate) {51 + *m = 0;52 + *n = 1;53 +54 + dev_dbg(fd->dev, "%s rate:(%ld) maybe invalid frequency setting!\n",55 + clk_hw_get_name(hw), rate);56 +57 + return;58 + }59 +50 60 p_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); 51 61 if ((rate * 20 > p_rate) && (p_rate % rate != 0)) { 52 62 p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));