.. | .. |
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24 | 24 | #include <linux/rational.h> |
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25 | 25 | #include "clk.h" |
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26 | 26 | |
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| 27 | +#ifdef MODULE |
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| 28 | +static HLIST_HEAD(clk_ctx_list); |
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| 29 | +#endif |
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| 30 | + |
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27 | 31 | /** |
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28 | 32 | * Register a clock branch. |
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29 | 33 | * Most clock branches have a form like |
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.. | .. |
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185 | 189 | struct clk_hw *p_parent; |
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186 | 190 | unsigned long scale; |
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187 | 191 | |
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| 192 | + if (rate == 0) { |
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| 193 | + pr_warn("%s p_rate(%ld), rate(%ld), maybe invalid frequency setting!\n", |
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| 194 | + clk_hw_get_name(hw), *parent_rate, rate); |
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| 195 | + *m = 0; |
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| 196 | + *n = 1; |
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| 197 | + return; |
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| 198 | + } |
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| 199 | + |
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188 | 200 | p_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); |
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189 | 201 | if ((rate * 20 > p_rate) && (p_rate % rate != 0)) { |
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190 | 202 | p_parent = clk_hw_get_parent(clk_hw_get_parent(hw)); |
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.. | .. |
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221 | 233 | * for m and n. In the result it will be the nearest rate left shifted |
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222 | 234 | * by (scale - fd->nwidth) bits. |
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223 | 235 | */ |
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| 236 | + if (*parent_rate == 0) { |
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| 237 | + pr_warn("%s p_rate(%ld), rate(%ld), maybe invalid frequency setting!\n", |
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| 238 | + clk_hw_get_name(hw), *parent_rate, rate); |
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| 239 | + *m = 0; |
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| 240 | + *n = 1; |
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| 241 | + return; |
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| 242 | + } |
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224 | 243 | scale = fls_long(*parent_rate / rate - 1); |
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225 | 244 | if (scale > fd->nwidth) |
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226 | 245 | rate <<= scale - fd->nwidth; |
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.. | .. |
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417 | 436 | "rockchip,grf"); |
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418 | 437 | ctx->pmugrf = syscon_regmap_lookup_by_phandle(ctx->cru_node, |
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419 | 438 | "rockchip,pmugrf"); |
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| 439 | + |
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| 440 | +#ifdef MODULE |
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| 441 | + hlist_add_head(&ctx->list_node, &clk_ctx_list); |
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| 442 | +#endif |
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420 | 443 | |
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421 | 444 | return ctx; |
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422 | 445 | |
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.. | .. |
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783 | 806 | |
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784 | 807 | } |
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785 | 808 | EXPORT_SYMBOL_GPL(rockchip_clk_unprotect); |
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| 809 | + |
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| 810 | +void rockchip_clk_disable_unused(void) |
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| 811 | +{ |
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| 812 | + struct rockchip_clk_provider *ctx; |
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| 813 | + struct clk *clk; |
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| 814 | + struct clk_hw *hw; |
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| 815 | + int i = 0, flag = 0; |
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| 816 | + |
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| 817 | + hlist_for_each_entry(ctx, &clk_ctx_list, list_node) { |
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| 818 | + for (i = 0; i < ctx->clk_data.clk_num; i++) { |
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| 819 | + clk = ctx->clk_data.clks[i]; |
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| 820 | + if (clk && !IS_ERR(clk)) { |
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| 821 | + hw = __clk_get_hw(clk); |
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| 822 | + if (hw) |
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| 823 | + flag = clk_hw_get_flags(hw); |
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| 824 | + if (flag & CLK_IGNORE_UNUSED) |
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| 825 | + continue; |
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| 826 | + if (flag & CLK_IS_CRITICAL) |
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| 827 | + continue; |
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| 828 | + clk_prepare_enable(clk); |
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| 829 | + clk_disable_unprepare(clk); |
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| 830 | + } |
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| 831 | + } |
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| 832 | + } |
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| 833 | +} |
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| 834 | +EXPORT_SYMBOL_GPL(rockchip_clk_disable_unused); |
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786 | 835 | #endif /* MODULE */ |
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