~hc/RK356X_SDK_RELEASE.git

..	..	@@ -5,8 +5,10 @@
5	5	*/
6	6
7	7	#include <linux/clk-provider.h>
	8	+#include <linux/module.h>
8	9	#include <linux/of.h>
9	10	#include <linux/of_address.h>
	11	+#include <linux/of_device.h>
10	12	#include <linux/syscore_ops.h>
11	13	#include <dt-bindings/clock/rv1126-cru.h>
12	14	#include "clk.h"
..	..	@@ -30,26 +32,56 @@
30	32	static struct rockchip_pll_rate_table rv1126_pll_rates[] = {
31	33	/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
32	34	RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
	35	+ RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
	36	+ RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0),
	37	+ RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0),
	38	+ RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0),
33	39	RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0),
	40	+ RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0),
	41	+ RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0),
	42	+ RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0),
34	43	RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0),
	44	+ RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0),
	45	+ RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0),
	46	+ RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0),
	47	+ RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0),
	48	+ RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0),
35	49	RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0),
	50	+ RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0),
	51	+ RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0),
36	52	RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
37	53	RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
	54	+ RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0),
	55	+ RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0),
38	56	RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
39	57	RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
	58	+ RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
	59	+ RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
	60	+ RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
	61	+ RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
	62	+ RK3036_PLL_RATE(900000000, 1, 75, 2, 1, 1, 0),
	63	+ RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
	64	+ RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
	65	+ RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
40	66	RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
41	67	RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
	68	+ RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),
42	69	RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),
	70	+ RK3036_PLL_RATE(624000000, 1, 104, 4, 1, 1, 0),
43	71	#ifdef CONFIG_ROCKCHIP_LOW_PERFORMANCE
44	72	RK3036_PLL_RATE(600000000, 1, 50, 2, 1, 1, 0),
45	73	#else
46	74	RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
47	75	#endif
48	76	RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
	77	+ RK3036_PLL_RATE(504000000, 1, 84, 4, 1, 1, 0),
49	78	RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
50	79	RK3036_PLL_RATE(496742400, 1, 124, 6, 1, 0, 3113851),
51	80	RK3036_PLL_RATE(491520000, 1, 40, 2, 1, 0, 16106127),
52	81	RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
	82	+ RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
	83	+ RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
	84	+ RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
53	85	{ /* sentinel */ },
54	86	};
55	87
..	..	@@ -77,13 +109,33 @@
77	109
78	110	static struct rockchip_cpuclk_rate_table rv1126_cpuclk_rates[] __initdata = {
79	111	RV1126_CPUCLK_RATE(1608000000, 1, 7),
	112	+ RV1126_CPUCLK_RATE(1584000000, 1, 7),
	113	+ RV1126_CPUCLK_RATE(1560000000, 1, 7),
	114	+ RV1126_CPUCLK_RATE(1536000000, 1, 7),
80	115	RV1126_CPUCLK_RATE(1512000000, 1, 7),
	116	+ RV1126_CPUCLK_RATE(1488000000, 1, 5),
	117	+ RV1126_CPUCLK_RATE(1464000000, 1, 5),
	118	+ RV1126_CPUCLK_RATE(1440000000, 1, 5),
81	119	RV1126_CPUCLK_RATE(1416000000, 1, 5),
	120	+ RV1126_CPUCLK_RATE(1392000000, 1, 5),
	121	+ RV1126_CPUCLK_RATE(1368000000, 1, 5),
	122	+ RV1126_CPUCLK_RATE(1344000000, 1, 5),
	123	+ RV1126_CPUCLK_RATE(1320000000, 1, 5),
	124	+ RV1126_CPUCLK_RATE(1296000000, 1, 5),
	125	+ RV1126_CPUCLK_RATE(1272000000, 1, 5),
	126	+ RV1126_CPUCLK_RATE(1248000000, 1, 5),
	127	+ RV1126_CPUCLK_RATE(1224000000, 1, 5),
82	128	RV1126_CPUCLK_RATE(1200000000, 1, 5),
	129	+ RV1126_CPUCLK_RATE(1104000000, 1, 5),
83	130	RV1126_CPUCLK_RATE(1008000000, 1, 5),
	131	+ RV1126_CPUCLK_RATE(912000000, 1, 5),
84	132	RV1126_CPUCLK_RATE(816000000, 1, 3),
	133	+ RV1126_CPUCLK_RATE(696000000, 1, 3),
85	134	RV1126_CPUCLK_RATE(600000000, 1, 3),
86	135	RV1126_CPUCLK_RATE(408000000, 1, 1),
	136	+ RV1126_CPUCLK_RATE(312000000, 1, 1),
	137	+ RV1126_CPUCLK_RATE(216000000, 1, 1),
	138	+ RV1126_CPUCLK_RATE(96000000, 1, 1),
87	139	};
88	140
89	141	static const struct rockchip_cpuclk_reg_data rv1126_cpuclk_data = {
..	..	@@ -146,7 +198,6 @@
146	198
147	199	#ifndef CONFIG_ROCKCHIP_LOW_PERFORMANCE
148	200	PNAME(mux_gpll_usb480m_cpll_xin24m_p) = { "gpll", "usb480m", "cpll", "xin24m" };
149		-PNAME(mux_armclk_p) = { "gpll", "cpll", "apll" };
150	201	PNAME(mux_gpll_cpll_dpll_p) = { "gpll", "cpll", "dummy_dpll" };
151	202	PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
152	203	PNAME(mux_gpll_cpll_usb480m_xin24m_p) = { "gpll", "cpll", "usb480m", "xin24m" };
..	..	@@ -158,7 +209,6 @@
158	209	PNAME(mux_gpll_cpll_apll_hpll_p) = { "gpll", "cpll", "dummy_apll", "hpll" };
159	210	#else
160	211	PNAME(mux_gpll_usb480m_cpll_xin24m_p) = { "gpll", "usb480m", "dummy_cpll", "xin24m" };
161		-PNAME(mux_armclk_p) = { "gpll", "dummy_cpll", "apll" };
162	212	PNAME(mux_gpll_cpll_dpll_p) = { "gpll", "dummy_cpll", "dummy_dpll" };
163	213	PNAME(mux_gpll_cpll_p) = { "gpll", "dummy_cpll" };
164	214	PNAME(mux_gpll_cpll_usb480m_xin24m_p) = { "gpll", "dummy_cpll", "usb480m", "xin24m" };
..	..	@@ -174,7 +224,7 @@
174	224
175	225	static struct rockchip_pll_clock rv1126_pmu_pll_clks[] __initdata = {
176	226	[gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
177		- CLK_IGNORE_UNUSED, RV1126_PMU_PLL_CON(0),
	227	+ CLK_IS_CRITICAL, RV1126_PMU_PLL_CON(0),
178	228	RV1126_PMU_MODE, 0, 3, 0, rv1126_pll_rates),
179	229	};
180	230
..	..	@@ -185,12 +235,21 @@
185	235	[dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
186	236	CLK_IGNORE_UNUSED, RV1126_PLL_CON(8),
187	237	RV1126_MODE_CON, 2, 1, 0, NULL),
	238	+#ifndef CONFIG_ROCKCHIP_LOW_PERFORMANCE
	239	+ [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
	240	+ CLK_IS_CRITICAL, RV1126_PLL_CON(16),
	241	+ RV1126_MODE_CON, 4, 2, 0, rv1126_pll_rates),
	242	+ [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p,
	243	+ CLK_IS_CRITICAL, RV1126_PLL_CON(24),
	244	+ RV1126_MODE_CON, 6, 4, 0, rv1126_pll_rates),
	245	+#else
188	246	[cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
189	247	0, RV1126_PLL_CON(16),
190	248	RV1126_MODE_CON, 4, 2, 0, rv1126_pll_rates),
191	249	[hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p,
192	250	0, RV1126_PLL_CON(24),
193	251	RV1126_MODE_CON, 6, 4, 0, rv1126_pll_rates),
	252	+#endif
194	253	};
195	254
196	255	#define MFLAGS CLK_MUX_HIWORD_MASK
..	..	@@ -257,53 +316,19 @@
257	316	MUX(CLK_MIPICSI_OUT_MUX, "clk_mipicsi_out2io_mux", mux_mipicsi_out2io_p, CLK_SET_RATE_PARENT,
258	317	RV1126_CLKSEL_CON(73), 10, 2, MFLAGS);
259	318
260		-static struct rockchip_clk_branch rv1126_aclk_pdvi_np5 __initdata =
261		- COMPOSITE_HALFDIV_OFFSET(ACLK_PDVI_NP5, "aclk_pdvi_np5", mux_cpll_gpll_hpll_p, 0,
262		- RV1126_CLKSEL_CON(49), 6, 2, MFLAGS,
263		- RV1126_CLKSEL_CON(76), 0, 5, DFLAGS,
264		- RV1126_CLKGATE_CON(16), 13, GFLAGS);
265		-
266		-static struct rockchip_clk_branch rv1126_clk_isp_np5 __initdata =
267		- COMPOSITE_HALFDIV_OFFSET(CLK_ISP_NP5, "clk_isp_np5", mux_gpll_cpll_hpll_p, 0,
268		- RV1126_CLKSEL_CON(50), 6, 2, MFLAGS,
269		- RV1126_CLKSEL_CON(76), 8, 5, DFLAGS,
270		- RV1126_CLKGATE_CON(16), 14, GFLAGS);
271		-
272		-static struct rockchip_clk_branch rv1126_aclk_pdispp_np5 __initdata =
273		- COMPOSITE_HALFDIV_OFFSET(ACLK_PDISPP_NP5, "aclk_pdispp_np5", mux_cpll_gpll_hpll_p, 0,
274		- RV1126_CLKSEL_CON(68), 6, 2, MFLAGS,
275		- RV1126_CLKSEL_CON(77), 0, 5, DFLAGS,
276		- RV1126_CLKGATE_CON(16), 8, GFLAGS);
277		-
278		-static struct rockchip_clk_branch rv1126_clk_ispp_np5 __initdata =
279		- COMPOSITE_HALFDIV_OFFSET(CLK_ISPP_NP5, "clk_ispp_np5", mux_cpll_gpll_hpll_p, 0,
280		- RV1126_CLKSEL_CON(69), 6, 2, MFLAGS,
281		- RV1126_CLKSEL_CON(77), 8, 5, DFLAGS,
282		- RV1126_CLKGATE_CON(16), 7, GFLAGS);
283		-
284		-static struct rockchip_clk_branch rv1126_aclk_pdnpu_npu5 __initdata =
285		- COMPOSITE_HALFDIV(ACLK_PDNPU_NP5, "aclk_pdnpu_np5", mux_gpll_cpll_apll_hpll_p, 0,
286		- RV1126_CLKSEL_CON(65), 8, 2, MFLAGS, 4, 4, DFLAGS,
287		- RV1126_CLKGATE_CON(22), 1, GFLAGS);
288		-
289		-static struct rockchip_clk_branch rv1126_clk_npu_np5 __initdata =
290		- COMPOSITE_HALFDIV(CLK_NPU_NP5, "clk_npu_np5", mux_gpll_cpll_apll_hpll_p, 0,
291		- RV1126_CLKSEL_CON(67), 8, 2, MFLAGS, 4, 4, DFLAGS,
292		- RV1126_CLKGATE_CON(22), 10, GFLAGS);
293		-
294	319	static struct rockchip_clk_branch rv1126_clk_pmu_branches[] __initdata = {
295	320	/*
296	321	* Clock-Architecture Diagram 2
297	322	*/
298	323	/* PD_PMU */
299		- COMPOSITE_NOMUX(PCLK_PDPMU, "pclk_pdpmu", "gpll", CLK_IGNORE_UNUSED,
	324	+ COMPOSITE_NOMUX(PCLK_PDPMU, "pclk_pdpmu", "gpll", CLK_IS_CRITICAL,
300	325	RV1126_PMU_CLKSEL_CON(1), 0, 5, DFLAGS,
301	326	RV1126_PMU_CLKGATE_CON(0), 0, GFLAGS),
302	327
303	328	COMPOSITE_FRACMUX(CLK_OSC0_DIV32K, "clk_osc0_div32k", "xin24m", CLK_IGNORE_UNUSED,
304	329	RV1126_PMU_CLKSEL_CON(13), 0,
305	330	RV1126_PMU_CLKGATE_CON(2), 9, GFLAGS,
306		- &rv1126_rtc32k_fracmux, 0),
	331	+ &rv1126_rtc32k_fracmux),
307	332
308	333	MUXPMUGRF(CLK_32K_IOE, "clk_32k_ioe", mux_clk_32k_ioe_p, 0,
309	334	RV1126_PMUGRF_SOC_CON0, 0, 1, MFLAGS),
..	..	@@ -327,7 +352,7 @@
327	352	COMPOSITE_FRACMUX(SCLK_UART1_FRACDIV, "sclk_uart1_fracdiv", "sclk_uart1_div", CLK_SET_RATE_PARENT,
328	353	RV1126_PMU_CLKSEL_CON(5), 0,
329	354	RV1126_PMU_CLKGATE_CON(0), 13, GFLAGS,
330		- &rv1126_uart1_fracmux, RV1126_FRAC_MAX_PRATE),
	355	+ &rv1126_uart1_fracmux),
331	356	GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0,
332	357	RV1126_PMU_CLKGATE_CON(0), 14, GFLAGS),
333	358
..	..	@@ -398,6 +423,24 @@
398	423	MUX(CLK_MIPIDSIPHY_REF, "clk_mipidsiphy_ref", mux_mipidsiphy_ref_p, CLK_SET_RATE_PARENT,
399	424	RV1126_PMU_CLKSEL_CON(7), 15, 1, MFLAGS),
400	425
	426	+#ifndef CONFIG_ROCKCHIP_LOW_PERFORMANCE
	427	+ GATE(CLK_PMU, "clk_pmu", "xin24m", CLK_IGNORE_UNUSED,
	428	+ RV1126_PMU_CLKGATE_CON(0), 15, GFLAGS),
	429	+
	430	+ GATE(PCLK_PMUSGRF, "pclk_pmusgrf", "pclk_pdpmu", CLK_IGNORE_UNUSED,
	431	+ RV1126_PMU_CLKGATE_CON(0), 4, GFLAGS),
	432	+ GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pdpmu", CLK_IGNORE_UNUSED,
	433	+ RV1126_PMU_CLKGATE_CON(1), 13, GFLAGS),
	434	+ GATE(PCLK_PMUCRU, "pclk_pmucru", "pclk_pdpmu", CLK_IGNORE_UNUSED,
	435	+ RV1126_PMU_CLKGATE_CON(2), 4, GFLAGS),
	436	+ GATE(PCLK_CHIPVEROTP, "pclk_chipverotp", "pclk_pdpmu", CLK_IGNORE_UNUSED,
	437	+ RV1126_PMU_CLKGATE_CON(2), 0, GFLAGS),
	438	+ GATE(PCLK_PDPMU_NIU, "pclk_pdpmu_niu", "pclk_pdpmu", CLK_IGNORE_UNUSED,
	439	+ RV1126_PMU_CLKGATE_CON(0), 2, GFLAGS),
	440	+
	441	+ GATE(PCLK_SCRKEYGEN, "pclk_scrkeygen", "pclk_pdpmu", 0,
	442	+ RV1126_PMU_CLKGATE_CON(0), 7, GFLAGS),
	443	+#endif
401	444	};
402	445
403	446	static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
..	..	@@ -412,7 +455,7 @@
412	455	* Clock-Architecture Diagram 3
413	456	*/
414	457	/* PD_CORE */
415		- COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
	458	+ COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IS_CRITICAL,
416	459	RV1126_CLKSEL_CON(1), 0, 3, DFLAGS \| CLK_DIVIDER_READ_ONLY,
417	460	RV1126_CLKGATE_CON(0), 6, GFLAGS),
418	461	GATE(CLK_CORE_CPUPVTM, "clk_core_cpupvtm", "armclk", 0,
..	..	@@ -429,20 +472,20 @@
429	472	* Clock-Architecture Diagram 4
430	473	*/
431	474	/* PD_BUS */
432		- COMPOSITE(0, "aclk_pdbus_pre", mux_gpll_cpll_dpll_p, CLK_IGNORE_UNUSED,
	475	+ COMPOSITE(0, "aclk_pdbus_pre", mux_gpll_cpll_dpll_p, CLK_IS_CRITICAL,
433	476	RV1126_CLKSEL_CON(2), 6, 2, MFLAGS, 0, 5, DFLAGS,
434	477	RV1126_CLKGATE_CON(2), 0, GFLAGS),
435		- GATE(ACLK_PDBUS, "aclk_pdbus", "aclk_pdbus_pre", CLK_IGNORE_UNUSED,
	478	+ GATE(ACLK_PDBUS, "aclk_pdbus", "aclk_pdbus_pre", CLK_IS_CRITICAL,
436	479	RV1126_CLKGATE_CON(2), 11, GFLAGS),
437		- COMPOSITE(0, "hclk_pdbus_pre", mux_hclk_pclk_pdbus_p, CLK_IGNORE_UNUSED,
	480	+ COMPOSITE(0, "hclk_pdbus_pre", mux_hclk_pclk_pdbus_p, CLK_IS_CRITICAL,
438	481	RV1126_CLKSEL_CON(2), 15, 1, MFLAGS, 8, 5, DFLAGS,
439	482	RV1126_CLKGATE_CON(2), 1, GFLAGS),
440		- GATE(HCLK_PDBUS, "hclk_pdbus", "hclk_pdbus_pre", CLK_IGNORE_UNUSED,
	483	+ GATE(HCLK_PDBUS, "hclk_pdbus", "hclk_pdbus_pre", CLK_IS_CRITICAL,
441	484	RV1126_CLKGATE_CON(2), 12, GFLAGS),
442		- COMPOSITE(0, "pclk_pdbus_pre", mux_hclk_pclk_pdbus_p, CLK_IGNORE_UNUSED,
	485	+ COMPOSITE(0, "pclk_pdbus_pre", mux_hclk_pclk_pdbus_p, CLK_IS_CRITICAL,
443	486	RV1126_CLKSEL_CON(3), 7, 1, MFLAGS, 0, 5, DFLAGS,
444	487	RV1126_CLKGATE_CON(2), 2, GFLAGS),
445		- GATE(PCLK_PDBUS, "pclk_pdbus", "pclk_pdbus_pre", CLK_IGNORE_UNUSED,
	488	+ GATE(PCLK_PDBUS, "pclk_pdbus", "pclk_pdbus_pre", CLK_IS_CRITICAL,
446	489	RV1126_CLKGATE_CON(2), 13, GFLAGS),
447	490	/* aclk_dmac is controlled by sgrf_clkgat_con. */
448	491	SGRF_GATE(ACLK_DMAC, "aclk_dmac", "hclk_pdbus"),
..	..	@@ -475,7 +518,7 @@
475	518	COMPOSITE_FRACMUX(SCLK_UART0_FRAC, "sclk_uart0_frac", "sclk_uart0_div", CLK_SET_RATE_PARENT,
476	519	RV1126_CLKSEL_CON(11), 0,
477	520	RV1126_CLKGATE_CON(5), 2, GFLAGS,
478		- &rv1126_uart0_fracmux, RV1126_FRAC_MAX_PRATE),
	521	+ &rv1126_uart0_fracmux),
479	522	GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 0,
480	523	RV1126_CLKGATE_CON(5), 3, GFLAGS),
481	524	GATE(PCLK_UART2, "pclk_uart2", "pclk_pdbus", 0,
..	..	@@ -486,7 +529,7 @@
486	529	COMPOSITE_FRACMUX(SCLK_UART2_FRAC, "sclk_uart2_frac", "sclk_uart2_div", CLK_SET_RATE_PARENT,
487	530	RV1126_CLKSEL_CON(13), 0,
488	531	RV1126_CLKGATE_CON(5), 6, GFLAGS,
489		- &rv1126_uart2_fracmux, RV1126_FRAC_MAX_PRATE),
	532	+ &rv1126_uart2_fracmux),
490	533	GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 0,
491	534	RV1126_CLKGATE_CON(5), 7, GFLAGS),
492	535	GATE(PCLK_UART3, "pclk_uart3", "pclk_pdbus", 0,
..	..	@@ -497,7 +540,7 @@
497	540	COMPOSITE_FRACMUX(SCLK_UART3_FRAC, "sclk_uart3_frac", "sclk_uart3_div", CLK_SET_RATE_PARENT,
498	541	RV1126_CLKSEL_CON(15), 0,
499	542	RV1126_CLKGATE_CON(5), 10, GFLAGS,
500		- &rv1126_uart3_fracmux, RV1126_FRAC_MAX_PRATE),
	543	+ &rv1126_uart3_fracmux),
501	544	GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0,
502	545	RV1126_CLKGATE_CON(5), 11, GFLAGS),
503	546	GATE(PCLK_UART4, "pclk_uart4", "pclk_pdbus", 0,
..	..	@@ -508,7 +551,7 @@
508	551	COMPOSITE_FRACMUX(SCLK_UART4_FRAC, "sclk_uart4_frac", "sclk_uart4_div", CLK_SET_RATE_PARENT,
509	552	RV1126_CLKSEL_CON(17), 0,
510	553	RV1126_CLKGATE_CON(5), 14, GFLAGS,
511		- &rv1126_uart4_fracmux, RV1126_FRAC_MAX_PRATE),
	554	+ &rv1126_uart4_fracmux),
512	555	GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0,
513	556	RV1126_CLKGATE_CON(5), 15, GFLAGS),
514	557	GATE(PCLK_UART5, "pclk_uart5", "pclk_pdbus", 0,
..	..	@@ -519,7 +562,7 @@
519	562	COMPOSITE_FRACMUX(SCLK_UART5_FRAC, "sclk_uart5_frac", "sclk_uart5_div", CLK_SET_RATE_PARENT,
520	563	RV1126_CLKSEL_CON(19), 0,
521	564	RV1126_CLKGATE_CON(6), 2, GFLAGS,
522		- &rv1126_uart5_fracmux, RV1126_FRAC_MAX_PRATE),
	565	+ &rv1126_uart5_fracmux),
523	566	GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0,
524	567	RV1126_CLKGATE_CON(6), 3, GFLAGS),
525	568
..	..	@@ -672,7 +715,7 @@
672	715	COMPOSITE_FRACMUX(MCLK_I2S0_TX_FRACDIV, "mclk_i2s0_tx_fracdiv", "mclk_i2s0_tx_div", CLK_SET_RATE_PARENT,
673	716	RV1126_CLKSEL_CON(28), 0,
674	717	RV1126_CLKGATE_CON(9), 6, GFLAGS,
675		- &rv1126_i2s0_tx_fracmux, RV1126_FRAC_MAX_PRATE),
	718	+ &rv1126_i2s0_tx_fracmux),
676	719	GATE(MCLK_I2S0_TX, "mclk_i2s0_tx", "mclk_i2s0_tx_mux", 0,
677	720	RV1126_CLKGATE_CON(9), 9, GFLAGS),
678	721	COMPOSITE(MCLK_I2S0_RX_DIV, "mclk_i2s0_rx_div", mux_cpll_gpll_p, 0,
..	..	@@ -681,7 +724,7 @@
681	724	COMPOSITE_FRACMUX(MCLK_I2S0_RX_FRACDIV, "mclk_i2s0_rx_fracdiv", "mclk_i2s0_rx_div", CLK_SET_RATE_PARENT,
682	725	RV1126_CLKSEL_CON(29), 0,
683	726	RV1126_CLKGATE_CON(9), 8, GFLAGS,
684		- &rv1126_i2s0_rx_fracmux, RV1126_FRAC_MAX_PRATE),
	727	+ &rv1126_i2s0_rx_fracmux),
685	728	GATE(MCLK_I2S0_RX, "mclk_i2s0_rx", "mclk_i2s0_rx_mux", 0,
686	729	RV1126_CLKGATE_CON(9), 10, GFLAGS),
687	730	COMPOSITE_NODIV(MCLK_I2S0_TX_OUT2IO, "mclk_i2s0_tx_out2io", mux_i2s0_tx_out2io_p, CLK_SET_RATE_PARENT,
..	..	@@ -699,7 +742,7 @@
699	742	COMPOSITE_FRACMUX(MCLK_I2S1_FRACDIV, "mclk_i2s1_fracdiv", "mclk_i2s1_div", CLK_SET_RATE_PARENT,
700	743	RV1126_CLKSEL_CON(32), 0,
701	744	RV1126_CLKGATE_CON(10), 2, GFLAGS,
702		- &rv1126_i2s1_fracmux, RV1126_FRAC_MAX_PRATE),
	745	+ &rv1126_i2s1_fracmux),
703	746	GATE(MCLK_I2S1, "mclk_i2s1", "mclk_i2s1_mux", 0,
704	747	RV1126_CLKGATE_CON(10), 3, GFLAGS),
705	748	COMPOSITE_NODIV(MCLK_I2S1_OUT2IO, "mclk_i2s1_out2io", mux_i2s1_out2io_p, CLK_SET_RATE_PARENT,
..	..	@@ -713,7 +756,7 @@
713	756	COMPOSITE_FRACMUX(MCLK_I2S2_FRACDIV, "mclk_i2s2_fracdiv", "mclk_i2s2_div", CLK_SET_RATE_PARENT,
714	757	RV1126_CLKSEL_CON(34), 0,
715	758	RV1126_CLKGATE_CON(10), 7, GFLAGS,
716		- &rv1126_i2s2_fracmux, RV1126_FRAC_MAX_PRATE),
	759	+ &rv1126_i2s2_fracmux),
717	760	GATE(MCLK_I2S2, "mclk_i2s2", "mclk_i2s2_mux", 0,
718	761	RV1126_CLKGATE_CON(10), 8, GFLAGS),
719	762	COMPOSITE_NODIV(MCLK_I2S2_OUT2IO, "mclk_i2s2_out2io", mux_i2s2_out2io_p, CLK_SET_RATE_PARENT,
..	..	@@ -734,7 +777,7 @@
734	777	COMPOSITE_FRACMUX(SCLK_AUDPWM_FRACDIV, "sclk_audpwm_fracdiv", "sclk_audpwm_div", CLK_SET_RATE_PARENT,
735	778	RV1126_CLKSEL_CON(37), 0,
736	779	RV1126_CLKGATE_CON(10), 14, GFLAGS,
737		- &rv1126_audpwm_fracmux, RV1126_FRAC_MAX_PRATE),
	780	+ &rv1126_audpwm_fracmux),
738	781	GATE(SCLK_AUDPWM, "sclk_audpwm", "mclk_audpwm_mux", 0,
739	782	RV1126_CLKGATE_CON(10), 15, GFLAGS),
740	783
..	..	@@ -770,18 +813,49 @@
770	813	* Clock-Architecture Diagram 8
771	814	*/
772	815	/* PD_VDPU */
	816	+#if IS_ENABLED(CONFIG_ROCKCHIP_MPP_VDPU2) \|\| IS_ENABLED(CONFIG_ROCKCHIP_MPP_RKVDEC)
	817	+ COMPOSITE(ACLK_PDVDEC, "aclk_pdvdec", mux_cpll_hpll_gpll_p, CLK_IS_CRITICAL,
	818	+ RV1126_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
	819	+ RV1126_CLKGATE_CON(13), 0, GFLAGS),
	820	+ COMPOSITE_NOMUX(HCLK_PDVDEC, "hclk_pdvdec", "aclk_pdvdec", CLK_IS_CRITICAL,
	821	+ RV1126_CLKSEL_CON(41), 8, 5, DFLAGS,
	822	+ RV1126_CLKGATE_CON(13), 4, GFLAGS),
	823	+ GATE(0, "aclk_pdvdec_niu", "aclk_pdvdec", CLK_IS_CRITICAL,
	824	+ RV1126_CLKGATE_CON(13), 5, GFLAGS),
	825	+ GATE(0, "hclk_pdvdec_niu", "hclk_pdvdec", CLK_IS_CRITICAL,
	826	+ RV1126_CLKGATE_CON(13), 6, GFLAGS),
	827	+ COMPOSITE(ACLK_PDJPEG, "aclk_pdjpeg", mux_cpll_hpll_gpll_p, CLK_IS_CRITICAL,
	828	+ RV1126_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5, DFLAGS,
	829	+ RV1126_CLKGATE_CON(13), 9, GFLAGS),
	830	+ COMPOSITE_NOMUX(HCLK_PDJPEG, "hclk_pdjpeg", "aclk_pdjpeg", CLK_IS_CRITICAL,
	831	+ RV1126_CLKSEL_CON(44), 8, 5, DFLAGS,
	832	+ RV1126_CLKGATE_CON(13), 10, GFLAGS),
	833	+ GATE(0, "aclk_pdjpeg_niu", "aclk_pdjpeg", CLK_IS_CRITICAL,
	834	+ RV1126_CLKGATE_CON(13), 11, GFLAGS),
	835	+ GATE(0, "hclk_pdjpeg_niu", "hclk_pdjpeg", CLK_IS_CRITICAL,
	836	+ RV1126_CLKGATE_CON(13), 12, GFLAGS),
	837	+#else
773	838	COMPOSITE(ACLK_PDVDEC, "aclk_pdvdec", mux_cpll_hpll_gpll_p, 0,
774	839	RV1126_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
775	840	RV1126_CLKGATE_CON(13), 0, GFLAGS),
776	841	COMPOSITE_NOMUX(HCLK_PDVDEC, "hclk_pdvdec", "aclk_pdvdec", 0,
777	842	RV1126_CLKSEL_CON(41), 8, 5, DFLAGS,
778	843	RV1126_CLKGATE_CON(13), 4, GFLAGS),
	844	+ GATE(0, "aclk_pdvdec_niu", "aclk_pdvdec", CLK_IGNORE_UNUSED,
	845	+ RV1126_CLKGATE_CON(13), 5, GFLAGS),
	846	+ GATE(0, "hclk_pdvdec_niu", "hclk_pdvdec", CLK_IGNORE_UNUSED,
	847	+ RV1126_CLKGATE_CON(13), 6, GFLAGS),
779	848	COMPOSITE(ACLK_PDJPEG, "aclk_pdjpeg", mux_cpll_hpll_gpll_p, 0,
780	849	RV1126_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5, DFLAGS,
781	850	RV1126_CLKGATE_CON(13), 9, GFLAGS),
782	851	COMPOSITE_NOMUX(HCLK_PDJPEG, "hclk_pdjpeg", "aclk_pdjpeg", 0,
783	852	RV1126_CLKSEL_CON(44), 8, 5, DFLAGS,
784	853	RV1126_CLKGATE_CON(13), 10, GFLAGS),
	854	+ GATE(0, "aclk_pdjpeg_niu", "aclk_pdjpeg", CLK_IGNORE_UNUSED,
	855	+ RV1126_CLKGATE_CON(13), 11, GFLAGS),
	856	+ GATE(0, "hclk_pdjpeg_niu", "hclk_pdjpeg", CLK_IGNORE_UNUSED,
	857	+ RV1126_CLKGATE_CON(13), 12, GFLAGS),
	858	+#endif
785	859	GATE(ACLK_VDEC, "aclk_vdec", "aclk_pdvdec", 0,
786	860	RV1126_CLKGATE_CON(13), 7, GFLAGS),
787	861	GATE(HCLK_VDEC, "hclk_vdec", "hclk_pdvdec", 0,
..	..	@@ -830,7 +904,7 @@
830	904	COMPOSITE_FRACMUX(DCLK_VOP_FRACDIV, "dclk_vop_fracdiv", "dclk_vop_div", CLK_SET_RATE_PARENT,
831	905	RV1126_CLKSEL_CON(48), 0,
832	906	RV1126_CLKGATE_CON(14), 12, GFLAGS,
833		- &rv1126_dclk_vop_fracmux, RV1126_FRAC_MAX_PRATE),
	907	+ &rv1126_dclk_vop_fracmux),
834	908	GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0,
835	909	RV1126_CLKGATE_CON(14), 13, GFLAGS),
836	910	GATE(PCLK_DSIHOST, "pclk_dsihost", "pclk_pdvo", 0,
..	..	@@ -847,10 +921,13 @@
847	921	* Clock-Architecture Diagram 10
848	922	*/
849	923	/* PD_VI */
850		- COMPOSITE_BROTHER(ACLK_PDVI_DIV, "aclk_pdvi_div", mux_cpll_gpll_hpll_p, 0,
	924	+ COMPOSITE(ACLK_PDVI_DIV, "aclk_pdvi_div", mux_cpll_gpll_hpll_p, 0,
851	925	RV1126_CLKSEL_CON(49), 6, 2, MFLAGS, 0, 5, DFLAGS,
852		- RV1126_CLKGATE_CON(15), 0, GFLAGS,
853		- &rv1126_aclk_pdvi_np5),
	926	+ RV1126_CLKGATE_CON(15), 0, GFLAGS),
	927	+ COMPOSITE_HALFDIV_OFFSET(ACLK_PDVI_NP5, "aclk_pdvi_np5", mux_cpll_gpll_hpll_p, 0,
	928	+ RV1126_CLKSEL_CON(49), 6, 2, MFLAGS,
	929	+ RV1126_CLKSEL_CON(76), 0, 5, DFLAGS,
	930	+ RV1126_CLKGATE_CON(16), 13, GFLAGS),
854	931	MUX(ACLK_PDVI, "aclk_pdvi", mux_aclk_pdvi_p, CLK_SET_RATE_PARENT \| CLK_OPS_PARENT_ENABLE,
855	932	RV1126_CLKSEL_CON(76), 5, 1, MFLAGS),
856	933	COMPOSITE_NOMUX(HCLK_PDVI, "hclk_pdvi", "aclk_pdvi", 0,
..	..	@@ -863,10 +940,13 @@
863	940	RV1126_CLKGATE_CON(15), 6, GFLAGS),
864	941	GATE(HCLK_ISP, "hclk_isp", "hclk_pdvi", 0,
865	942	RV1126_CLKGATE_CON(15), 7, GFLAGS),
866		- COMPOSITE_BROTHER(CLK_ISP_DIV, "clk_isp_div", mux_gpll_cpll_hpll_p, 0,
	943	+ COMPOSITE(CLK_ISP_DIV, "clk_isp_div", mux_gpll_cpll_hpll_p, 0,
867	944	RV1126_CLKSEL_CON(50), 6, 2, MFLAGS, 0, 5, DFLAGS,
868		- RV1126_CLKGATE_CON(15), 8, GFLAGS,
869		- &rv1126_clk_isp_np5),
	945	+ RV1126_CLKGATE_CON(15), 8, GFLAGS),
	946	+ COMPOSITE_HALFDIV_OFFSET(CLK_ISP_NP5, "clk_isp_np5", mux_gpll_cpll_hpll_p, 0,
	947	+ RV1126_CLKSEL_CON(50), 6, 2, MFLAGS,
	948	+ RV1126_CLKSEL_CON(76), 8, 5, DFLAGS,
	949	+ RV1126_CLKGATE_CON(16), 14, GFLAGS),
870	950	MUX(CLK_ISP, "clk_isp", mux_clk_isp_p, CLK_SET_RATE_PARENT \| CLK_OPS_PARENT_ENABLE,
871	951	RV1126_CLKSEL_CON(76), 13, 1, MFLAGS),
872	952	GATE(ACLK_CIF, "aclk_cif", "aclk_pdvi", 0,
..	..	@@ -882,7 +962,7 @@
882	962	COMPOSITE_FRACMUX(CLK_CIF_OUT_FRACDIV, "clk_cif_out2io_fracdiv", "clk_cif_out2io_div", CLK_SET_RATE_PARENT,
883	963	RV1126_CLKSEL_CON(52), 0,
884	964	RV1126_CLKGATE_CON(15), 13, GFLAGS,
885		- &rv1126_cif_out2io_fracmux, RV1126_FRAC_MAX_PRATE),
	965	+ &rv1126_cif_out2io_fracmux),
886	966	GATE(CLK_CIF_OUT, "clk_cif_out2io", "clk_cif_out2io_mux", 0,
887	967	RV1126_CLKGATE_CON(15), 14, GFLAGS),
888	968	COMPOSITE(CLK_MIPICSI_OUT_DIV, "clk_mipicsi_out2io_div", mux_gpll_usb480m_p, 0,
..	..	@@ -891,7 +971,7 @@
891	971	COMPOSITE_FRACMUX(CLK_MIPICSI_OUT_FRACDIV, "clk_mipicsi_out2io_fracdiv", "clk_mipicsi_out2io_div", CLK_SET_RATE_PARENT,
892	972	RV1126_CLKSEL_CON(74), 0,
893	973	RV1126_CLKGATE_CON(23), 6, GFLAGS,
894		- &rv1126_mipicsi_out2io_fracmux, RV1126_CSIOUT_FRAC_MAX_PRATE),
	974	+ &rv1126_mipicsi_out2io_fracmux),
895	975	GATE(CLK_MIPICSI_OUT, "clk_mipicsi_out2io", "clk_mipicsi_out2io_mux", 0,
896	976	RV1126_CLKGATE_CON(23), 7, GFLAGS),
897	977	GATE(PCLK_CSIHOST, "pclk_csihost", "pclk_pdvi", 0,
..	..	@@ -908,10 +988,13 @@
908	988	* Clock-Architecture Diagram 11
909	989	*/
910	990	/* PD_ISPP */
911		- COMPOSITE_BROTHER(ACLK_PDISPP_DIV, "aclk_pdispp_div", mux_cpll_gpll_hpll_p, 0,
	991	+ COMPOSITE(ACLK_PDISPP_DIV, "aclk_pdispp_div", mux_cpll_gpll_hpll_p, 0,
912	992	RV1126_CLKSEL_CON(68), 6, 2, MFLAGS, 0, 5, DFLAGS,
913		- RV1126_CLKGATE_CON(16), 0, GFLAGS,
914		- &rv1126_aclk_pdispp_np5),
	993	+ RV1126_CLKGATE_CON(16), 0, GFLAGS),
	994	+ COMPOSITE_HALFDIV_OFFSET(ACLK_PDISPP_NP5, "aclk_pdispp_np5", mux_cpll_gpll_hpll_p, 0,
	995	+ RV1126_CLKSEL_CON(68), 6, 2, MFLAGS,
	996	+ RV1126_CLKSEL_CON(77), 0, 5, DFLAGS,
	997	+ RV1126_CLKGATE_CON(16), 8, GFLAGS),
915	998	MUX(ACLK_PDISPP, "aclk_pdispp", mux_aclk_pdispp_p, CLK_SET_RATE_PARENT \| CLK_OPS_PARENT_ENABLE,
916	999	RV1126_CLKSEL_CON(77), 5, 1, MFLAGS),
917	1000	COMPOSITE_NOMUX(HCLK_PDISPP, "hclk_pdispp", "aclk_pdispp", 0,
..	..	@@ -921,10 +1004,13 @@
921	1004	RV1126_CLKGATE_CON(16), 4, GFLAGS),
922	1005	GATE(HCLK_ISPP, "hclk_ispp", "hclk_pdispp", 0,
923	1006	RV1126_CLKGATE_CON(16), 5, GFLAGS),
924		- COMPOSITE_BROTHER(CLK_ISPP_DIV, "clk_ispp_div", mux_cpll_gpll_hpll_p, 0,
	1007	+ COMPOSITE(CLK_ISPP_DIV, "clk_ispp_div", mux_cpll_gpll_hpll_p, 0,
925	1008	RV1126_CLKSEL_CON(69), 6, 2, MFLAGS, 0, 5, DFLAGS,
926		- RV1126_CLKGATE_CON(16), 6, GFLAGS,
927		- &rv1126_clk_ispp_np5),
	1009	+ RV1126_CLKGATE_CON(16), 6, GFLAGS),
	1010	+ COMPOSITE_HALFDIV_OFFSET(CLK_ISPP_NP5, "clk_ispp_np5", mux_cpll_gpll_hpll_p, 0,
	1011	+ RV1126_CLKSEL_CON(69), 6, 2, MFLAGS,
	1012	+ RV1126_CLKSEL_CON(77), 8, 5, DFLAGS,
	1013	+ RV1126_CLKGATE_CON(16), 7, GFLAGS),
928	1014	MUX(CLK_ISPP, "clk_ispp", mux_clk_ispp_p, CLK_SET_RATE_PARENT \| CLK_OPS_PARENT_ENABLE,
929	1015	RV1126_CLKSEL_CON(77), 13, 1, MFLAGS),
930	1016
..	..	@@ -932,10 +1018,10 @@
932	1018	* Clock-Architecture Diagram 12
933	1019	*/
934	1020	/* PD_PHP */
935		- COMPOSITE(ACLK_PDPHP, "aclk_pdphp", mux_gpll_cpll_p, CLK_IGNORE_UNUSED,
	1021	+ COMPOSITE(ACLK_PDPHP, "aclk_pdphp", mux_gpll_cpll_p, CLK_IS_CRITICAL,
936	1022	RV1126_CLKSEL_CON(53), 7, 1, MFLAGS, 0, 5, DFLAGS,
937	1023	RV1126_CLKGATE_CON(17), 0, GFLAGS),
938		- COMPOSITE_NOMUX(HCLK_PDPHP, "hclk_pdphp", "gpll", CLK_IGNORE_UNUSED,
	1024	+ COMPOSITE_NOMUX(HCLK_PDPHP, "hclk_pdphp", "gpll", CLK_IS_CRITICAL,
939	1025	RV1126_CLKSEL_CON(53), 8, 5, DFLAGS,
940	1026	RV1126_CLKGATE_CON(17), 1, GFLAGS),
941	1027	/* PD_SDCARD */
..	..	@@ -992,9 +1078,15 @@
992	1078	RV1126_CLKGATE_CON(19), 4, GFLAGS),
993	1079	GATE(HCLK_USBHOST_ARB, "hclk_usbhost_arb", "hclk_pdusb", 0,
994	1080	RV1126_CLKGATE_CON(19), 5, GFLAGS),
	1081	+#if IS_ENABLED(CONFIG_USB_EHCI_HCD_PLATFORM) \|\| IS_ENABLED(CONFIG_USB_OHCI_HCD_PLATFORM)
	1082	+ COMPOSITE(CLK_USBHOST_UTMI_OHCI, "clk_usbhost_utmi_ohci", mux_usb480m_gpll_p, CLK_IS_CRITICAL,
	1083	+ RV1126_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 5, DFLAGS,
	1084	+ RV1126_CLKGATE_CON(19), 6, GFLAGS),
	1085	+#else
995	1086	COMPOSITE(CLK_USBHOST_UTMI_OHCI, "clk_usbhost_utmi_ohci", mux_usb480m_gpll_p, 0,
996	1087	RV1126_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 5, DFLAGS,
997	1088	RV1126_CLKGATE_CON(19), 6, GFLAGS),
	1089	+#endif
998	1090	GATE(ACLK_USBOTG, "aclk_usbotg", "aclk_pdusb", 0,
999	1091	RV1126_CLKGATE_CON(19), 7, GFLAGS),
1000	1092	GATE(CLK_USBOTG_REF, "clk_usbotg_ref", "xin24m", 0,
..	..	@@ -1053,10 +1145,12 @@
1053	1145	* Clock-Architecture Diagram 14
1054	1146	*/
1055	1147	/* PD_NPU */
1056		- COMPOSITE_BROTHER(ACLK_PDNPU_DIV, "aclk_pdnpu_div", mux_gpll_cpll_apll_hpll_p, 0,
	1148	+ COMPOSITE(ACLK_PDNPU_DIV, "aclk_pdnpu_div", mux_gpll_cpll_apll_hpll_p, 0,
1057	1149	RV1126_CLKSEL_CON(65), 8, 2, MFLAGS, 0, 4, DFLAGS,
1058		- RV1126_CLKGATE_CON(22), 0, GFLAGS,
1059		- &rv1126_aclk_pdnpu_npu5),
	1150	+ RV1126_CLKGATE_CON(22), 0, GFLAGS),
	1151	+ COMPOSITE_HALFDIV(ACLK_PDNPU_NP5, "aclk_pdnpu_np5", mux_gpll_cpll_apll_hpll_p, 0,
	1152	+ RV1126_CLKSEL_CON(65), 8, 2, MFLAGS, 4, 4, DFLAGS,
	1153	+ RV1126_CLKGATE_CON(22), 1, GFLAGS),
1060	1154	MUX(ACLK_PDNPU, "aclk_pdnpu", mux_aclk_pdnpu_p, CLK_SET_RATE_PARENT \| CLK_OPS_PARENT_ENABLE,
1061	1155	RV1126_CLKSEL_CON(65), 12, 1, MFLAGS),
1062	1156	COMPOSITE_NOMUX(HCLK_PDNPU, "hclk_pdnpu", "gpll", 0,
..	..	@@ -1069,10 +1163,12 @@
1069	1163	RV1126_CLKGATE_CON(22), 7, GFLAGS),
1070	1164	GATE(HCLK_NPU, "hclk_npu", "hclk_pdnpu", 0,
1071	1165	RV1126_CLKGATE_CON(22), 8, GFLAGS),
1072		- COMPOSITE_BROTHER(CLK_NPU_DIV, "clk_npu_div", mux_gpll_cpll_apll_hpll_p, 0,
	1166	+ COMPOSITE(CLK_NPU_DIV, "clk_npu_div", mux_gpll_cpll_apll_hpll_p, 0,
1073	1167	RV1126_CLKSEL_CON(67), 8, 2, MFLAGS, 0, 4, DFLAGS,
1074		- RV1126_CLKGATE_CON(22), 9, GFLAGS,
1075		- &rv1126_clk_npu_np5),
	1168	+ RV1126_CLKGATE_CON(22), 9, GFLAGS),
	1169	+ COMPOSITE_HALFDIV(CLK_NPU_NP5, "clk_npu_np5", mux_gpll_cpll_apll_hpll_p, 0,
	1170	+ RV1126_CLKSEL_CON(67), 8, 2, MFLAGS, 4, 4, DFLAGS,
	1171	+ RV1126_CLKGATE_CON(22), 10, GFLAGS),
1076	1172	MUX(CLK_CORE_NPU, "clk_core_npu", mux_clk_npu_p, CLK_SET_RATE_PARENT \| CLK_OPS_PARENT_ENABLE,
1077	1173	RV1126_CLKSEL_CON(67), 12, 1, MFLAGS),
1078	1174	GATE(CLK_CORE_NPUPVTM, "clk_core_npupvtm", "clk_core_npu", CLK_IGNORE_UNUSED,
..	..	@@ -1085,7 +1181,7 @@
1085	1181	/*
1086	1182	* Clock-Architecture Diagram 15
1087	1183	*/
1088		- GATE(PCLK_PDTOP, "pclk_pdtop", "pclk_pdbus", CLK_IGNORE_UNUSED,
	1184	+ GATE(PCLK_PDTOP, "pclk_pdtop", "pclk_pdbus", CLK_IS_CRITICAL,
1089	1185	RV1126_CLKGATE_CON(23), 8, GFLAGS),
1090	1186	GATE(PCLK_DSIPHY, "pclk_dsiphy", "pclk_pdtop", 0,
1091	1187	RV1126_CLKGATE_CON(23), 4, GFLAGS),
..	..	@@ -1103,46 +1199,102 @@
1103	1199	* Clock-Architecture Diagram 3
1104	1200	*/
1105	1201	/* PD_CORE */
1106		- COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
	1202	+ COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IS_CRITICAL,
1107	1203	RV1126_CLKSEL_CON(1), 4, 4, DFLAGS \| CLK_DIVIDER_READ_ONLY,
1108	1204	RV1126_CLKGATE_CON(0), 2, GFLAGS),
1109	1205	GATE(0, "pclk_dbg_daplite", "pclk_dbg", CLK_IGNORE_UNUSED,
1110	1206	RV1126_CLKGATE_CON(0), 5, GFLAGS),
1111	1207	GATE(0, "clk_a7_jtag", "clk_jtag_ori", CLK_IGNORE_UNUSED,
1112	1208	RV1126_CLKGATE_CON(0), 9, GFLAGS),
	1209	+ GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED,
	1210	+ RV1126_CLKGATE_CON(0), 3, GFLAGS),
	1211	+ GATE(0, "pclk_dbg_niu", "pclk_dbg", CLK_IGNORE_UNUSED,
	1212	+ RV1126_CLKGATE_CON(0), 4, GFLAGS),
1113	1213	/*
1114	1214	* Clock-Architecture Diagram 4
1115	1215	*/
1116	1216	/* PD_BUS */
	1217	+ GATE(0, "aclk_pdbus_hold_niu1", "aclk_pdbus", CLK_IGNORE_UNUSED,
	1218	+ RV1126_CLKGATE_CON(2), 10, GFLAGS),
	1219	+ GATE(0, "aclk_pdbus_niu1", "aclk_pdbus", CLK_IGNORE_UNUSED,
	1220	+ RV1126_CLKGATE_CON(2), 3, GFLAGS),
	1221	+ GATE(0, "hclk_pdbus_niu1", "hclk_pdbus", CLK_IGNORE_UNUSED,
	1222	+ RV1126_CLKGATE_CON(2), 4, GFLAGS),
	1223	+ GATE(0, "pclk_pdbus_niu1", "pclk_pdbus", CLK_IGNORE_UNUSED,
	1224	+ RV1126_CLKGATE_CON(2), 5, GFLAGS),
	1225	+ GATE(0, "aclk_pdbus_niu2", "aclk_pdbus", CLK_IGNORE_UNUSED,
	1226	+ RV1126_CLKGATE_CON(2), 6, GFLAGS),
	1227	+ GATE(0, "hclk_pdbus_niu2", "hclk_pdbus", CLK_IGNORE_UNUSED,
	1228	+ RV1126_CLKGATE_CON(2), 7, GFLAGS),
	1229	+ GATE(0, "aclk_pdbus_niu3", "aclk_pdbus", CLK_IGNORE_UNUSED,
	1230	+ RV1126_CLKGATE_CON(2), 8, GFLAGS),
	1231	+ GATE(0, "hclk_pdbus_niu3", "hclk_pdbus", CLK_IGNORE_UNUSED,
	1232	+ RV1126_CLKGATE_CON(2), 9, GFLAGS),
	1233	+ GATE(0, "pclk_grf", "pclk_pdbus", CLK_IGNORE_UNUSED,
	1234	+ RV1126_CLKGATE_CON(6), 15, GFLAGS),
	1235	+ GATE(0, "pclk_sgrf", "pclk_pdbus", CLK_IGNORE_UNUSED,
	1236	+ RV1126_CLKGATE_CON(8), 4, GFLAGS),
	1237	+ GATE(0, "aclk_sysram", "hclk_pdbus", CLK_IGNORE_UNUSED,
	1238	+ RV1126_CLKGATE_CON(3), 9, GFLAGS),
	1239	+ GATE(0, "pclk_intmux", "pclk_pdbus", CLK_IGNORE_UNUSED,
	1240	+ RV1126_CLKGATE_CON(7), 14, GFLAGS),
1117	1241
1118	1242	/*
1119	1243	* Clock-Architecture Diagram 5
1120	1244	*/
1121	1245	/* PD_CRYPTO */
	1246	+ GATE(0, "aclk_pdcrypto_niu", "aclk_pdcrypto", CLK_IGNORE_UNUSED,
	1247	+ RV1126_CLKGATE_CON(4), 13, GFLAGS),
	1248	+ GATE(0, "hclk_pdcrypto_niu", "hclk_pdcrypto", CLK_IGNORE_UNUSED,
	1249	+ RV1126_CLKGATE_CON(4), 14, GFLAGS),
1122	1250
1123	1251	/*
1124	1252	* Clock-Architecture Diagram 6
1125	1253	*/
1126	1254	/* PD_AUDIO */
	1255	+ GATE(0, "hclk_pdaudio_niu", "hclk_pdaudio", CLK_IGNORE_UNUSED,
	1256	+ RV1126_CLKGATE_CON(9), 2, GFLAGS),
	1257	+ GATE(0, "pclk_pdaudio_niu", "hclk_pdaudio", CLK_IGNORE_UNUSED,
	1258	+ RV1126_CLKGATE_CON(9), 3, GFLAGS),
1127	1259
1128	1260	/*
1129	1261	* Clock-Architecture Diagram 7
1130	1262	*/
1131	1263	/* PD_VEPU */
	1264	+ GATE(0, "aclk_pdvepu_niu", "aclk_pdvepu", CLK_IGNORE_UNUSED,
	1265	+ RV1126_CLKGATE_CON(12), 3, GFLAGS),
	1266	+ GATE(0, "hclk_pdvepu_niu", "hclk_pdvepu", CLK_IGNORE_UNUSED,
	1267	+ RV1126_CLKGATE_CON(12), 4, GFLAGS),
1132	1268
1133	1269	/*
1134	1270	* Clock-Architecture Diagram 9
1135	1271	*/
1136	1272	/* PD_VO */
	1273	+ GATE(0, "aclk_pdvo_niu", "aclk_pdvo", CLK_IGNORE_UNUSED,
	1274	+ RV1126_CLKGATE_CON(14), 3, GFLAGS),
	1275	+ GATE(0, "hclk_pdvo_niu", "hclk_pdvo", CLK_IGNORE_UNUSED,
	1276	+ RV1126_CLKGATE_CON(14), 4, GFLAGS),
	1277	+ GATE(0, "pclk_pdvo_niu", "pclk_pdvo", CLK_IGNORE_UNUSED,
	1278	+ RV1126_CLKGATE_CON(14), 5, GFLAGS),
1137	1279
1138	1280	/*
1139	1281	* Clock-Architecture Diagram 10
1140	1282	*/
1141	1283	/* PD_VI */
	1284	+ GATE(0, "aclk_pdvi_niu", "aclk_pdvi", CLK_IGNORE_UNUSED,
	1285	+ RV1126_CLKGATE_CON(15), 3, GFLAGS),
	1286	+ GATE(0, "hclk_pdvi_niu", "hclk_pdvi", CLK_IGNORE_UNUSED,
	1287	+ RV1126_CLKGATE_CON(15), 4, GFLAGS),
	1288	+ GATE(0, "pclk_pdvi_niu", "pclk_pdvi", CLK_IGNORE_UNUSED,
	1289	+ RV1126_CLKGATE_CON(15), 5, GFLAGS),
1142	1290	/*
1143	1291	* Clock-Architecture Diagram 11
1144	1292	*/
1145	1293	/* PD_ISPP */
	1294	+ GATE(0, "aclk_pdispp_niu", "aclk_pdispp", CLK_IGNORE_UNUSED,
	1295	+ RV1126_CLKGATE_CON(16), 2, GFLAGS),
	1296	+ GATE(0, "hclk_pdispp_niu", "hclk_pdispp", CLK_IGNORE_UNUSED,
	1297	+ RV1126_CLKGATE_CON(16), 3, GFLAGS),
1146	1298
1147	1299	/*
1148	1300	* Clock-Architecture Diagram 12
..	..	@@ -1152,32 +1304,49 @@
1152	1304	RV1126_CLKGATE_CON(17), 2, GFLAGS),
1153	1305	GATE(0, "hclk_pdphpmid", "hclk_pdphp", CLK_IGNORE_UNUSED,
1154	1306	RV1126_CLKGATE_CON(17), 3, GFLAGS),
	1307	+ GATE(0, "aclk_pdphpmid_niu", "aclk_pdphpmid", CLK_IGNORE_UNUSED,
	1308	+ RV1126_CLKGATE_CON(17), 4, GFLAGS),
	1309	+ GATE(0, "hclk_pdphpmid_niu", "hclk_pdphpmid", CLK_IGNORE_UNUSED,
	1310	+ RV1126_CLKGATE_CON(17), 5, GFLAGS),
1155	1311
1156	1312	/* PD_SDCARD */
	1313	+ GATE(0, "hclk_pdsdmmc_niu", "hclk_pdsdmmc", CLK_IGNORE_UNUSED,
	1314	+ RV1126_CLKGATE_CON(17), 7, GFLAGS),
1157	1315
1158	1316	/* PD_SDIO */
	1317	+ GATE(0, "hclk_pdsdio_niu", "hclk_pdsdio", CLK_IGNORE_UNUSED,
	1318	+ RV1126_CLKGATE_CON(17), 9, GFLAGS),
1159	1319
1160	1320	/* PD_NVM */
	1321	+ GATE(0, "hclk_pdnvm_niu", "hclk_pdnvm", CLK_IGNORE_UNUSED,
	1322	+ RV1126_CLKGATE_CON(18), 3, GFLAGS),
1161	1323
1162	1324	/* PD_USB */
	1325	+ GATE(0, "aclk_pdusb_niu", "aclk_pdusb", CLK_IGNORE_UNUSED,
	1326	+ RV1126_CLKGATE_CON(19), 2, GFLAGS),
	1327	+ GATE(0, "hclk_pdusb_niu", "hclk_pdusb", CLK_IGNORE_UNUSED,
	1328	+ RV1126_CLKGATE_CON(19), 3, GFLAGS),
1163	1329
1164	1330	/* PD_GMAC */
	1331	+ GATE(0, "aclk_pdgmac_niu", "aclk_pdgmac", CLK_IGNORE_UNUSED,
	1332	+ RV1126_CLKGATE_CON(20), 2, GFLAGS),
	1333	+ GATE(0, "pclk_pdgmac_niu", "pclk_pdgmac", CLK_IGNORE_UNUSED,
	1334	+ RV1126_CLKGATE_CON(20), 3, GFLAGS),
1165	1335
1166	1336	/*
1167	1337	* Clock-Architecture Diagram 13
1168	1338	*/
1169	1339	/* PD_DDR */
1170		- COMPOSITE_NOMUX(0, "pclk_pdddr_pre", "gpll", CLK_IGNORE_UNUSED,
	1340	+ COMPOSITE_NOMUX(0, "pclk_pdddr_pre", "gpll", CLK_IS_CRITICAL,
1171	1341	RV1126_CLKSEL_CON(64), 0, 5, DFLAGS,
1172	1342	RV1126_CLKGATE_CON(21), 0, GFLAGS),
1173		- GATE(PCLK_PDDDR, "pclk_pdddr", "pclk_pdddr_pre", CLK_IGNORE_UNUSED,
	1343	+ GATE(PCLK_PDDDR, "pclk_pdddr", "pclk_pdddr_pre", CLK_IS_CRITICAL,
1174	1344	RV1126_CLKGATE_CON(21), 15, GFLAGS),
1175	1345	GATE(0, "pclk_ddr_msch", "pclk_pdddr", CLK_IGNORE_UNUSED,
1176	1346	RV1126_CLKGATE_CON(21), 6, GFLAGS),
1177		- COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_dpll_gpll_p,
1178		- CLK_IGNORE_UNUSED, RV1126_CLKSEL_CON(64), 15, 1, 8, 5,
1179		- ROCKCHIP_DDRCLK_SIP_V2),
1180		- COMPOSITE(CLK_DDRPHY, "clk_ddrphy", mux_dpll_gpll_p, CLK_IGNORE_UNUSED,
	1347	+ COMPOSITE_NOGATE(SCLK_DDRCLK, "sclk_ddrc", mux_dpll_gpll_p, CLK_IS_CRITICAL,
	1348	+ RV1126_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS),
	1349	+ COMPOSITE(CLK_DDRPHY, "clk_ddrphy", mux_dpll_gpll_p, CLK_IS_CRITICAL,
1181	1350	RV1126_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS,
1182	1351	RV1126_CLKGATE_CON(21), 8, GFLAGS),
1183	1352	GATE(0, "clk1x_phy", "clk_ddrphy", CLK_IGNORE_UNUSED,
..	..	@@ -1207,43 +1376,26 @@
1207	1376	* Clock-Architecture Diagram 14
1208	1377	*/
1209	1378	/* PD_NPU */
	1379	+ GATE(0, "aclk_pdnpu_niu", "aclk_pdnpu", CLK_IGNORE_UNUSED,
	1380	+ RV1126_CLKGATE_CON(22), 4, GFLAGS),
	1381	+ GATE(0, "hclk_pdnpu_niu", "hclk_pdnpu", CLK_IGNORE_UNUSED,
	1382	+ RV1126_CLKGATE_CON(22), 5, GFLAGS),
	1383	+ GATE(0, "pclk_pdnpu_niu", "pclk_pdnpu", CLK_IGNORE_UNUSED,
	1384	+ RV1126_CLKGATE_CON(22), 6, GFLAGS),
	1385	+
1210	1386	/*
1211	1387	* Clock-Architecture Diagram 15
1212	1388	*/
	1389	+ GATE(0, "pclk_topniu", "pclk_pdtop", CLK_IGNORE_UNUSED,
	1390	+ RV1126_CLKGATE_CON(23), 9, GFLAGS),
	1391	+ GATE(PCLK_TOPCRU, "pclk_topcru", "pclk_pdtop", CLK_IGNORE_UNUSED,
	1392	+ RV1126_CLKGATE_CON(23), 10, GFLAGS),
	1393	+ GATE(PCLK_TOPGRF, "pclk_topgrf", "pclk_pdtop", CLK_IGNORE_UNUSED,
	1394	+ RV1126_CLKGATE_CON(23), 11, GFLAGS),
1213	1395	GATE(PCLK_CPUEMADET, "pclk_cpuemadet", "pclk_pdtop", CLK_IGNORE_UNUSED,
1214	1396	RV1126_CLKGATE_CON(23), 12, GFLAGS),
1215	1397	GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_pdtop", CLK_IGNORE_UNUSED,
1216	1398	RV1126_CLKGATE_CON(23), 0, GFLAGS),
1217		-#endif
1218		-};
1219		-
1220		-static const char *const rv1126_cru_critical_clocks[] __initconst = {
1221		- "gpll",
1222		-#ifndef CONFIG_ROCKCHIP_LOW_PERFORMANCE
1223		- "cpll",
1224		- "hpll",
1225		-#endif
1226		- "armclk",
1227		- "pclk_dbg",
1228		- "pclk_pdpmu",
1229		- "aclk_pdbus",
1230		- "hclk_pdbus",
1231		- "pclk_pdbus",
1232		- "aclk_pdphp",
1233		- "hclk_pdphp",
1234		- "clk_ddrphy",
1235		- "pclk_pdddr",
1236		- "pclk_pdtop",
1237		-#if IS_ENABLED(CONFIG_USB_EHCI_HCD_PLATFORM) \|\| IS_ENABLED(CONFIG_USB_OHCI_HCD_PLATFORM)
1238		- "clk_usbhost_utmi_ohci",
1239		-#endif
1240		-#if IS_ENABLED(CONFIG_ROCKCHIP_MPP_VDPU2) \|\| \
1241		- IS_ENABLED(CONFIG_ROCKCHIP_MPP_RKVDEC) \|\| \
1242		- IS_ENABLED(CONFIG_ROCKCHIP_MPP_VEPU2)
1243		- "aclk_pdjpeg",
1244		- "hclk_pdjpeg",
1245		- "aclk_pdvdec",
1246		- "hclk_pdvdec",
1247	1399	#endif
1248	1400	};
1249	1401
..	..	@@ -1278,6 +1430,7 @@
1278	1430	.notifier_call = rv1126_clk_panic,
1279	1431	};
1280	1432
	1433	+static struct rockchip_clk_provider *pmucru_ctx;
1281	1434	static void __init rv1126_pmu_clk_init(struct device_node *np)
1282	1435	{
1283	1436	struct rockchip_clk_provider *ctx;
..	..	@@ -1308,6 +1461,8 @@
1308	1461	ROCKCHIP_SOFTRST_HIWORD_MASK);
1309	1462
1310	1463	rockchip_clk_of_add_provider(np, ctx);
	1464	+
	1465	+ pmucru_ctx = ctx;
1311	1466	}
1312	1467
1313	1468	CLK_OF_DECLARE(rv1126_cru_pmu, "rockchip,rv1126-pmucru", rv1126_pmu_clk_init);
..	..	@@ -1316,6 +1471,7 @@
1316	1471	{
1317	1472	struct rockchip_clk_provider *ctx;
1318	1473	void __iomem *reg_base;
	1474	+ struct clk cru_clks, pmucru_clks;
1319	1475
1320	1476	reg_base = of_iomap(np, 0);
1321	1477	if (!reg_base) {
..	..	@@ -1331,13 +1487,15 @@
1331	1487	iounmap(reg_base);
1332	1488	return;
1333	1489	}
	1490	+ cru_clks = ctx->clk_data.clks;
	1491	+ pmucru_clks = pmucru_ctx->clk_data.clks;
1334	1492
1335	1493	rockchip_clk_register_plls(ctx, rv1126_pll_clks,
1336	1494	ARRAY_SIZE(rv1126_pll_clks),
1337	1495	RV1126_GRF_SOC_STATUS0);
1338	1496
1339	1497	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
1340		- mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
	1498	+ 3, cru_clks[PLL_APLL], pmucru_clks[PLL_GPLL],
1341	1499	&rv1126_cpuclk_data, rv1126_cpuclk_rates,
1342	1500	ARRAY_SIZE(rv1126_cpuclk_rates));
1343	1501
..	..	@@ -1349,9 +1507,6 @@
1349	1507
1350	1508	rockchip_register_restart_notifier(ctx, RV1126_GLB_SRST_FST, NULL);
1351	1509
1352		- rockchip_clk_protect_critical(rv1126_cru_critical_clocks,
1353		- ARRAY_SIZE(rv1126_cru_critical_clocks));
1354		-
1355	1510	rockchip_clk_of_add_provider(np, ctx);
1356	1511
1357	1512	atomic_notifier_chain_register(&panic_notifier_list,
..	..	@@ -1359,3 +1514,55 @@
1359	1514	}
1360	1515
1361	1516	CLK_OF_DECLARE(rv1126_cru, "rockchip,rv1126-cru", rv1126_clk_init);
	1517	+
	1518	+struct clk_rv1126_inits {
	1519	+ void (inits)(struct device_node np);
	1520	+};
	1521	+
	1522	+static const struct clk_rv1126_inits clk_rv1126_pmu_init = {
	1523	+ .inits = rv1126_pmu_clk_init,
	1524	+};
	1525	+
	1526	+static const struct clk_rv1126_inits clk_rv1126_init = {
	1527	+ .inits = rv1126_clk_init,
	1528	+};
	1529	+
	1530	+static const struct of_device_id clk_rv1126_match_table[] = {
	1531	+ {
	1532	+ .compatible = "rockchip,rv1126-cru",
	1533	+ .data = &clk_rv1126_init,
	1534	+ }, {
	1535	+ .compatible = "rockchip,rv1126-pmucru",
	1536	+ .data = &clk_rv1126_pmu_init,
	1537	+ },
	1538	+ { }
	1539	+};
	1540	+MODULE_DEVICE_TABLE(of, clk_rv1126_match_table);
	1541	+
	1542	+static int __init clk_rv1126_probe(struct platform_device *pdev)
	1543	+{
	1544	+ struct device_node *np = pdev->dev.of_node;
	1545	+ const struct of_device_id *match;
	1546	+ const struct clk_rv1126_inits *init_data;
	1547	+
	1548	+ match = of_match_device(clk_rv1126_match_table, &pdev->dev);
	1549	+ if (!match \|\| !match->data)
	1550	+ return -EINVAL;
	1551	+
	1552	+ init_data = match->data;
	1553	+ if (init_data->inits)
	1554	+ init_data->inits(np);
	1555	+
	1556	+ return 0;
	1557	+}
	1558	+
	1559	+static struct platform_driver clk_rv1126_driver = {
	1560	+ .driver = {
	1561	+ .name = "clk-rv1126",
	1562	+ .of_match_table = clk_rv1126_match_table,
	1563	+ },
	1564	+};
	1565	+builtin_platform_driver_probe(clk_rv1126_driver, clk_rv1126_probe);
	1566	+
	1567	+MODULE_DESCRIPTION("Rockchip RV1126 Clock Driver");
	1568	+MODULE_LICENSE("GPL");