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2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da 
 kernel/drivers/clk/rockchip/clk-rv1108.c
....@@ -1,29 +1,21 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
34  * Author: Shawn Lin <shawn.lin@rock-chips.com>
45  *         Andy Yan <andy.yan@rock-chips.com>
5
- *
6
- * This program is free software; you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License as published by
8
- * the Free Software Foundation; either version 2 of the License, or
9
- * (at your option) any later version.
10
- *
11
- * This program is distributed in the hope that it will be useful,
12
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
- * GNU General Public License for more details.
156  */
167 
178 #include <linux/clk-provider.h>
9
+#include <linux/io.h>
10
+#include <linux/module.h>
1811 #include <linux/of.h>
1912 #include <linux/of_address.h>
13
+#include <linux/of_device.h>
2014 #include <linux/syscore_ops.h>
2115 #include <dt-bindings/clock/rv1108-cru.h>
2216 #include "clk.h"
2317 
2418 #define RV1108_GRF_SOC_STATUS0	0x480
25
-#define RV1108_I2S_FRAC_MAX_RATE	600000000
26
-#define RV1108_UART_FRAC_MAX_RATE	600000000
2719 
2820 enum rv1108_plls {
2921 	apll, dpll, gpll,
....@@ -128,12 +120,10 @@
128120 
129121 PNAME(mux_pll_p)		= { "xin24m", "xin24m"};
130122 PNAME(mux_ddrphy_p)		= { "dpll_ddr", "gpll_ddr", "apll_ddr" };
131
-PNAME(mux_armclk_p)		= { "apll_core", "gpll_core", "dpll_core" };
132123 PNAME(mux_usb480m_pre_p)	= { "usbphy", "xin24m" };
133124 PNAME(mux_hdmiphy_phy_p)	= { "hdmiphy", "xin24m" };
134125 PNAME(mux_dclk_hdmiphy_pre_p)	= { "dclk_hdmiphy_src_gpll", "dclk_hdmiphy_src_dpll" };
135126 PNAME(mux_pll_src_4plls_p)	= { "dpll", "gpll", "hdmiphy", "usb480m" };
136
-PNAME(mux_pll_src_3plls_p)	= { "apll", "gpll", "dpll" };
137127 PNAME(mux_pll_src_2plls_p)	= { "dpll", "gpll" };
138128 PNAME(mux_pll_src_apll_gpll_p)	= { "apll", "gpll" };
139129 PNAME(mux_aclk_peri_src_p)	= { "aclk_peri_src_gpll", "aclk_peri_src_dpll" };
....@@ -221,7 +211,7 @@
221211 	COMPOSITE_NOMUX(ACLK_ENMCORE, "aclkenm_core", "armclk", CLK_IGNORE_UNUSED,
222212 			RV1108_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
223213 			RV1108_CLKGATE_CON(0), 4, GFLAGS),
224
-	GATE(ACLK_CORE, "aclk_core", "aclkenm_core", CLK_IGNORE_UNUSED,
214
+	GATE(ACLK_CORE, "aclk_core", "aclkenm_core", CLK_IS_CRITICAL,
225215 			RV1108_CLKGATE_CON(11), 0, GFLAGS),
226216 	GATE(0, "pclk_dbg", "pclken_dbg", CLK_IGNORE_UNUSED,
227217 			RV1108_CLKGATE_CON(11), 1, GFLAGS),
....@@ -276,10 +266,10 @@
276266 			RV1108_CLKGATE_CON(19), 6, GFLAGS),
277267 
278268 	/* PD_PMU_wrapper */
279
-	COMPOSITE_NOMUX(0, "pmu_24m_ena", "gpll", CLK_IGNORE_UNUSED,
269
+	COMPOSITE_NOMUX(0, "pmu_24m_ena", "gpll", CLK_IS_CRITICAL,
280270 			RV1108_CLKSEL_CON(38), 0, 5, DFLAGS,
281271 			RV1108_CLKGATE_CON(8), 12, GFLAGS),
282
-	GATE(0, "pclk_pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED,
272
+	GATE(0, "pclk_pmu", "pmu_24m_ena", CLK_IS_CRITICAL,
283273 			RV1108_CLKGATE_CON(10), 0, GFLAGS),
284274 	GATE(0, "pclk_intmem1", "pmu_24m_ena", CLK_IGNORE_UNUSED,
285275 			RV1108_CLKGATE_CON(10), 1, GFLAGS),
....@@ -317,7 +307,7 @@
317307 			RV1108_CLKSEL_CON(41), 0, 5, DFLAGS,
318308 			RV1108_CLKGATE_CON(9), 12, GFLAGS),
319309 
320
-	GATE(0, "pclk_acodecphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
310
+	GATE(0, "pclk_acodecphy", "pclk_top_pre", CLK_IS_CRITICAL,
321311 			RV1108_CLKGATE_CON(14), 6, GFLAGS),
322312 	GATE(0, "pclk_usbgrf", "pclk_top_pre", CLK_IGNORE_UNUSED,
323313 			RV1108_CLKGATE_CON(14), 14, GFLAGS),
....@@ -515,7 +505,7 @@
515505 	COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
516506 			RV1108_CLKSEL_CON(8), 0,
517507 			RV1108_CLKGATE_CON(2), 1, GFLAGS,
518
-			&rv1108_i2s0_fracmux, RV1108_I2S_FRAC_MAX_RATE),
508
+			&rv1108_i2s0_fracmux),
519509 	GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
520510 			RV1108_CLKGATE_CON(2), 2, GFLAGS),
521511 	COMPOSITE_NODIV(0, "i2s_out", mux_i2s_out_p, 0,
....@@ -528,7 +518,7 @@
528518 	COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
529519 			RK2928_CLKSEL_CON(9), 0,
530520 			RK2928_CLKGATE_CON(2), 5, GFLAGS,
531
-			&rv1108_i2s1_fracmux, RV1108_I2S_FRAC_MAX_RATE),
521
+			&rv1108_i2s1_fracmux),
532522 	GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
533523 			RV1108_CLKGATE_CON(2), 6, GFLAGS),
534524 
....@@ -538,28 +528,28 @@
538528 	COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
539529 			RV1108_CLKSEL_CON(10), 0,
540530 			RV1108_CLKGATE_CON(2), 9, GFLAGS,
541
-			&rv1108_i2s2_fracmux, RV1108_I2S_FRAC_MAX_RATE),
531
+			&rv1108_i2s2_fracmux),
542532 	GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
543533 			RV1108_CLKGATE_CON(2), 10, GFLAGS),
544534 
545535 	/* PD_BUS */
546
-	GATE(0, "aclk_bus_src_gpll", "gpll", CLK_IGNORE_UNUSED,
536
+	GATE(0, "aclk_bus_src_gpll", "gpll", CLK_IS_CRITICAL,
547537 			RV1108_CLKGATE_CON(1), 0, GFLAGS),
548
-	GATE(0, "aclk_bus_src_apll", "apll", CLK_IGNORE_UNUSED,
538
+	GATE(0, "aclk_bus_src_apll", "apll", CLK_IS_CRITICAL,
549539 			RV1108_CLKGATE_CON(1), 1, GFLAGS),
550
-	GATE(0, "aclk_bus_src_dpll", "dpll", CLK_IGNORE_UNUSED,
540
+	GATE(0, "aclk_bus_src_dpll", "dpll", CLK_IS_CRITICAL,
551541 			RV1108_CLKGATE_CON(1), 2, GFLAGS),
552
-	COMPOSITE_NOGATE(ACLK_PRE, "aclk_bus_pre", mux_aclk_bus_src_p, 0,
542
+	COMPOSITE_NOGATE(ACLK_PRE, "aclk_bus_pre", mux_aclk_bus_src_p, CLK_IS_CRITICAL,
553543 			RV1108_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 5, DFLAGS),
554
-	COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus_pre", "aclk_bus_pre", 0,
544
+	COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus_pre", "aclk_bus_pre", CLK_IS_CRITICAL,
555545 			RV1108_CLKSEL_CON(3), 0, 5, DFLAGS,
556546 			RV1108_CLKGATE_CON(1), 4, GFLAGS),
557
-	COMPOSITE_NOMUX(0, "pclk_bus_pre", "aclk_bus_pre", 0,
547
+	COMPOSITE_NOMUX(0, "pclk_bus_pre", "aclk_bus_pre", CLK_IS_CRITICAL,
558548 			RV1108_CLKSEL_CON(3), 8, 5, DFLAGS,
559549 			RV1108_CLKGATE_CON(1), 5, GFLAGS),
560
-	GATE(PCLK_BUS, "pclk_bus", "pclk_bus_pre", 0,
550
+	GATE(PCLK_BUS, "pclk_bus", "pclk_bus_pre", CLK_IS_CRITICAL,
561551 			RV1108_CLKGATE_CON(1), 6, GFLAGS),
562
-	GATE(0, "pclk_top_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED,
552
+	GATE(0, "pclk_top_pre", "pclk_bus_pre", CLK_IS_CRITICAL,
563553 			RV1108_CLKGATE_CON(1), 7, GFLAGS),
564554 	GATE(0, "pclk_ddr_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED,
565555 			RV1108_CLKGATE_CON(1), 8, GFLAGS),
....@@ -604,15 +594,15 @@
604594 	COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
605595 			RV1108_CLKSEL_CON(16), 0,
606596 			RV1108_CLKGATE_CON(3), 2, GFLAGS,
607
-			&rv1108_uart0_fracmux, RV1108_UART_FRAC_MAX_RATE),
597
+			&rv1108_uart0_fracmux),
608598 	COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
609599 			RV1108_CLKSEL_CON(17), 0,
610600 			RV1108_CLKGATE_CON(3), 4, GFLAGS,
611
-			&rv1108_uart1_fracmux, RV1108_UART_FRAC_MAX_RATE),
601
+			&rv1108_uart1_fracmux),
612602 	COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
613603 			RV1108_CLKSEL_CON(18), 0,
614604 			RV1108_CLKGATE_CON(3), 6, GFLAGS,
615
-			&rv1108_uart2_fracmux, RV1108_UART_FRAC_MAX_RATE),
605
+			&rv1108_uart2_fracmux),
616606 	GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_pre", 0,
617607 			RV1108_CLKGATE_CON(13), 10, GFLAGS),
618608 	GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0,
....@@ -680,7 +670,7 @@
680670 			RV1108_CLKGATE_CON(0), 9, GFLAGS),
681671 	GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
682672 			RV1108_CLKGATE_CON(0), 10, GFLAGS),
683
-	COMPOSITE_NOGATE(0, "clk_ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
673
+	COMPOSITE_NOGATE(0, "clk_ddrphy_src", mux_ddrphy_p, CLK_IS_CRITICAL,
684674 			RV1108_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 3,
685675 			DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
686676 	FACTOR(0, "clk_ddr", "clk_ddrphy_src", 0, 1, 2),
....@@ -688,9 +678,9 @@
688678 			RV1108_CLKGATE_CON(10), 9, GFLAGS),
689679 	GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
690680 			RV1108_CLKGATE_CON(12), 4, GFLAGS),
691
-	GATE(0, "nclk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
681
+	GATE(0, "nclk_ddrupctl", "clk_ddr", CLK_IS_CRITICAL,
692682 			RV1108_CLKGATE_CON(12), 5, GFLAGS),
693
-	GATE(0, "pclk_ddrmon", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
683
+	GATE(0, "pclk_ddrmon", "pclk_ddr_pre", CLK_IS_CRITICAL,
694684 			RV1108_CLKGATE_CON(12), 6, GFLAGS),
695685 	GATE(0, "timer_clk", "xin24m", CLK_IGNORE_UNUSED,
696686 			RV1108_CLKGATE_CON(0), 11, GFLAGS),
....@@ -704,22 +694,22 @@
704694 	 */
705695 
706696 	/* PD_PERI */
707
-	COMPOSITE_NOMUX(0, "pclk_periph_pre", "gpll", 0,
697
+	COMPOSITE_NOMUX(0, "pclk_periph_pre", "gpll", CLK_IS_CRITICAL,
708698 			RV1108_CLKSEL_CON(23), 10, 5, DFLAGS,
709699 			RV1108_CLKGATE_CON(4), 5, GFLAGS),
710
-	GATE(PCLK_PERI, "pclk_periph", "pclk_periph_pre", CLK_IGNORE_UNUSED,
700
+	GATE(PCLK_PERI, "pclk_periph", "pclk_periph_pre", CLK_IS_CRITICAL,
711701 			RV1108_CLKGATE_CON(15), 13, GFLAGS),
712
-	COMPOSITE_NOMUX(0, "hclk_periph_pre", "gpll", 0,
702
+	COMPOSITE_NOMUX(0, "hclk_periph_pre", "gpll", CLK_IS_CRITICAL,
713703 			RV1108_CLKSEL_CON(23), 5, 5, DFLAGS,
714704 			RV1108_CLKGATE_CON(4), 4, GFLAGS),
715
-	GATE(HCLK_PERI, "hclk_periph", "hclk_periph_pre", CLK_IGNORE_UNUSED,
705
+	GATE(HCLK_PERI, "hclk_periph", "hclk_periph_pre", CLK_IS_CRITICAL,
716706 			RV1108_CLKGATE_CON(15), 12, GFLAGS),
717707 
718
-	GATE(0, "aclk_peri_src_dpll", "dpll", CLK_IGNORE_UNUSED,
708
+	GATE(0, "aclk_peri_src_dpll", "dpll", CLK_IS_CRITICAL,
719709 			RV1108_CLKGATE_CON(4), 1, GFLAGS),
720
-	GATE(0, "aclk_peri_src_gpll", "gpll", CLK_IGNORE_UNUSED,
710
+	GATE(0, "aclk_peri_src_gpll", "gpll", CLK_IS_CRITICAL,
721711 			RV1108_CLKGATE_CON(4), 2, GFLAGS),
722
-	COMPOSITE(ACLK_PERI, "aclk_periph", mux_aclk_peri_src_p, 0,
712
+	COMPOSITE(ACLK_PERI, "aclk_periph", mux_aclk_peri_src_p, CLK_IS_CRITICAL,
723713 			RV1108_CLKSEL_CON(23), 15, 1, MFLAGS, 0, 5, DFLAGS,
724714 			RV1108_CLKGATE_CON(15), 11, GFLAGS),
725715 
....@@ -779,20 +769,6 @@
779769 	MMC(SCLK_EMMC_SAMPLE,  "emmc_sample",  "sclk_emmc",  RV1108_EMMC_CON1,  1),
780770 };
781771 
782
-static const char *const rv1108_critical_clocks[] __initconst = {
783
-	"aclk_core",
784
-	"aclk_bus",
785
-	"hclk_bus",
786
-	"pclk_bus",
787
-	"aclk_periph",
788
-	"hclk_periph",
789
-	"pclk_periph",
790
-	"nclk_ddrupctl",
791
-	"pclk_ddrmon",
792
-	"pclk_acodecphy",
793
-	"pclk_pmu",
794
-};
795
-
796772 static void __iomem *rv1108_cru_base;
797773 
798774 static void rv1108_dump_cru(void)
....@@ -809,6 +785,7 @@
809785 {
810786 	struct rockchip_clk_provider *ctx;
811787 	void __iomem *reg_base;
788
+	struct clk **clks;
812789 
813790 	reg_base = of_iomap(np, 0);
814791 	if (!reg_base) {
....@@ -822,17 +799,16 @@
822799 		iounmap(reg_base);
823800 		return;
824801 	}
802
+	clks = ctx->clk_data.clks;
825803 
826804 	rockchip_clk_register_plls(ctx, rv1108_pll_clks,
827805 				   ARRAY_SIZE(rv1108_pll_clks),
828806 				   RV1108_GRF_SOC_STATUS0);
829807 	rockchip_clk_register_branches(ctx, rv1108_clk_branches,
830808 				  ARRAY_SIZE(rv1108_clk_branches));
831
-	rockchip_clk_protect_critical(rv1108_critical_clocks,
832
-				      ARRAY_SIZE(rv1108_critical_clocks));
833809 
834810 	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
835
-			mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
811
+			3, clks[PLL_APLL], clks[PLL_GPLL],
836812 			&rv1108_cpuclk_data, rv1108_cpuclk_rates,
837813 			ARRAY_SIZE(rv1108_cpuclk_rates));
838814 
....@@ -849,3 +825,31 @@
849825 	}
850826 }
851827 CLK_OF_DECLARE(rv1108_cru, "rockchip,rv1108-cru", rv1108_clk_init);
828
+
829
+static int __init clk_rv1108_probe(struct platform_device *pdev)
830
+{
831
+	struct device_node *np = pdev->dev.of_node;
832
+
833
+	rv1108_clk_init(np);
834
+
835
+	return 0;
836
+}
837
+
838
+static const struct of_device_id clk_rv1108_match_table[] = {
839
+	{
840
+		.compatible = "rockchip,rv1108-cru",
841
+	},
842
+	{ }
843
+};
844
+MODULE_DEVICE_TABLE(of, clk_rv1108_match_table);
845
+
846
+static struct platform_driver clk_rv1108_driver = {
847
+	.driver		= {
848
+		.name	= "clk-rv1108",
849
+		.of_match_table = clk_rv1108_match_table,
850
+	},
851
+};
852
+builtin_platform_driver_probe(clk_rv1108_driver, clk_rv1108_probe);
853
+
854
+MODULE_DESCRIPTION("Rockchip RV1108 Clock Driver");
855
+MODULE_LICENSE("GPL");