forked from ~ljy/RK356X_SDK_RELEASE

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2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da 
 kernel/drivers/clk/rockchip/clk-rk3568.c
....@@ -110,15 +110,6 @@
110110 #define RK3568_MUX_CLK_PVTPLL_MASK	0x1
111111 #define RK3568_MUX_CLK_PVTPLL_SHIFT	15
112112 
113
-#define RK3568_CLKSEL0(_apllcore, _pvtpll)			\
114
-{								\
115
-	.reg = RK3568_CLKSEL_CON(0),				\
116
-	.val = HIWORD_UPDATE(_apllcore, RK3568_MUX_CLK_CORE_APLL_MASK,	\
117
-			RK3568_MUX_CLK_CORE_APLL_SHIFT) |		\
118
-		HIWORD_UPDATE(_pvtpll, RK3568_MUX_CLK_PVTPLL_MASK,	\
119
-			RK3568_MUX_CLK_PVTPLL_SHIFT),			\
120
-}
121
-
122113 #define RK3568_CLKSEL1(_sclk_core)					\
123114 {								\
124115 	.reg = RK3568_CLKSEL_CON(2),				\
....@@ -155,69 +146,48 @@
155146 			RK3568_DIV_PERIPHCLK_CORE_SHIFT),		\
156147 }
157148 
158
-#define RK3568_CLKSEL5(_sclk_core_src)					\
159
-{								\
160
-	.reg = RK3568_CLKSEL_CON(2),				\
161
-	.val = HIWORD_UPDATE(_sclk_core_src, RK3568_MUX_SCLK_CORE_MASK, \
162
-			RK3568_MUX_SCLK_CORE_SHIFT),		\
163
-}
164
-
165
-#define RK3568_CPUCLK_RATE(_prate, _pvtpll, _apllcore, _sclk, _acore, _atcore, _gicclk, _pclk, _periph) \
149
+#define RK3568_CPUCLK_RATE(_prate, _sclk, _acore, _atcore, _gicclk, _pclk, _periph) \
166150 {								\
167151 	.prate = _prate##U,					\
168152 	.divs = {						\
153
+		RK3568_CLKSEL1(_sclk),				\
169154 		RK3568_CLKSEL2(_acore),				\
170155 		RK3568_CLKSEL3(_atcore, _gicclk),		\
171156 		RK3568_CLKSEL4(_pclk, _periph),			\
172157 	},							\
173
-	.pre_muxs = {						\
174
-		RK3568_CLKSEL0(0, _pvtpll),			\
175
-		RK3568_CLKSEL5(1),				\
176
-	},							\
177
-	.post_muxs = {						\
178
-		RK3568_CLKSEL0(_apllcore, _pvtpll),		\
179
-		RK3568_CLKSEL1(_sclk),				\
180
-	},							\
181158 }
182159 
183160 static struct rockchip_cpuclk_rate_table rk3568_cpuclk_rates[] __initdata = {
184
-	RK3568_CPUCLK_RATE(2208000000, 1, 1, 1, 1, 9, 9, 9, 9),
185
-	RK3568_CPUCLK_RATE(2184000000, 1, 1, 1, 1, 9, 9, 9, 9),
186
-	RK3568_CPUCLK_RATE(2088000000, 1, 1, 1, 1, 9, 9, 9, 9),
187
-	RK3568_CPUCLK_RATE(2040000000, 1, 1, 1, 1, 9, 9, 9, 9),
188
-	RK3568_CPUCLK_RATE(2016000000, 1, 1, 1, 1, 7, 7, 7, 7),
189
-	RK3568_CPUCLK_RATE(1992000000, 1, 1, 1, 1, 7, 7, 7, 7),
190
-	RK3568_CPUCLK_RATE(1896000000, 1, 1, 1, 1, 7, 7, 7, 7),
191
-	RK3568_CPUCLK_RATE(1800000000, 1, 1, 1, 1, 7, 7, 7, 7),
192
-	RK3568_CPUCLK_RATE(1704000000, 0, 1, 1, 1, 7, 7, 7, 7),
193
-	RK3568_CPUCLK_RATE(1608000000, 0, 1, 1, 1, 5, 5, 5, 5),
194
-	RK3568_CPUCLK_RATE(1584000000, 0, 1, 1, 1, 5, 5, 5, 5),
195
-	RK3568_CPUCLK_RATE(1560000000, 0, 0, 0, 1, 5, 5, 5, 5),
196
-	RK3568_CPUCLK_RATE(1536000000, 0, 0, 0, 1, 5, 5, 5, 5),
197
-	RK3568_CPUCLK_RATE(1512000000, 0, 0, 0, 1, 5, 5, 5, 5),
198
-	RK3568_CPUCLK_RATE(1488000000, 0, 0, 0, 1, 5, 5, 5, 5),
199
-	RK3568_CPUCLK_RATE(1464000000, 0, 0, 0, 1, 5, 5, 5, 5),
200
-	RK3568_CPUCLK_RATE(1440000000, 0, 0, 0, 1, 5, 5, 5, 5),
201
-	RK3568_CPUCLK_RATE(1416000000, 0, 0, 0, 1, 5, 5, 5, 5),
202
-	RK3568_CPUCLK_RATE(1392000000, 0, 0, 0, 1, 5, 5, 5, 5),
203
-	RK3568_CPUCLK_RATE(1368000000, 0, 0, 0, 1, 5, 5, 5, 5),
204
-	RK3568_CPUCLK_RATE(1344000000, 0, 0, 0, 1, 5, 5, 5, 5),
205
-	RK3568_CPUCLK_RATE(1320000000, 0, 0, 0, 1, 5, 5, 5, 5),
206
-	RK3568_CPUCLK_RATE(1296000000, 0, 0, 0, 1, 5, 5, 5, 5),
207
-	RK3568_CPUCLK_RATE(1272000000, 0, 0, 0, 1, 5, 5, 5, 5),
208
-	RK3568_CPUCLK_RATE(1248000000, 0, 0, 0, 1, 5, 5, 5, 5),
209
-	RK3568_CPUCLK_RATE(1224000000, 0, 0, 0, 1, 5, 5, 5, 5),
210
-	RK3568_CPUCLK_RATE(1200000000, 0, 0, 0, 1, 3, 3, 3, 3),
211
-	RK3568_CPUCLK_RATE(1104000000, 0, 0, 0, 1, 3, 3, 3, 3),
212
-	RK3568_CPUCLK_RATE(1008000000, 0, 0, 0, 1, 3, 3, 3, 3),
213
-	RK3568_CPUCLK_RATE(912000000, 0, 0, 0, 1, 3, 3, 3, 3),
214
-	RK3568_CPUCLK_RATE(816000000, 0, 0, 0, 1, 3, 3, 3, 3),
215
-	RK3568_CPUCLK_RATE(696000000, 0, 0, 0, 1, 3, 3, 3, 3),
216
-	RK3568_CPUCLK_RATE(600000000, 0, 0, 0, 1, 3, 3, 3, 3),
217
-	RK3568_CPUCLK_RATE(408000000, 0, 0, 0, 1, 3, 3, 3, 3),
218
-	RK3568_CPUCLK_RATE(312000000, 0, 0, 0, 1, 3, 3, 3, 3),
219
-	RK3568_CPUCLK_RATE(216000000, 0, 0, 0, 1, 3, 3, 3, 3),
220
-	RK3568_CPUCLK_RATE(96000000, 0, 0, 0, 1, 3, 3, 3, 3),
161
+	RK3568_CPUCLK_RATE(1800000000, 0, 1, 7, 7, 7, 7),
162
+	RK3568_CPUCLK_RATE(1704000000, 0, 1, 7, 7, 7, 7),
163
+	RK3568_CPUCLK_RATE(1608000000, 0, 1, 5, 5, 5, 5),
164
+	RK3568_CPUCLK_RATE(1584000000, 0, 1, 5, 5, 5, 5),
165
+	RK3568_CPUCLK_RATE(1560000000, 0, 1, 5, 5, 5, 5),
166
+	RK3568_CPUCLK_RATE(1536000000, 0, 1, 5, 5, 5, 5),
167
+	RK3568_CPUCLK_RATE(1512000000, 0, 1, 5, 5, 5, 5),
168
+	RK3568_CPUCLK_RATE(1488000000, 0, 1, 5, 5, 5, 5),
169
+	RK3568_CPUCLK_RATE(1464000000, 0, 1, 5, 5, 5, 5),
170
+	RK3568_CPUCLK_RATE(1440000000, 0, 1, 5, 5, 5, 5),
171
+	RK3568_CPUCLK_RATE(1416000000, 0, 1, 5, 5, 5, 5),
172
+	RK3568_CPUCLK_RATE(1392000000, 0, 1, 5, 5, 5, 5),
173
+	RK3568_CPUCLK_RATE(1368000000, 0, 1, 5, 5, 5, 5),
174
+	RK3568_CPUCLK_RATE(1344000000, 0, 1, 5, 5, 5, 5),
175
+	RK3568_CPUCLK_RATE(1320000000, 0, 1, 5, 5, 5, 5),
176
+	RK3568_CPUCLK_RATE(1296000000, 0, 1, 5, 5, 5, 5),
177
+	RK3568_CPUCLK_RATE(1272000000, 0, 1, 5, 5, 5, 5),
178
+	RK3568_CPUCLK_RATE(1248000000, 0, 1, 5, 5, 5, 5),
179
+	RK3568_CPUCLK_RATE(1224000000, 0, 1, 5, 5, 5, 5),
180
+	RK3568_CPUCLK_RATE(1200000000, 0, 1, 3, 3, 3, 3),
181
+	RK3568_CPUCLK_RATE(1104000000, 0, 1, 3, 3, 3, 3),
182
+	RK3568_CPUCLK_RATE(1008000000, 0, 1, 3, 3, 3, 3),
183
+	RK3568_CPUCLK_RATE(912000000, 0, 1, 3, 3, 3, 3),
184
+	RK3568_CPUCLK_RATE(816000000, 0, 1, 3, 3, 3, 3),
185
+	RK3568_CPUCLK_RATE(696000000, 0, 1, 3, 3, 3, 3),
186
+	RK3568_CPUCLK_RATE(600000000, 0, 1, 3, 3, 3, 3),
187
+	RK3568_CPUCLK_RATE(408000000, 0, 1, 3, 3, 3, 3),
188
+	RK3568_CPUCLK_RATE(312000000, 0, 1, 3, 3, 3, 3),
189
+	RK3568_CPUCLK_RATE(216000000, 0, 1, 3, 3, 3, 3),
190
+	RK3568_CPUCLK_RATE(96000000, 0, 1, 3, 3, 3, 3),
221191 };
222192 
223193 static const struct rockchip_cpuclk_reg_data rk3568_cpuclk_data = {
....@@ -242,7 +212,6 @@
242212 
243213 PNAME(mux_pll_p)			= { "xin24m" };
244214 PNAME(mux_usb480m_p)			= { "xin24m", "usb480m_phy", "clk_rtc_32k" };
245
-PNAME(mux_armclk_p)			= { "apll", "gpll" };
246215 PNAME(clk_i2s0_8ch_tx_p)		= { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half" };
247216 PNAME(clk_i2s0_8ch_rx_p)		= { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half" };
248217 PNAME(clk_i2s1_8ch_tx_p)		= { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin_osc0_half" };
....@@ -370,7 +339,7 @@
370339 		     0, RK3568_PLL_CON(16),
371340 		     RK3568_MODE_CON0, 6, 3, 0, rk3568_pll_rates),
372341 	[npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p,
373
-		     0, RK3568_PLL_CON(32),
342
+		     CLK_IS_CRITICAL, RK3568_PLL_CON(32),
374343 		     RK3568_MODE_CON0, 10, 5, 0, rk3568_pll_rates),
375344 	[vpll] = PLL(pll_rk3328, PLL_VPLL, "vpll", mux_pll_p,
376345 		     0, RK3568_PLL_CON(40),
....@@ -461,11 +430,6 @@
461430 	MUX(CLK_RTC_32K, "clk_rtc_32k", clk_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
462431 			RK3568_PMU_CLKSEL_CON(0), 6, 2, MFLAGS);
463432 
464
-static struct rockchip_clk_branch rk3568_clk_npu_np5 __initdata =
465
-	COMPOSITE_HALFDIV(CLK_NPU_NP5, "clk_npu_np5", npll_gpll_p, 0,
466
-			RK3568_CLKSEL_CON(7), 7, 1, MFLAGS, 4, 2, DFLAGS,
467
-			RK3568_CLKGATE_CON(3), 1, GFLAGS);
468
-
469433 static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
470434 	/*
471435 	 * Clock-Architecture Diagram 1
....@@ -525,36 +489,36 @@
525489 			RK3568_MODE_CON0, 14, 2, MFLAGS),
526490 
527491 	/* PD_CORE */
528
-	COMPOSITE(0, "sclk_core_src", apll_gpll_npll_p, CLK_IGNORE_UNUSED,
492
+	COMPOSITE(0, "sclk_core_src", apll_gpll_npll_p, CLK_IS_CRITICAL,
529493 			RK3568_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
530494 			RK3568_CLKGATE_CON(0), 5, GFLAGS),
531
-	COMPOSITE_NODIV(0, "sclk_core", sclk_core_pre_p, CLK_IGNORE_UNUSED,
495
+	COMPOSITE_NODIV(0, "sclk_core", sclk_core_pre_p, CLK_IS_CRITICAL,
532496 			RK3568_CLKSEL_CON(2), 15, 1, MFLAGS,
533497 			RK3568_CLKGATE_CON(0), 7, GFLAGS),
534498 
535
-	COMPOSITE_NOMUX(0, "atclk_core", "armclk", CLK_IGNORE_UNUSED,
499
+	COMPOSITE_NOMUX(0, "atclk_core", "armclk", CLK_IS_CRITICAL,
536500 			RK3568_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
537501 			RK3568_CLKGATE_CON(0), 8, GFLAGS),
538
-	COMPOSITE_NOMUX(0, "gicclk_core", "armclk", CLK_IGNORE_UNUSED,
502
+	COMPOSITE_NOMUX(0, "gicclk_core", "armclk", CLK_IS_CRITICAL,
539503 			RK3568_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
540504 			RK3568_CLKGATE_CON(0), 9, GFLAGS),
541
-	COMPOSITE_NOMUX(0, "pclk_core_pre", "armclk", CLK_IGNORE_UNUSED,
505
+	COMPOSITE_NOMUX(0, "pclk_core_pre", "armclk", CLK_IS_CRITICAL,
542506 			RK3568_CLKSEL_CON(4), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
543507 			RK3568_CLKGATE_CON(0), 10, GFLAGS),
544
-	COMPOSITE_NOMUX(0, "periphclk_core_pre", "armclk", CLK_IGNORE_UNUSED,
508
+	COMPOSITE_NOMUX(0, "periphclk_core_pre", "armclk", CLK_IS_CRITICAL,
545509 			RK3568_CLKSEL_CON(4), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
546510 			RK3568_CLKGATE_CON(0), 11, GFLAGS),
547
-	COMPOSITE_NOMUX(0, "tsclk_core", "periphclk_core_pre", CLK_IGNORE_UNUSED,
511
+	COMPOSITE_NOMUX(0, "tsclk_core", "periphclk_core_pre", CLK_IS_CRITICAL,
548512 			RK3568_CLKSEL_CON(5), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
549513 			RK3568_CLKGATE_CON(0), 14, GFLAGS),
550
-	COMPOSITE_NOMUX(0, "cntclk_core", "periphclk_core_pre", CLK_IGNORE_UNUSED,
514
+	COMPOSITE_NOMUX(0, "cntclk_core", "periphclk_core_pre", CLK_IS_CRITICAL,
551515 			RK3568_CLKSEL_CON(5), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
552516 			RK3568_CLKGATE_CON(0), 15, GFLAGS),
553
-	COMPOSITE_NOMUX(0, "aclk_core", "sclk_core", CLK_IGNORE_UNUSED,
517
+	COMPOSITE_NOMUX(0, "aclk_core", "sclk_core", CLK_IS_CRITICAL,
554518 			RK3568_CLKSEL_CON(5), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
555519 			RK3568_CLKGATE_CON(1), 0, GFLAGS),
556520 
557
-	COMPOSITE_NODIV(ACLK_CORE_NIU2BUS, "aclk_core_niu2bus", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED,
521
+	COMPOSITE_NODIV(ACLK_CORE_NIU2BUS, "aclk_core_niu2bus", gpll150_gpll100_gpll75_xin24m_p, CLK_IS_CRITICAL,
558522 			RK3568_CLKSEL_CON(5), 14, 2, MFLAGS,
559523 			RK3568_CLKGATE_CON(1), 2, GFLAGS),
560524 
....@@ -590,10 +554,12 @@
590554 			RK3568_CLKGATE_CON(2), 9, GFLAGS),
591555 
592556 	/* PD_NPU */
593
-	COMPOSITE_BROTHER(CLK_NPU_SRC, "clk_npu_src", npll_gpll_p, 0,
557
+	COMPOSITE(CLK_NPU_SRC, "clk_npu_src", npll_gpll_p, 0,
594558 			RK3568_CLKSEL_CON(7), 6, 1, MFLAGS, 0, 4, DFLAGS,
595
-			RK3568_CLKGATE_CON(3), 0, GFLAGS,
596
-			&rk3568_clk_npu_np5),
559
+			RK3568_CLKGATE_CON(3), 0, GFLAGS),
560
+	COMPOSITE_HALFDIV(CLK_NPU_NP5, "clk_npu_np5", npll_gpll_p, 0,
561
+			RK3568_CLKSEL_CON(7), 7, 1, MFLAGS, 4, 2, DFLAGS,
562
+			RK3568_CLKGATE_CON(3), 1, GFLAGS),
597563 	MUX(CLK_NPU_PRE_NDFT, "clk_npu_pre_ndft", clk_npu_pre_ndft_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
598564 			RK3568_CLKSEL_CON(7), 8, 1, MFLAGS),
599565 	MUX(CLK_NPU, "clk_npu", clk_npu_p, CLK_SET_RATE_PARENT,
....@@ -664,7 +630,7 @@
664630 	COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT,
665631 			RK3568_CLKSEL_CON(12), 0,
666632 			RK3568_CLKGATE_CON(6), 1, GFLAGS,
667
-			&rk3568_i2s0_8ch_tx_fracmux, RK3568_FRAC_MAX_PRATE),
633
+			&rk3568_i2s0_8ch_tx_fracmux),
668634 	GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0,
669635 			RK3568_CLKGATE_CON(6), 2, GFLAGS),
670636 	COMPOSITE_NODIV(I2S0_MCLKOUT_TX, "i2s0_mclkout_tx", i2s0_mclkout_tx_p, CLK_SET_RATE_PARENT,
....@@ -677,7 +643,7 @@
677643 	COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT,
678644 			RK3568_CLKSEL_CON(14), 0,
679645 			RK3568_CLKGATE_CON(6), 5, GFLAGS,
680
-			&rk3568_i2s0_8ch_rx_fracmux, RK3568_FRAC_MAX_PRATE),
646
+			&rk3568_i2s0_8ch_rx_fracmux),
681647 	GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0,
682648 			RK3568_CLKGATE_CON(6), 6, GFLAGS),
683649 	COMPOSITE_NODIV(I2S0_MCLKOUT_RX, "i2s0_mclkout_rx", i2s0_mclkout_rx_p, CLK_SET_RATE_PARENT,
....@@ -690,7 +656,7 @@
690656 	COMPOSITE_FRACMUX(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", CLK_SET_RATE_PARENT,
691657 			RK3568_CLKSEL_CON(16), 0,
692658 			RK3568_CLKGATE_CON(6), 9, GFLAGS,
693
-			&rk3568_i2s1_8ch_tx_fracmux, RK3568_FRAC_MAX_PRATE),
659
+			&rk3568_i2s1_8ch_tx_fracmux),
694660 	GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 0,
695661 			RK3568_CLKGATE_CON(6), 10, GFLAGS),
696662 	COMPOSITE_NODIV(I2S1_MCLKOUT_TX, "i2s1_mclkout_tx", i2s1_mclkout_tx_p, CLK_SET_RATE_PARENT,
....@@ -703,7 +669,7 @@
703669 	COMPOSITE_FRACMUX(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", CLK_SET_RATE_PARENT,
704670 			RK3568_CLKSEL_CON(18), 0,
705671 			RK3568_CLKGATE_CON(6), 13, GFLAGS,
706
-			&rk3568_i2s1_8ch_rx_fracmux, RK3568_FRAC_MAX_PRATE),
672
+			&rk3568_i2s1_8ch_rx_fracmux),
707673 	GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 0,
708674 			RK3568_CLKGATE_CON(6), 14, GFLAGS),
709675 	COMPOSITE_NODIV(I2S1_MCLKOUT_RX, "i2s1_mclkout_rx", i2s1_mclkout_rx_p, CLK_SET_RATE_PARENT,
....@@ -716,7 +682,7 @@
716682 	COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", CLK_SET_RATE_PARENT,
717683 			RK3568_CLKSEL_CON(20), 0,
718684 			RK3568_CLKGATE_CON(7), 1, GFLAGS,
719
-			&rk3568_i2s2_2ch_fracmux, RK3568_FRAC_MAX_PRATE),
685
+			&rk3568_i2s2_2ch_fracmux),
720686 	GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 0,
721687 			RK3568_CLKGATE_CON(7), 2, GFLAGS),
722688 	COMPOSITE_NODIV(I2S2_MCLKOUT, "i2s2_mclkout", i2s2_mclkout_p, CLK_SET_RATE_PARENT,
....@@ -729,7 +695,7 @@
729695 	COMPOSITE_FRACMUX(CLK_I2S3_2CH_TX_FRAC, "clk_i2s3_2ch_tx_frac", "clk_i2s3_2ch_tx_src", CLK_SET_RATE_PARENT,
730696 			RK3568_CLKSEL_CON(22), 0,
731697 			RK3568_CLKGATE_CON(7), 5, GFLAGS,
732
-			&rk3568_i2s3_2ch_tx_fracmux, RK3568_FRAC_MAX_PRATE),
698
+			&rk3568_i2s3_2ch_tx_fracmux),
733699 	GATE(MCLK_I2S3_2CH_TX, "mclk_i2s3_2ch_tx", "clk_i2s3_2ch_tx", 0,
734700 			RK3568_CLKGATE_CON(7), 6, GFLAGS),
735701 	COMPOSITE_NODIV(I2S3_MCLKOUT_TX, "i2s3_mclkout_tx", i2s3_mclkout_tx_p, CLK_SET_RATE_PARENT,
....@@ -742,7 +708,7 @@
742708 	COMPOSITE_FRACMUX(CLK_I2S3_2CH_RX_FRAC, "clk_i2s3_2ch_rx_frac", "clk_i2s3_2ch_rx_src", CLK_SET_RATE_PARENT,
743709 			RK3568_CLKSEL_CON(84), 0,
744710 			RK3568_CLKGATE_CON(7), 9, GFLAGS,
745
-			&rk3568_i2s3_2ch_rx_fracmux, RK3568_FRAC_MAX_PRATE),
711
+			&rk3568_i2s3_2ch_rx_fracmux),
746712 	GATE(MCLK_I2S3_2CH_RX, "mclk_i2s3_2ch_rx", "clk_i2s3_2ch_rx", 0,
747713 			RK3568_CLKGATE_CON(7), 10, GFLAGS),
748714 	COMPOSITE_NODIV(I2S3_MCLKOUT_RX, "i2s3_mclkout_rx", i2s3_mclkout_rx_p, CLK_SET_RATE_PARENT,
....@@ -778,7 +744,7 @@
778744 	COMPOSITE_FRACMUX(MCLK_SPDIF_8CH_FRAC, "mclk_spdif_8ch_frac", "mclk_spdif_8ch_src", CLK_SET_RATE_PARENT,
779745 			RK3568_CLKSEL_CON(24), 0,
780746 			RK3568_CLKGATE_CON(7), 15, GFLAGS,
781
-			&rk3568_spdif_8ch_fracmux, RK3568_SPDIF_FRAC_MAX_PRATE),
747
+			&rk3568_spdif_8ch_fracmux),
782748 
783749 	GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_gic_audio", 0,
784750 			RK3568_CLKGATE_CON(8), 0, GFLAGS),
....@@ -788,7 +754,7 @@
788754 	COMPOSITE_FRACMUX(SCLK_AUDPWM_FRAC, "sclk_audpwm_frac", "sclk_audpwm_src", CLK_SET_RATE_PARENT,
789755 			RK3568_CLKSEL_CON(26), 0,
790756 			RK3568_CLKGATE_CON(8), 2, GFLAGS,
791
-			&rk3568_audpwm_fracmux, RK3568_FRAC_MAX_PRATE),
757
+			&rk3568_audpwm_fracmux),
792758 
793759 	GATE(HCLK_ACDCDIG, "hclk_acdcdig", "hclk_gic_audio", 0,
794760 			RK3568_CLKGATE_CON(8), 3, GFLAGS),
....@@ -801,10 +767,10 @@
801767 			RK3568_CLKGATE_CON(8), 6, GFLAGS),
802768 
803769 	/* PD_SECURE_FLASH */
804
-	COMPOSITE_NODIV(ACLK_SECURE_FLASH, "aclk_secure_flash", gpll200_gpll150_gpll100_xin24m_p, 0,
770
+	COMPOSITE_NODIV(ACLK_SECURE_FLASH, "aclk_secure_flash", gpll200_gpll150_gpll100_xin24m_p, CLK_IS_CRITICAL,
805771 			RK3568_CLKSEL_CON(27), 0, 2, MFLAGS,
806772 			RK3568_CLKGATE_CON(8), 7, GFLAGS),
807
-	COMPOSITE_NODIV(HCLK_SECURE_FLASH, "hclk_secure_flash", gpll150_gpll100_gpll75_xin24m_p, 0,
773
+	COMPOSITE_NODIV(HCLK_SECURE_FLASH, "hclk_secure_flash", gpll150_gpll100_gpll75_xin24m_p, CLK_IS_CRITICAL,
808774 			RK3568_CLKSEL_CON(27), 2, 2, MFLAGS,
809775 			RK3568_CLKGATE_CON(8), 8, GFLAGS),
810776 	GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_flash", 0,
....@@ -935,10 +901,10 @@
935901 	COMPOSITE_NODIV(ACLK_PHP, "aclk_php", gpll300_gpll200_gpll100_xin24m_p, 0,
936902 			RK3568_CLKSEL_CON(30), 0, 2, MFLAGS,
937903 			RK3568_CLKGATE_CON(14), 8, GFLAGS),
938
-	COMPOSITE_NODIV(HCLK_PHP, "hclk_php", gpll150_gpll100_gpll75_xin24m_p, 0,
904
+	COMPOSITE_NODIV(HCLK_PHP, "hclk_php", gpll150_gpll100_gpll75_xin24m_p, CLK_IS_CRITICAL,
939905 			RK3568_CLKSEL_CON(30), 2, 2, MFLAGS,
940906 			RK3568_CLKGATE_CON(14), 9, GFLAGS),
941
-	COMPOSITE_NOMUX(PCLK_PHP, "pclk_php", "aclk_php", 0,
907
+	COMPOSITE_NOMUX(PCLK_PHP, "pclk_php", "aclk_php", CLK_IS_CRITICAL,
942908 			RK3568_CLKSEL_CON(30), 4, 4, DFLAGS,
943909 			RK3568_CLKGATE_CON(14), 10, GFLAGS),
944910 	GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_php", 0,
....@@ -982,17 +948,17 @@
982948 			RK3568_CLKSEL_CON(31), 4, 2, MFLAGS),
983949 	MUX(SCLK_GMAC0_RMII_SPEED, "clk_gmac0_rmii_speed", mux_gmac0_rmii_speed_p, 0,
984950 			RK3568_CLKSEL_CON(31), 3, 1, MFLAGS),
985
-	MUX(SCLK_GMAC0_RX_TX, "clk_gmac0_rx_tx", mux_gmac0_rx_tx_p,  CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
951
+	MUX(SCLK_GMAC0_RX_TX, "clk_gmac0_rx_tx", mux_gmac0_rx_tx_p,  CLK_SET_RATE_PARENT,
986952 			RK3568_CLKSEL_CON(31), 0, 2, MFLAGS),
987953 
988954 	/* PD_USB */
989955 	COMPOSITE_NODIV(ACLK_USB, "aclk_usb", gpll300_gpll200_gpll100_xin24m_p, 0,
990956 			RK3568_CLKSEL_CON(32), 0, 2, MFLAGS,
991957 			RK3568_CLKGATE_CON(16), 0, GFLAGS),
992
-	COMPOSITE_NODIV(HCLK_USB, "hclk_usb", gpll150_gpll100_gpll75_xin24m_p, 0,
958
+	COMPOSITE_NODIV(HCLK_USB, "hclk_usb", gpll150_gpll100_gpll75_xin24m_p, CLK_IS_CRITICAL,
993959 			RK3568_CLKSEL_CON(32), 2, 2, MFLAGS,
994960 			RK3568_CLKGATE_CON(16), 1, GFLAGS),
995
-	COMPOSITE_NOMUX(PCLK_USB, "pclk_usb", "aclk_usb", 0,
961
+	COMPOSITE_NOMUX(PCLK_USB, "pclk_usb", "aclk_usb", CLK_IS_CRITICAL,
996962 			RK3568_CLKSEL_CON(32), 4, 4, DFLAGS,
997963 			RK3568_CLKGATE_CON(16), 2, GFLAGS),
998964 	GATE(HCLK_USB2HOST0, "hclk_usb2host0", "hclk_usb", 0,
....@@ -1036,14 +1002,14 @@
10361002 			RK3568_CLKSEL_CON(33), 4, 2, MFLAGS),
10371003 	MUX(SCLK_GMAC1_RMII_SPEED, "clk_gmac1_rmii_speed", mux_gmac1_rmii_speed_p, 0,
10381004 			RK3568_CLKSEL_CON(33), 3, 1, MFLAGS),
1039
-	MUX(SCLK_GMAC1_RX_TX, "clk_gmac1_rx_tx", mux_gmac1_rx_tx_p,  CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1005
+	MUX(SCLK_GMAC1_RX_TX, "clk_gmac1_rx_tx", mux_gmac1_rx_tx_p,  CLK_SET_RATE_PARENT,
10401006 			RK3568_CLKSEL_CON(33), 0, 2, MFLAGS),
10411007 
10421008 	/* PD_PERI */
1043
-	COMPOSITE_NODIV(ACLK_PERIMID, "aclk_perimid", gpll300_gpll200_gpll100_xin24m_p, CLK_IGNORE_UNUSED,
1009
+	COMPOSITE_NODIV(ACLK_PERIMID, "aclk_perimid", gpll300_gpll200_gpll100_xin24m_p, CLK_IS_CRITICAL,
10441010 			RK3568_CLKSEL_CON(10), 4, 2, MFLAGS,
10451011 			RK3568_CLKGATE_CON(14), 0, GFLAGS),
1046
-	COMPOSITE_NODIV(HCLK_PERIMID, "hclk_perimid", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED,
1012
+	COMPOSITE_NODIV(HCLK_PERIMID, "hclk_perimid", gpll150_gpll100_gpll75_xin24m_p, CLK_IS_CRITICAL,
10471013 			RK3568_CLKSEL_CON(10), 6, 2, MFLAGS,
10481014 			RK3568_CLKGATE_CON(14), 1, GFLAGS),
10491015 
....@@ -1102,13 +1068,13 @@
11021068 			RK3568_CLKGATE_CON(20), 8, GFLAGS),
11031069 	GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 0,
11041070 			RK3568_CLKGATE_CON(20), 9, GFLAGS),
1105
-	COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1071
+	COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,
11061072 			RK3568_CLKSEL_CON(39), 10, 2, MFLAGS, 0, 8, DFLAGS,
11071073 			RK3568_CLKGATE_CON(20), 10, GFLAGS),
1108
-	COMPOSITE_DCLK(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1074
+	COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,
11091075 			RK3568_CLKSEL_CON(40), 10, 2, MFLAGS, 0, 8, DFLAGS,
1110
-			RK3568_CLKGATE_CON(20), 11, GFLAGS, RK3568_DCLK_PARENT_MAX_PRATE),
1111
-	COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, 0,
1076
+			RK3568_CLKGATE_CON(20), 11, GFLAGS),
1077
+	COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,
11121078 			RK3568_CLKSEL_CON(41), 10, 2, MFLAGS, 0, 8, DFLAGS,
11131079 			RK3568_CLKGATE_CON(20), 12, GFLAGS),
11141080 	GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 0,
....@@ -1158,35 +1124,35 @@
11581124 			RK3568_CLKSEL_CON(43), 12, 4, DFLAGS,
11591125 			RK3568_CLKGATE_CON(22), 12, GFLAGS),
11601126 	GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0,
1161
-			RK3568_CLKGATE_CON(23), 4, GFLAGS | CLK_GATE_NO_SET_RATE),
1127
+			RK3568_CLKGATE_CON(23), 4, GFLAGS),
11621128 	GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0,
1163
-			RK3568_CLKGATE_CON(23), 5, GFLAGS | CLK_GATE_NO_SET_RATE),
1129
+			RK3568_CLKGATE_CON(23), 5, GFLAGS),
11641130 	COMPOSITE_NODIV(CLK_RGA_CORE, "clk_rga_core", gpll300_gpll200_gpll100_p, 0,
11651131 			RK3568_CLKSEL_CON(43), 2, 2, MFLAGS,
11661132 			RK3568_CLKGATE_CON(23), 6, GFLAGS),
11671133 	GATE(ACLK_IEP, "aclk_iep", "aclk_rga_pre", 0,
1168
-			RK3568_CLKGATE_CON(23), 7, GFLAGS | CLK_GATE_NO_SET_RATE),
1134
+			RK3568_CLKGATE_CON(23), 7, GFLAGS),
11691135 	GATE(HCLK_IEP, "hclk_iep", "hclk_rga_pre", 0,
1170
-			RK3568_CLKGATE_CON(23), 8, GFLAGS | CLK_GATE_NO_SET_RATE),
1136
+			RK3568_CLKGATE_CON(23), 8, GFLAGS),
11711137 	COMPOSITE_NODIV(CLK_IEP_CORE, "clk_iep_core", gpll300_gpll200_gpll100_p, 0,
11721138 			RK3568_CLKSEL_CON(43), 4, 2, MFLAGS,
11731139 			RK3568_CLKGATE_CON(23), 9, GFLAGS),
1174
-	GATE(HCLK_EBC, "hclk_ebc", "hclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 10, GFLAGS | CLK_GATE_NO_SET_RATE),
1140
+	GATE(HCLK_EBC, "hclk_ebc", "hclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 10, GFLAGS),
11751141 	COMPOSITE_NODIV(DCLK_EBC, "dclk_ebc", gpll400_cpll333_gpll200_p, 0,
11761142 			RK3568_CLKSEL_CON(43), 6, 2, MFLAGS,
11771143 			RK3568_CLKGATE_CON(23), 11, GFLAGS),
11781144 	GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_pre", 0,
1179
-			RK3568_CLKGATE_CON(23), 12, GFLAGS | CLK_GATE_NO_SET_RATE),
1145
+			RK3568_CLKGATE_CON(23), 12, GFLAGS),
11801146 	GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 0,
1181
-			RK3568_CLKGATE_CON(23), 13, GFLAGS | CLK_GATE_NO_SET_RATE),
1147
+			RK3568_CLKGATE_CON(23), 13, GFLAGS),
11821148 	GATE(ACLK_JENC, "aclk_jenc", "aclk_rga_pre", 0,
1183
-			RK3568_CLKGATE_CON(23), 14, GFLAGS | CLK_GATE_NO_SET_RATE),
1149
+			RK3568_CLKGATE_CON(23), 14, GFLAGS),
11841150 	GATE(HCLK_JENC, "hclk_jenc", "hclk_rga_pre", 0,
11851151 			RK3568_CLKGATE_CON(23), 15, GFLAGS),
11861152 	GATE(PCLK_EINK, "pclk_eink", "pclk_rga_pre", 0,
1187
-			RK3568_CLKGATE_CON(22), 14, GFLAGS | CLK_GATE_NO_SET_RATE),
1153
+			RK3568_CLKGATE_CON(22), 14, GFLAGS),
11881154 	GATE(HCLK_EINK, "hclk_eink", "hclk_rga_pre", 0,
1189
-			RK3568_CLKGATE_CON(22), 15, GFLAGS | CLK_GATE_NO_SET_RATE),
1155
+			RK3568_CLKGATE_CON(22), 15, GFLAGS),
11901156 
11911157 	/* PD_RKVENC */
11921158 	COMPOSITE(ACLK_RKVENC_PRE, "aclk_rkvenc_pre", gpll_cpll_npll_p, 0,
....@@ -1223,10 +1189,10 @@
12231189 			RK3568_CLKGATE_CON(25), 8, GFLAGS),
12241190 
12251191 	/* PD_BUS */
1226
-	COMPOSITE_NODIV(ACLK_BUS, "aclk_bus", gpll200_gpll150_gpll100_xin24m_p, 0,
1192
+	COMPOSITE_NODIV(ACLK_BUS, "aclk_bus", gpll200_gpll150_gpll100_xin24m_p, CLK_IS_CRITICAL,
12271193 			RK3568_CLKSEL_CON(50), 0, 2, MFLAGS,
12281194 			RK3568_CLKGATE_CON(26), 0, GFLAGS),
1229
-	COMPOSITE_NODIV(PCLK_BUS, "pclk_bus", gpll100_gpll75_cpll50_xin24m_p, 0,
1195
+	COMPOSITE_NODIV(PCLK_BUS, "pclk_bus", gpll100_gpll75_cpll50_xin24m_p, CLK_IS_CRITICAL,
12301196 			RK3568_CLKSEL_CON(50), 4, 2, MFLAGS,
12311197 			RK3568_CLKGATE_CON(26), 1, GFLAGS),
12321198 	GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0,
....@@ -1262,7 +1228,7 @@
12621228 	COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
12631229 			RK3568_CLKSEL_CON(53), CLK_FRAC_DIVIDER_NO_LIMIT,
12641230 			RK3568_CLKGATE_CON(27), 14, GFLAGS,
1265
-			&rk3568_uart1_fracmux, RK3568_UART_FRAC_MAX_PRATE),
1231
+			&rk3568_uart1_fracmux),
12661232 	GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0,
12671233 			RK3568_CLKGATE_CON(27), 15, GFLAGS),
12681234 
....@@ -1274,7 +1240,7 @@
12741240 	COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
12751241 			RK3568_CLKSEL_CON(55), CLK_FRAC_DIVIDER_NO_LIMIT,
12761242 			RK3568_CLKGATE_CON(28), 2, GFLAGS,
1277
-			&rk3568_uart2_fracmux, RK3568_UART_FRAC_MAX_PRATE),
1243
+			&rk3568_uart2_fracmux),
12781244 	GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 0,
12791245 			RK3568_CLKGATE_CON(28), 3, GFLAGS),
12801246 
....@@ -1286,7 +1252,7 @@
12861252 	COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
12871253 			RK3568_CLKSEL_CON(57), CLK_FRAC_DIVIDER_NO_LIMIT,
12881254 			RK3568_CLKGATE_CON(28), 6, GFLAGS,
1289
-			&rk3568_uart3_fracmux, RK3568_UART_FRAC_MAX_PRATE),
1255
+			&rk3568_uart3_fracmux),
12901256 	GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0,
12911257 			RK3568_CLKGATE_CON(28), 7, GFLAGS),
12921258 
....@@ -1298,7 +1264,7 @@
12981264 	COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
12991265 			RK3568_CLKSEL_CON(59), CLK_FRAC_DIVIDER_NO_LIMIT,
13001266 			RK3568_CLKGATE_CON(28), 10, GFLAGS,
1301
-			&rk3568_uart4_fracmux, RK3568_UART_FRAC_MAX_PRATE),
1267
+			&rk3568_uart4_fracmux),
13021268 	GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0,
13031269 			RK3568_CLKGATE_CON(28), 11, GFLAGS),
13041270 
....@@ -1310,7 +1276,7 @@
13101276 	COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
13111277 			RK3568_CLKSEL_CON(61), CLK_FRAC_DIVIDER_NO_LIMIT,
13121278 			RK3568_CLKGATE_CON(28), 14, GFLAGS,
1313
-			&rk3568_uart5_fracmux, RK3568_UART_FRAC_MAX_PRATE),
1279
+			&rk3568_uart5_fracmux),
13141280 	GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0,
13151281 			RK3568_CLKGATE_CON(28), 15, GFLAGS),
13161282 
....@@ -1322,7 +1288,7 @@
13221288 	COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT,
13231289 			RK3568_CLKSEL_CON(63), CLK_FRAC_DIVIDER_NO_LIMIT,
13241290 			RK3568_CLKGATE_CON(29), 2, GFLAGS,
1325
-			&rk3568_uart6_fracmux, RK3568_UART_FRAC_MAX_PRATE),
1291
+			&rk3568_uart6_fracmux),
13261292 	GATE(SCLK_UART6, "sclk_uart6", "sclk_uart6_mux", 0,
13271293 			RK3568_CLKGATE_CON(29), 3, GFLAGS),
13281294 
....@@ -1334,7 +1300,7 @@
13341300 	COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT,
13351301 			RK3568_CLKSEL_CON(65), CLK_FRAC_DIVIDER_NO_LIMIT,
13361302 			RK3568_CLKGATE_CON(29), 6, GFLAGS,
1337
-			&rk3568_uart7_fracmux, RK3568_UART_FRAC_MAX_PRATE),
1303
+			&rk3568_uart7_fracmux),
13381304 	GATE(SCLK_UART7, "sclk_uart7", "sclk_uart7_mux", 0,
13391305 			RK3568_CLKGATE_CON(29), 7, GFLAGS),
13401306 
....@@ -1346,7 +1312,7 @@
13461312 	COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT,
13471313 			RK3568_CLKSEL_CON(67), CLK_FRAC_DIVIDER_NO_LIMIT,
13481314 			RK3568_CLKGATE_CON(29), 10, GFLAGS,
1349
-			&rk3568_uart8_fracmux, RK3568_UART_FRAC_MAX_PRATE),
1315
+			&rk3568_uart8_fracmux),
13501316 	GATE(SCLK_UART8, "sclk_uart8", "sclk_uart8_mux", 0,
13511317 			RK3568_CLKGATE_CON(29), 11, GFLAGS),
13521318 
....@@ -1358,7 +1324,7 @@
13581324 	COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT,
13591325 			RK3568_CLKSEL_CON(69), CLK_FRAC_DIVIDER_NO_LIMIT,
13601326 			RK3568_CLKGATE_CON(29), 14, GFLAGS,
1361
-			&rk3568_uart9_fracmux, RK3568_UART_FRAC_MAX_PRATE),
1327
+			&rk3568_uart9_fracmux),
13621328 	GATE(SCLK_UART9, "sclk_uart9", "sclk_uart9_mux", 0,
13631329 			RK3568_CLKGATE_CON(29), 15, GFLAGS),
13641330 
....@@ -1421,21 +1387,21 @@
14211387 			RK3568_CLKSEL_CON(72), 6, 1, MFLAGS, RK3568_CLKGATE_CON(31), 1, GFLAGS),
14221388 	GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 10, GFLAGS),
14231389 	COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", gpll100_xin24m_cpll100_p, 0,
1424
-			RK3568_CLKSEL_CON(72), 8, 1, MFLAGS,
1390
+			RK3568_CLKSEL_CON(72), 8, 2, MFLAGS,
14251391 			RK3568_CLKGATE_CON(31), 11, GFLAGS),
14261392 	GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0,
14271393 			RK3568_CLKGATE_CON(31), 12, GFLAGS),
14281394 	GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", 0,
14291395 			RK3568_CLKGATE_CON(31), 13, GFLAGS),
14301396 	COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", gpll100_xin24m_cpll100_p, 0,
1431
-			RK3568_CLKSEL_CON(72), 10, 1, MFLAGS,
1397
+			RK3568_CLKSEL_CON(72), 10, 2, MFLAGS,
14321398 			RK3568_CLKGATE_CON(31), 14, GFLAGS),
14331399 	GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0,
14341400 			RK3568_CLKGATE_CON(31), 15, GFLAGS),
14351401 	GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus", 0,
14361402 			RK3568_CLKGATE_CON(32), 0, GFLAGS),
14371403 	COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", gpll100_xin24m_cpll100_p, 0,
1438
-			RK3568_CLKSEL_CON(72), 12, 1, MFLAGS,
1404
+			RK3568_CLKSEL_CON(72), 12, 2, MFLAGS,
14391405 			RK3568_CLKGATE_CON(32), 1, GFLAGS),
14401406 	GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0,
14411407 			RK3568_CLKGATE_CON(32), 2, GFLAGS),
....@@ -1474,21 +1440,21 @@
14741440 			RK3568_CLKGATE_CON(32), 9, GFLAGS),
14751441 
14761442 	/* PD_TOP */
1477
-	COMPOSITE_NODIV(ACLK_TOP_HIGH, "aclk_top_high", cpll500_gpll400_gpll300_xin24m_p, 0,
1443
+	COMPOSITE_NODIV(ACLK_TOP_HIGH, "aclk_top_high", cpll500_gpll400_gpll300_xin24m_p, CLK_IS_CRITICAL,
14781444 			RK3568_CLKSEL_CON(73), 0, 2, MFLAGS,
14791445 			RK3568_CLKGATE_CON(33), 0, GFLAGS),
1480
-	COMPOSITE_NODIV(ACLK_TOP_LOW, "aclk_top_low", gpll400_gpll300_gpll200_xin24m_p, 0,
1446
+	COMPOSITE_NODIV(ACLK_TOP_LOW, "aclk_top_low", gpll400_gpll300_gpll200_xin24m_p, CLK_IS_CRITICAL,
14811447 			RK3568_CLKSEL_CON(73), 4, 2, MFLAGS,
14821448 			RK3568_CLKGATE_CON(33), 1, GFLAGS),
1483
-	COMPOSITE_NODIV(HCLK_TOP, "hclk_top", gpll150_gpll100_gpll75_xin24m_p, 0,
1449
+	COMPOSITE_NODIV(HCLK_TOP, "hclk_top", gpll150_gpll100_gpll75_xin24m_p, CLK_IS_CRITICAL,
14841450 			RK3568_CLKSEL_CON(73), 8, 2, MFLAGS,
14851451 			RK3568_CLKGATE_CON(33), 2, GFLAGS),
1486
-	COMPOSITE_NODIV(PCLK_TOP, "pclk_top", gpll100_gpll75_cpll50_xin24m_p, 0,
1452
+	COMPOSITE_NODIV(PCLK_TOP, "pclk_top", gpll100_gpll75_cpll50_xin24m_p, CLK_IS_CRITICAL,
14871453 			RK3568_CLKSEL_CON(73), 12, 2, MFLAGS,
14881454 			RK3568_CLKGATE_CON(33), 3, GFLAGS),
14891455 	GATE(PCLK_PCIE30PHY, "pclk_pcie30phy", "pclk_top", 0,
14901456 			RK3568_CLKGATE_CON(33), 8, GFLAGS),
1491
-	COMPOSITE_NODIV(CLK_OPTC_ARB, "clk_optc_arb", xin24m_cpll100_p, 0,
1457
+	COMPOSITE_NODIV(CLK_OPTC_ARB, "clk_optc_arb", xin24m_cpll100_p, CLK_IS_CRITICAL,
14921458 			RK3568_CLKSEL_CON(73), 15, 1, MFLAGS,
14931459 			RK3568_CLKGATE_CON(33), 9, GFLAGS),
14941460 	GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top", 0,
....@@ -1521,12 +1487,12 @@
15211487 
15221488 	MUX(CLK_PDPMU, "clk_pdpmu", clk_pdpmu_p, 0,
15231489 			RK3568_PMU_CLKSEL_CON(2), 15, 1, MFLAGS),
1524
-	COMPOSITE_NOMUX(PCLK_PDPMU, "pclk_pdpmu", "clk_pdpmu", 0,
1490
+	COMPOSITE_NOMUX(PCLK_PDPMU, "pclk_pdpmu", "clk_pdpmu", CLK_IS_CRITICAL,
15251491 			RK3568_PMU_CLKSEL_CON(2), 0, 5, DFLAGS,
15261492 			RK3568_PMU_CLKGATE_CON(0), 2, GFLAGS),
1527
-	GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", 0,
1493
+	GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", CLK_IS_CRITICAL,
15281494 			RK3568_PMU_CLKGATE_CON(0), 6, GFLAGS),
1529
-	GATE(CLK_PMU, "clk_pmu", "xin24m", 0,
1495
+	GATE(CLK_PMU, "clk_pmu", "xin24m", CLK_IS_CRITICAL,
15301496 			RK3568_PMU_CLKGATE_CON(0), 7, GFLAGS),
15311497 	GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 0,
15321498 			RK3568_PMU_CLKGATE_CON(1), 0, GFLAGS),
....@@ -1539,7 +1505,7 @@
15391505 	COMPOSITE_FRACMUX(CLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
15401506 			RK3568_PMU_CLKSEL_CON(1), 0,
15411507 			RK3568_PMU_CLKGATE_CON(0), 1, GFLAGS,
1542
-			&rk3568_rtc32k_pmu_fracmux, 0),
1508
+			&rk3568_rtc32k_pmu_fracmux),
15431509 
15441510 	COMPOSITE_NOMUX(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", CLK_IGNORE_UNUSED,
15451511 			RK3568_PMU_CLKSEL_CON(0), 0, 5, DFLAGS,
....@@ -1551,7 +1517,7 @@
15511517 	COMPOSITE_FRACMUX(CLK_UART0_FRAC, "sclk_uart0_frac", "sclk_uart0_div", CLK_SET_RATE_PARENT,
15521518 			RK3568_PMU_CLKSEL_CON(5), CLK_FRAC_DIVIDER_NO_LIMIT,
15531519 			RK3568_PMU_CLKGATE_CON(1), 4, GFLAGS,
1554
-			&rk3568_uart0_fracmux, RK3568_UART_FRAC_MAX_PRATE),
1520
+			&rk3568_uart0_fracmux),
15551521 	GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 0,
15561522 			RK3568_PMU_CLKGATE_CON(1), 5, GFLAGS),
15571523 
....@@ -1633,34 +1599,6 @@
16331599 			RK3568_PMU_GRF_SOC_CON0, 0, 1, MFLAGS)
16341600 };
16351601 
1636
-static const char *const rk3568_cru_critical_clocks[] __initconst = {
1637
-	"armclk",
1638
-	"pclk_core_pre",
1639
-	"aclk_bus",
1640
-	"pclk_bus",
1641
-	"aclk_top_high",
1642
-	"aclk_top_low",
1643
-	"hclk_top",
1644
-	"pclk_top",
1645
-	"aclk_perimid",
1646
-	"hclk_perimid",
1647
-	"aclk_secure_flash",
1648
-	"hclk_secure_flash",
1649
-	"aclk_core_niu2bus",
1650
-	"npll",
1651
-	"clk_optc_arb",
1652
-	"hclk_php",
1653
-	"pclk_php",
1654
-	"hclk_usb",
1655
-	"pclk_usb",
1656
-};
1657
-
1658
-static const char *const rk3568_pmucru_critical_clocks[] __initconst = {
1659
-	"pclk_pdpmu",
1660
-	"pclk_pmu",
1661
-	"clk_pmu",
1662
-};
1663
-
16641602 static void __iomem *rk3568_cru_base;
16651603 static void __iomem *rk3568_pmucru_base;
16661604 
....@@ -1679,6 +1617,16 @@
16791617 			       0x588, false);
16801618 	}
16811619 }
1620
+
1621
+static int protect_clocks[] = {
1622
+	ACLK_VO,
1623
+	HCLK_VO,
1624
+	ACLK_VOP,
1625
+	HCLK_VOP,
1626
+	DCLK_VOP0,
1627
+	DCLK_VOP1,
1628
+	DCLK_VOP2,
1629
+};
16821630 
16831631 static void __init rk3568_pmu_clk_init(struct device_node *np)
16841632 {
....@@ -1709,9 +1657,6 @@
17091657 	rockchip_register_softrst(np, 1, reg_base + RK3568_PMU_SOFTRST_CON(0),
17101658 				  ROCKCHIP_SOFTRST_HIWORD_MASK);
17111659 
1712
-	rockchip_clk_protect_critical(rk3568_pmucru_critical_clocks,
1713
-				      ARRAY_SIZE(rk3568_pmucru_critical_clocks));
1714
-
17151660 	rockchip_clk_of_add_provider(np, ctx);
17161661 }
17171662 
....@@ -1721,6 +1666,7 @@
17211666 {
17221667 	struct rockchip_clk_provider *ctx;
17231668 	void __iomem *reg_base;
1669
+	struct clk **clks;
17241670 
17251671 	reg_base = of_iomap(np, 0);
17261672 	if (!reg_base) {
....@@ -1736,13 +1682,14 @@
17361682 		iounmap(reg_base);
17371683 		return;
17381684 	}
1685
+	clks = ctx->clk_data.clks;
17391686 
17401687 	rockchip_clk_register_plls(ctx, rk3568_pll_clks,
17411688 				   ARRAY_SIZE(rk3568_pll_clks),
17421689 				   RK3568_GRF_SOC_STATUS0);
17431690 
17441691 	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
1745
-				     mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
1692
+				     2, clks[PLL_APLL], clks[PLL_GPLL],
17461693 				     &rk3568_cpuclk_data, rk3568_cpuclk_rates,
17471694 				     ARRAY_SIZE(rk3568_cpuclk_rates));
17481695 
....@@ -1754,17 +1701,17 @@
17541701 
17551702 	rockchip_register_restart_notifier(ctx, RK3568_GLB_SRST_FST, NULL);
17561703 
1757
-	rockchip_clk_protect_critical(rk3568_cru_critical_clocks,
1758
-				      ARRAY_SIZE(rk3568_cru_critical_clocks));
1759
-
17601704 	rockchip_clk_of_add_provider(np, ctx);
17611705 
17621706 	if (!rk_dump_cru)
17631707 		rk_dump_cru = rk3568_dump_cru;
1708
+
1709
+	rockchip_clk_protect(ctx, protect_clocks, ARRAY_SIZE(protect_clocks));
17641710 }
17651711 
17661712 CLK_OF_DECLARE(rk3568_cru, "rockchip,rk3568-cru", rk3568_clk_init);
17671713 
1714
+#ifdef MODULE
17681715 struct clk_rk3568_inits {
17691716 	void (*inits)(struct device_node *np);
17701717 };
....@@ -1789,7 +1736,7 @@
17891736 };
17901737 MODULE_DEVICE_TABLE(of, clk_rk3568_match_table);
17911738 
1792
-static int __init clk_rk3568_probe(struct platform_device *pdev)
1739
+static int clk_rk3568_probe(struct platform_device *pdev)
17931740 {
17941741 	struct device_node *np = pdev->dev.of_node;
17951742 	const struct of_device_id *match;
....@@ -1807,14 +1754,16 @@
18071754 }
18081755 
18091756 static struct platform_driver clk_rk3568_driver = {
1757
+	.probe		= clk_rk3568_probe,
18101758 	.driver		= {
18111759 		.name	= "clk-rk3568",
18121760 		.of_match_table = clk_rk3568_match_table,
18131761 		.suppress_bind_attrs = true,
18141762 	},
18151763 };
1816
-builtin_platform_driver_probe(clk_rk3568_driver, clk_rk3568_probe);
1764
+module_platform_driver(clk_rk3568_driver);
18171765 
18181766 MODULE_DESCRIPTION("Rockchip RK3568 Clock Driver");
18191767 MODULE_LICENSE("GPL");
18201768 MODULE_ALIAS("platform:clk-rk3568");
1769
+#endif /* MODULE */