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2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da 
 kernel/drivers/clk/rockchip/clk-rk3399.c
....@@ -1,31 +1,19 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
34  * Author: Xing Zheng <zhengxing@rock-chips.com>
4
- *
5
- * This program is free software; you can redistribute it and/or modify
6
- * it under the terms of the GNU General Public License as published by
7
- * the Free Software Foundation; either version 2 of the License, or
8
- * (at your option) any later version.
9
- *
10
- * This program is distributed in the hope that it will be useful,
11
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
12
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
- * GNU General Public License for more details.
145  */
156 
167 #include <linux/clk-provider.h>
8
+#include <linux/module.h>
9
+#include <linux/io.h>
1710 #include <linux/of.h>
1811 #include <linux/of_address.h>
12
+#include <linux/of_device.h>
1913 #include <linux/platform_device.h>
2014 #include <linux/regmap.h>
2115 #include <dt-bindings/clock/rk3399-cru.h>
2216 #include "clk.h"
23
-
24
-#define RK3399_I2S_FRAC_MAX_PRATE       800000000
25
-#define RK3399_UART_FRAC_MAX_PRATE	800000000
26
-#define RK3399_SPDIF_FRAC_MAX_PRATE	600000000
27
-#define RK3399_VOP_FRAC_MAX_PRATE	600000000
28
-#define RK3399_WIFI_FRAC_MAX_PRATE	600000000
2917 
3018 enum rk3399_plls {
3119 	lpll, bpll, dpll, cpll, gpll, npll, vpll,
....@@ -139,14 +127,6 @@
139127 /* CRU parents */
140128 PNAME(mux_pll_p)				= { "xin24m", "xin32k" };
141129 
142
-PNAME(mux_armclkl_p)				= { "clk_core_l_lpll_src",
143
-						    "clk_core_l_bpll_src",
144
-						    "clk_core_l_dpll_src",
145
-						    "clk_core_l_gpll_src" };
146
-PNAME(mux_armclkb_p)				= { "clk_core_b_lpll_src",
147
-						    "clk_core_b_bpll_src",
148
-						    "clk_core_b_dpll_src",
149
-						    "clk_core_b_gpll_src" };
150130 PNAME(mux_ddrclk_p)				= { "clk_ddrc_lpll_src",
151131 						    "clk_ddrc_bpll_src",
152132 						    "clk_ddrc_dpll_src",
....@@ -333,7 +313,7 @@
333313 };
334314 
335315 static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
336
-	[ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll",  mux_pll_p, 0, RK3399_PMU_PLL_CON(0),
316
+	[ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll",  mux_pll_p, CLK_IS_CRITICAL, RK3399_PMU_PLL_CON(0),
337317 		     RK3399_PMU_PLL_CON(3), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
338318 };
339319 
....@@ -379,11 +359,11 @@
379359 			RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS, uart_mux_idx);
380360 
381361 static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata =
382
-	MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT | CLK_KEEP_REQ_RATE,
362
+	MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT,
383363 			RK3399_CLKSEL_CON(49), 11, 1, MFLAGS);
384364 
385365 static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata =
386
-	MUX(DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_p, CLK_SET_RATE_PARENT | CLK_KEEP_REQ_RATE,
366
+	MUX(DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_p, CLK_SET_RATE_PARENT,
387367 			RK3399_CLKSEL_CON(50), 11, 1, MFLAGS);
388368 
389369 static struct rockchip_clk_branch rk3399_pmuclk_wifi_fracmux __initdata =
....@@ -525,7 +505,7 @@
525505 	COMPOSITE(ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_p, 0,
526506 			RK3399_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS,
527507 			RK3399_CLKGATE_CON(12), 0, GFLAGS),
528
-	GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", CLK_IGNORE_UNUSED,
508
+	GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", CLK_IS_CRITICAL,
529509 			RK3399_CLKGATE_CON(30), 0, GFLAGS),
530510 	GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 0,
531511 			RK3399_CLKGATE_CON(30), 1, GFLAGS),
....@@ -651,7 +631,7 @@
651631 
652632 	GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0,
653633 			RK3399_CLKGATE_CON(32), 0, GFLAGS),
654
-	GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", CLK_IGNORE_UNUSED,
634
+	GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", CLK_IS_CRITICAL,
655635 			RK3399_CLKGATE_CON(32), 1, GFLAGS),
656636 	GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", 0,
657637 			RK3399_CLKGATE_CON(32), 4, GFLAGS),
....@@ -661,7 +641,7 @@
661641 			RK3399_CLKGATE_CON(6), 11, GFLAGS),
662642 	GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0,
663643 			RK3399_CLKGATE_CON(32), 2, GFLAGS),
664
-	GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", CLK_IGNORE_UNUSED,
644
+	GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", CLK_IS_CRITICAL,
665645 			RK3399_CLKGATE_CON(32), 3, GFLAGS),
666646 
667647 	COMPOSITE(SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_p, 0,
....@@ -671,9 +651,9 @@
671651 	MUX(SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT,
672652 			RK3399_CLKSEL_CON(19), 4, 1, MFLAGS),
673653 	GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 0,
674
-			RK3399_CLKGATE_CON(5), 6, GFLAGS),
675
-	GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 0,
676654 			RK3399_CLKGATE_CON(5), 7, GFLAGS),
655
+	GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 0,
656
+			RK3399_CLKGATE_CON(5), 6, GFLAGS),
677657 	GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", 0,
678658 			RK3399_CLKGATE_CON(5), 8, GFLAGS),
679659 	GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", 0,
....@@ -686,7 +666,7 @@
686666 	COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT,
687667 			RK3399_CLKSEL_CON(99), 0,
688668 			RK3399_CLKGATE_CON(8), 14, GFLAGS,
689
-			&rk3399_spdif_fracmux, RK3399_SPDIF_FRAC_MAX_PRATE),
669
+			&rk3399_spdif_fracmux),
690670 	GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", CLK_SET_RATE_PARENT,
691671 			RK3399_CLKGATE_CON(8), 15, GFLAGS),
692672 
....@@ -700,7 +680,7 @@
700680 	COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
701681 			RK3399_CLKSEL_CON(96), 0,
702682 			RK3399_CLKGATE_CON(8), 4, GFLAGS,
703
-			&rk3399_i2s0_fracmux, RK3399_I2S_FRAC_MAX_PRATE),
683
+			&rk3399_i2s0_fracmux),
704684 	GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLK_SET_RATE_PARENT,
705685 			RK3399_CLKGATE_CON(8), 5, GFLAGS),
706686 
....@@ -710,7 +690,7 @@
710690 	COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
711691 			RK3399_CLKSEL_CON(97), 0,
712692 			RK3399_CLKGATE_CON(8), 7, GFLAGS,
713
-			&rk3399_i2s1_fracmux, RK3399_I2S_FRAC_MAX_PRATE),
693
+			&rk3399_i2s1_fracmux),
714694 	GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
715695 			RK3399_CLKGATE_CON(8), 8, GFLAGS),
716696 
....@@ -720,7 +700,7 @@
720700 	COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
721701 			RK3399_CLKSEL_CON(98), 0,
722702 			RK3399_CLKGATE_CON(8), 10, GFLAGS,
723
-			&rk3399_i2s2_fracmux, RK3399_I2S_FRAC_MAX_PRATE),
703
+			&rk3399_i2s2_fracmux),
724704 	GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
725705 			RK3399_CLKGATE_CON(8), 11, GFLAGS),
726706 
....@@ -739,7 +719,7 @@
739719 	COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT,
740720 			RK3399_CLKSEL_CON(100), 0,
741721 			RK3399_CLKGATE_CON(9), 1, GFLAGS,
742
-			&rk3399_uart0_fracmux, RK3399_UART_FRAC_MAX_PRATE),
722
+			&rk3399_uart0_fracmux),
743723 
744724 	MUX(SCLK_UART_SRC, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0,
745725 			RK3399_CLKSEL_CON(33), 15, 1, MFLAGS),
....@@ -749,7 +729,7 @@
749729 	COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT,
750730 			RK3399_CLKSEL_CON(101), 0,
751731 			RK3399_CLKGATE_CON(9), 3, GFLAGS,
752
-			&rk3399_uart1_fracmux, RK3399_UART_FRAC_MAX_PRATE),
732
+			&rk3399_uart1_fracmux),
753733 
754734 	COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0,
755735 			RK3399_CLKSEL_CON(35), 0, 7, DFLAGS,
....@@ -757,7 +737,7 @@
757737 	COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT,
758738 			RK3399_CLKSEL_CON(102), 0,
759739 			RK3399_CLKGATE_CON(9), 5, GFLAGS,
760
-			&rk3399_uart2_fracmux, RK3399_UART_FRAC_MAX_PRATE),
740
+			&rk3399_uart2_fracmux),
761741 
762742 	COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0,
763743 			RK3399_CLKSEL_CON(36), 0, 7, DFLAGS,
....@@ -765,13 +745,13 @@
765745 	COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", CLK_SET_RATE_PARENT,
766746 			RK3399_CLKSEL_CON(103), 0,
767747 			RK3399_CLKGATE_CON(9), 7, GFLAGS,
768
-			&rk3399_uart3_fracmux, RK3399_UART_FRAC_MAX_PRATE),
748
+			&rk3399_uart3_fracmux),
769749 
770
-	COMPOSITE(PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
750
+	COMPOSITE(PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IS_CRITICAL,
771751 			RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS,
772752 			RK3399_CLKGATE_CON(3), 4, GFLAGS),
773753 
774
-	GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", CLK_IGNORE_UNUSED,
754
+	GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", CLK_IS_CRITICAL,
775755 			RK3399_CLKGATE_CON(18), 10, GFLAGS),
776756 	GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", 0,
777757 			RK3399_CLKGATE_CON(18), 12, GFLAGS),
....@@ -788,30 +768,30 @@
788768 			RK3399_CLKGATE_CON(3), 6, GFLAGS),
789769 
790770 	/* cci */
791
-	GATE(0, "cpll_aclk_cci_src", "cpll", CLK_IGNORE_UNUSED,
771
+	GATE(0, "cpll_aclk_cci_src", "cpll", CLK_IS_CRITICAL,
792772 			RK3399_CLKGATE_CON(2), 0, GFLAGS),
793
-	GATE(0, "gpll_aclk_cci_src", "gpll", CLK_IGNORE_UNUSED,
773
+	GATE(0, "gpll_aclk_cci_src", "gpll", CLK_IS_CRITICAL,
794774 			RK3399_CLKGATE_CON(2), 1, GFLAGS),
795
-	GATE(0, "npll_aclk_cci_src", "npll", CLK_IGNORE_UNUSED,
775
+	GATE(0, "npll_aclk_cci_src", "npll", CLK_IS_CRITICAL,
796776 			RK3399_CLKGATE_CON(2), 2, GFLAGS),
797
-	GATE(0, "vpll_aclk_cci_src", "vpll", CLK_IGNORE_UNUSED,
777
+	GATE(0, "vpll_aclk_cci_src", "vpll", CLK_IS_CRITICAL,
798778 			RK3399_CLKGATE_CON(2), 3, GFLAGS),
799779 
800
-	COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_p, CLK_IGNORE_UNUSED,
780
+	COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_p, CLK_IS_CRITICAL,
801781 			RK3399_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
802782 			RK3399_CLKGATE_CON(2), 4, GFLAGS),
803783 
804
-	GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IGNORE_UNUSED,
784
+	GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IS_CRITICAL,
805785 			RK3399_CLKGATE_CON(15), 0, GFLAGS),
806
-	GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IGNORE_UNUSED,
786
+	GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IS_CRITICAL,
807787 			RK3399_CLKGATE_CON(15), 1, GFLAGS),
808
-	GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLK_IGNORE_UNUSED,
788
+	GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLK_IS_CRITICAL,
809789 			RK3399_CLKGATE_CON(15), 2, GFLAGS),
810
-	GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", CLK_IGNORE_UNUSED,
790
+	GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", CLK_IS_CRITICAL,
811791 			RK3399_CLKGATE_CON(15), 3, GFLAGS),
812
-	GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", CLK_IGNORE_UNUSED,
792
+	GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", CLK_IS_CRITICAL,
813793 			RK3399_CLKGATE_CON(15), 4, GFLAGS),
814
-	GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", CLK_IGNORE_UNUSED,
794
+	GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", CLK_IS_CRITICAL,
815795 			RK3399_CLKGATE_CON(15), 7, GFLAGS),
816796 
817797 	GATE(0, "cpll_cci_trace", "cpll", CLK_IGNORE_UNUSED,
....@@ -822,17 +802,17 @@
822802 			RK3399_CLKSEL_CON(5), 15, 1, MFLAGS, 8, 5, DFLAGS,
823803 			RK3399_CLKGATE_CON(2), 7, GFLAGS),
824804 
825
-	GATE(0, "cpll_cs", "cpll", CLK_IGNORE_UNUSED,
805
+	GATE(0, "cpll_cs", "cpll", CLK_IS_CRITICAL,
826806 			RK3399_CLKGATE_CON(2), 8, GFLAGS),
827
-	GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
807
+	GATE(0, "gpll_cs", "gpll", CLK_IS_CRITICAL,
828808 			RK3399_CLKGATE_CON(2), 9, GFLAGS),
829
-	GATE(0, "npll_cs", "npll", CLK_IGNORE_UNUSED,
809
+	GATE(0, "npll_cs", "npll", CLK_IS_CRITICAL,
830810 			RK3399_CLKGATE_CON(2), 10, GFLAGS),
831
-	COMPOSITE_NOGATE(SCLK_CS, "clk_cs", mux_cs_p, CLK_IGNORE_UNUSED,
811
+	COMPOSITE_NOGATE(SCLK_CS, "clk_cs", mux_cs_p, CLK_IS_CRITICAL,
832812 			RK3399_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS),
833813 	GATE(0, "clk_dbg_cxcs", "clk_cs", CLK_IGNORE_UNUSED,
834814 			RK3399_CLKGATE_CON(15), 5, GFLAGS),
835
-	GATE(0, "clk_dbg_noc", "clk_cs", CLK_IGNORE_UNUSED,
815
+	GATE(0, "clk_dbg_noc", "clk_cs", CLK_IS_CRITICAL,
836816 			RK3399_CLKGATE_CON(15), 6, GFLAGS),
837817 
838818 	/* vcodec */
....@@ -844,12 +824,12 @@
844824 			RK3399_CLKGATE_CON(4), 1, GFLAGS),
845825 	GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
846826 			RK3399_CLKGATE_CON(17), 2, GFLAGS),
847
-	GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", CLK_IGNORE_UNUSED,
827
+	GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", CLK_IS_CRITICAL,
848828 			RK3399_CLKGATE_CON(17), 3, GFLAGS),
849829 
850830 	GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0,
851831 			RK3399_CLKGATE_CON(17), 0, GFLAGS),
852
-	GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", CLK_IGNORE_UNUSED,
832
+	GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", CLK_IS_CRITICAL,
853833 			RK3399_CLKGATE_CON(17), 1, GFLAGS),
854834 
855835 	/* vdu */
....@@ -868,12 +848,12 @@
868848 			RK3399_CLKGATE_CON(4), 3, GFLAGS),
869849 	GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", 0,
870850 			RK3399_CLKGATE_CON(17), 10, GFLAGS),
871
-	GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", CLK_IGNORE_UNUSED,
851
+	GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", CLK_IS_CRITICAL,
872852 			RK3399_CLKGATE_CON(17), 11, GFLAGS),
873853 
874854 	GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 0,
875855 			RK3399_CLKGATE_CON(17), 8, GFLAGS),
876
-	GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", CLK_IGNORE_UNUSED,
856
+	GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", CLK_IS_CRITICAL,
877857 			RK3399_CLKGATE_CON(17), 9, GFLAGS),
878858 
879859 	/* iep */
....@@ -885,12 +865,12 @@
885865 			RK3399_CLKGATE_CON(4), 7, GFLAGS),
886866 	GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 0,
887867 			RK3399_CLKGATE_CON(16), 2, GFLAGS),
888
-	GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", CLK_IGNORE_UNUSED,
868
+	GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", CLK_IS_CRITICAL,
889869 			RK3399_CLKGATE_CON(16), 3, GFLAGS),
890870 
891871 	GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0,
892872 			RK3399_CLKGATE_CON(16), 0, GFLAGS),
893
-	GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", CLK_IGNORE_UNUSED,
873
+	GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", CLK_IS_CRITICAL,
894874 			RK3399_CLKGATE_CON(16), 1, GFLAGS),
895875 
896876 	/* rga */
....@@ -906,21 +886,21 @@
906886 			RK3399_CLKGATE_CON(4), 9, GFLAGS),
907887 	GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0,
908888 			RK3399_CLKGATE_CON(16), 10, GFLAGS),
909
-	GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", CLK_IGNORE_UNUSED,
889
+	GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", CLK_IS_CRITICAL,
910890 			RK3399_CLKGATE_CON(16), 11, GFLAGS),
911891 
912892 	GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0,
913893 			RK3399_CLKGATE_CON(16), 8, GFLAGS),
914
-	GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED,
894
+	GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", CLK_IS_CRITICAL,
915895 			RK3399_CLKGATE_CON(16), 9, GFLAGS),
916896 
917897 	/* center */
918
-	COMPOSITE(ACLK_CENTER, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
898
+	COMPOSITE(ACLK_CENTER, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IS_CRITICAL,
919899 			RK3399_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS,
920900 			RK3399_CLKGATE_CON(3), 7, GFLAGS),
921
-	GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", CLK_IGNORE_UNUSED,
901
+	GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", CLK_IS_CRITICAL,
922902 			RK3399_CLKGATE_CON(19), 0, GFLAGS),
923
-	GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", CLK_IGNORE_UNUSED,
903
+	GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", CLK_IS_CRITICAL,
924904 			RK3399_CLKGATE_CON(19), 1, GFLAGS),
925905 
926906 	/* gpu */
....@@ -937,17 +917,17 @@
937917 			RK3399_CLKGATE_CON(13), 1, GFLAGS),
938918 
939919 	/* perihp */
940
-	GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
920
+	GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IS_CRITICAL,
941921 			RK3399_CLKGATE_CON(5), 1, GFLAGS),
942
-	GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
922
+	GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IS_CRITICAL,
943923 			RK3399_CLKGATE_CON(5), 0, GFLAGS),
944
-	COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
924
+	COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IS_CRITICAL,
945925 			RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
946926 			RK3399_CLKGATE_CON(5), 2, GFLAGS),
947
-	COMPOSITE_NOMUX(HCLK_PERIHP, "hclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
927
+	COMPOSITE_NOMUX(HCLK_PERIHP, "hclk_perihp", "aclk_perihp", CLK_IS_CRITICAL,
948928 			RK3399_CLKSEL_CON(14), 8, 2, DFLAGS,
949929 			RK3399_CLKGATE_CON(5), 3, GFLAGS),
950
-	COMPOSITE_NOMUX(PCLK_PERIHP, "pclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
930
+	COMPOSITE_NOMUX(PCLK_PERIHP, "pclk_perihp", "aclk_perihp", CLK_IS_CRITICAL,
951931 			RK3399_CLKSEL_CON(14), 12, 3, DFLAGS,
952932 			RK3399_CLKGATE_CON(5), 4, GFLAGS),
953933 
....@@ -955,7 +935,7 @@
955935 			RK3399_CLKGATE_CON(20), 2, GFLAGS),
956936 	GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 0,
957937 			RK3399_CLKGATE_CON(20), 10, GFLAGS),
958
-	GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IGNORE_UNUSED,
938
+	GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IS_CRITICAL,
959939 			RK3399_CLKGATE_CON(20), 12, GFLAGS),
960940 
961941 	GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 0,
....@@ -968,16 +948,16 @@
968948 			RK3399_CLKGATE_CON(20), 8, GFLAGS),
969949 	GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", 0,
970950 			RK3399_CLKGATE_CON(20), 9, GFLAGS),
971
-	GATE(0, "hclk_perihp_noc", "hclk_perihp", CLK_IGNORE_UNUSED,
951
+	GATE(0, "hclk_perihp_noc", "hclk_perihp", CLK_IS_CRITICAL,
972952 			RK3399_CLKGATE_CON(20), 13, GFLAGS),
973953 	GATE(0, "hclk_ahb1tom", "hclk_perihp", CLK_IGNORE_UNUSED,
974954 			RK3399_CLKGATE_CON(20), 15, GFLAGS),
975955 
976
-	GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", CLK_IGNORE_UNUSED,
956
+	GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", CLK_IS_CRITICAL,
977957 			RK3399_CLKGATE_CON(20), 4, GFLAGS),
978958 	GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", 0,
979959 			RK3399_CLKGATE_CON(20), 11, GFLAGS),
980
-	GATE(0, "pclk_perihp_noc", "pclk_perihp", CLK_IGNORE_UNUSED,
960
+	GATE(0, "pclk_perihp_noc", "pclk_perihp", CLK_IS_CRITICAL,
981961 			RK3399_CLKGATE_CON(20), 14, GFLAGS),
982962 	GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", 0,
983963 			RK3399_CLKGATE_CON(31), 8, GFLAGS),
....@@ -988,7 +968,7 @@
988968 			RK3399_CLKGATE_CON(12), 13, GFLAGS),
989969 	GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0,
990970 			RK3399_CLKGATE_CON(33), 8, GFLAGS),
991
-	GATE(0, "hclk_sdmmc_noc", "hclk_sd", CLK_IGNORE_UNUSED,
971
+	GATE(0, "hclk_sdmmc_noc", "hclk_sd", CLK_IS_CRITICAL,
992972 			RK3399_CLKGATE_CON(33), 9, GFLAGS),
993973 
994974 	COMPOSITE(SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
....@@ -1035,23 +1015,23 @@
10351015 			RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
10361016 	GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
10371017 			RK3399_CLKGATE_CON(32), 8, GFLAGS),
1038
-	GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLK_IGNORE_UNUSED,
1018
+	GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLK_IS_CRITICAL,
10391019 			RK3399_CLKGATE_CON(32), 9, GFLAGS),
10401020 	GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLK_IGNORE_UNUSED,
10411021 			RK3399_CLKGATE_CON(32), 10, GFLAGS),
10421022 
10431023 	/* perilp0 */
1044
-	GATE(0, "cpll_aclk_perilp0_src", "cpll", CLK_IGNORE_UNUSED,
1024
+	GATE(0, "cpll_aclk_perilp0_src", "cpll", CLK_IS_CRITICAL,
10451025 			RK3399_CLKGATE_CON(7), 1, GFLAGS),
1046
-	GATE(0, "gpll_aclk_perilp0_src", "gpll", CLK_IGNORE_UNUSED,
1026
+	GATE(0, "gpll_aclk_perilp0_src", "gpll", CLK_IS_CRITICAL,
10471027 			RK3399_CLKGATE_CON(7), 0, GFLAGS),
1048
-	COMPOSITE(ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_p, CLK_IGNORE_UNUSED,
1028
+	COMPOSITE(ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_p, CLK_IS_CRITICAL,
10491029 			RK3399_CLKSEL_CON(23), 7, 1, MFLAGS, 0, 5, DFLAGS,
10501030 			RK3399_CLKGATE_CON(7), 2, GFLAGS),
1051
-	COMPOSITE_NOMUX(HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", CLK_IGNORE_UNUSED,
1031
+	COMPOSITE_NOMUX(HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", CLK_IS_CRITICAL,
10521032 			RK3399_CLKSEL_CON(23), 8, 2, DFLAGS,
10531033 			RK3399_CLKGATE_CON(7), 3, GFLAGS),
1054
-	COMPOSITE_NOMUX(PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", 0,
1034
+	COMPOSITE_NOMUX(PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", CLK_IS_CRITICAL,
10551035 			RK3399_CLKSEL_CON(23), 12, 3, DFLAGS,
10561036 			RK3399_CLKGATE_CON(7), 4, GFLAGS),
10571037 
....@@ -1066,8 +1046,8 @@
10661046 	GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 7, GFLAGS),
10671047 	GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", 0, RK3399_CLKGATE_CON(23), 8, GFLAGS),
10681048 	GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 5, GFLAGS),
1069
-	GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 6, GFLAGS),
1070
-	GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 7, GFLAGS),
1049
+	GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 6, GFLAGS),
1050
+	GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 7, GFLAGS),
10711051 
10721052 	/* hclk_perilp0 gates */
10731053 	GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 4, GFLAGS),
....@@ -1075,7 +1055,7 @@
10751055 	GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 6, GFLAGS),
10761056 	GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 14, GFLAGS),
10771057 	GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 15, GFLAGS),
1078
-	GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 8, GFLAGS),
1058
+	GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 8, GFLAGS),
10791059 
10801060 	/* pclk_perilp0 gates */
10811061 	GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", 0, RK3399_CLKGATE_CON(23), 9, GFLAGS),
....@@ -1103,29 +1083,29 @@
11031083 	GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 9, GFLAGS),
11041084 	GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 10, GFLAGS),
11051085 	GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 11, GFLAGS),
1106
-	GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 11, GFLAGS),
1086
+	GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 11, GFLAGS),
11071087 
11081088 	/* perilp1 */
1109
-	GATE(0, "cpll_hclk_perilp1_src", "cpll", CLK_IGNORE_UNUSED,
1089
+	GATE(0, "cpll_hclk_perilp1_src", "cpll", CLK_IS_CRITICAL,
11101090 			RK3399_CLKGATE_CON(8), 1, GFLAGS),
1111
-	GATE(0, "gpll_hclk_perilp1_src", "gpll", CLK_IGNORE_UNUSED,
1091
+	GATE(0, "gpll_hclk_perilp1_src", "gpll", CLK_IS_CRITICAL,
11121092 			RK3399_CLKGATE_CON(8), 0, GFLAGS),
1113
-	COMPOSITE_NOGATE(HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_p, CLK_IGNORE_UNUSED,
1093
+	COMPOSITE_NOGATE(HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_p, CLK_IS_CRITICAL,
11141094 			RK3399_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 5, DFLAGS),
1115
-	COMPOSITE_NOMUX(PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", CLK_IGNORE_UNUSED,
1095
+	COMPOSITE_NOMUX(PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", CLK_IS_CRITICAL,
11161096 			RK3399_CLKSEL_CON(25), 8, 3, DFLAGS,
11171097 			RK3399_CLKGATE_CON(8), 2, GFLAGS),
11181098 
11191099 	/* hclk_perilp1 gates */
1120
-	GATE(0, "hclk_perilp1_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 9, GFLAGS),
1121
-	GATE(0, "hclk_sdio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 12, GFLAGS),
1100
+	GATE(0, "hclk_perilp1_noc", "hclk_perilp1", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 9, GFLAGS),
1101
+	GATE(0, "hclk_sdio_noc", "hclk_perilp1", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 12, GFLAGS),
11221102 	GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 0, GFLAGS),
11231103 	GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 1, GFLAGS),
11241104 	GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 2, GFLAGS),
11251105 	GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 3, GFLAGS),
11261106 	GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 4, GFLAGS),
11271107 	GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 5, GFLAGS),
1128
-	GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 6, GFLAGS),
1108
+	GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(34), 6, GFLAGS),
11291109 
11301110 	/* pclk_perilp1 gates */
11311111 	GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 0, GFLAGS),
....@@ -1148,7 +1128,7 @@
11481128 	GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 12, GFLAGS),
11491129 	GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 13, GFLAGS),
11501130 	GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 0, RK3399_CLKGATE_CON(24), 13, GFLAGS),
1151
-	GATE(0, "pclk_perilp1_noc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(25), 10, GFLAGS),
1131
+	GATE(0, "pclk_perilp1_noc", "pclk_perilp1", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 10, GFLAGS),
11521132 
11531133 	/* saradc */
11541134 	COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
....@@ -1177,18 +1157,18 @@
11771157 	COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
11781158 			RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
11791159 			RK3399_CLKGATE_CON(11), 0, GFLAGS),
1180
-	COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", CLK_IGNORE_UNUSED,
1160
+	COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", CLK_IS_CRITICAL,
11811161 			RK3399_CLKSEL_CON(43), 0, 5, DFLAGS,
11821162 			RK3399_CLKGATE_CON(11), 1, GFLAGS),
11831163 
1184
-	GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", CLK_IGNORE_UNUSED,
1164
+	GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", CLK_IS_CRITICAL,
11851165 			RK3399_CLKGATE_CON(29), 0, GFLAGS),
11861166 
11871167 	GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", 0,
11881168 			RK3399_CLKGATE_CON(29), 1, GFLAGS),
11891169 	GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", 0,
11901170 			RK3399_CLKGATE_CON(29), 2, GFLAGS),
1191
-	GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLK_IGNORE_UNUSED,
1171
+	GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLK_IS_CRITICAL,
11921172 			RK3399_CLKGATE_CON(29), 12, GFLAGS),
11931173 
11941174 	/* hdcp */
....@@ -1201,17 +1181,17 @@
12011181 			RK3399_CLKSEL_CON(43), 10, 5, DFLAGS,
12021182 			RK3399_CLKGATE_CON(11), 10, GFLAGS),
12031183 
1204
-	GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", CLK_IGNORE_UNUSED,
1184
+	GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", CLK_IS_CRITICAL,
12051185 			RK3399_CLKGATE_CON(29), 4, GFLAGS),
12061186 	GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", 0,
12071187 			RK3399_CLKGATE_CON(29), 10, GFLAGS),
12081188 
1209
-	GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", CLK_IGNORE_UNUSED,
1189
+	GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", CLK_IS_CRITICAL,
12101190 			RK3399_CLKGATE_CON(29), 5, GFLAGS),
12111191 	GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", 0,
12121192 			RK3399_CLKGATE_CON(29), 9, GFLAGS),
12131193 
1214
-	GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", CLK_IGNORE_UNUSED,
1194
+	GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", CLK_IS_CRITICAL,
12151195 			RK3399_CLKGATE_CON(29), 3, GFLAGS),
12161196 	GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", 0,
12171197 			RK3399_CLKGATE_CON(29), 6, GFLAGS),
....@@ -1230,7 +1210,7 @@
12301210 	COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0,
12311211 			RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 6, DFLAGS,
12321212 			RK3399_CLKGATE_CON(11), 11, GFLAGS),
1233
-	GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED,
1213
+	GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IS_CRITICAL,
12341214 			RK3399_CLKGATE_CON(32), 12, GFLAGS),
12351215 	GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", 0,
12361216 			RK3399_CLKGATE_CON(32), 13, GFLAGS),
....@@ -1253,12 +1233,12 @@
12531233 
12541234 	GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", 0,
12551235 			RK3399_CLKGATE_CON(28), 3, GFLAGS),
1256
-	GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", CLK_IGNORE_UNUSED,
1236
+	GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", CLK_IS_CRITICAL,
12571237 			RK3399_CLKGATE_CON(28), 1, GFLAGS),
12581238 
12591239 	GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", 0,
12601240 			RK3399_CLKGATE_CON(28), 2, GFLAGS),
1261
-	GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
1241
+	GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IS_CRITICAL,
12621242 			RK3399_CLKGATE_CON(28), 0, GFLAGS),
12631243 
12641244 #ifdef RK3399_TWO_PLL_FOR_VOP
....@@ -1274,7 +1254,7 @@
12741254 	/* The VOP0 is main screen, it is able to re-set parent rate. */
12751255 	COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop0_frac", "dclk_vop0_div", CLK_SET_RATE_PARENT,
12761256 			RK3399_CLKSEL_CON(106), 0,
1277
-			&rk3399_dclk_vop0_fracmux, RK3399_VOP_FRAC_MAX_PRATE),
1257
+			&rk3399_dclk_vop0_fracmux),
12781258 
12791259 	COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_dmyvpll_cpll_gpll_gpll_p, 0,
12801260 			RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
....@@ -1290,12 +1270,12 @@
12901270 
12911271 	GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", 0,
12921272 			RK3399_CLKGATE_CON(28), 7, GFLAGS),
1293
-	GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", CLK_IGNORE_UNUSED,
1273
+	GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", CLK_IS_CRITICAL,
12941274 			RK3399_CLKGATE_CON(28), 5, GFLAGS),
12951275 
12961276 	GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", 0,
12971277 			RK3399_CLKGATE_CON(28), 6, GFLAGS),
1298
-	GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", CLK_IGNORE_UNUSED,
1278
+	GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", CLK_IS_CRITICAL,
12991279 			RK3399_CLKGATE_CON(28), 4, GFLAGS),
13001280 
13011281 	/* The VOP1 is sub screen, it is note able to re-set parent rate. */
....@@ -1311,7 +1291,7 @@
13111291 
13121292 	COMPOSITE_FRACMUX_NOGATE(DCLK_VOP1_FRAC, "dclk_vop1_frac", "dclk_vop1_div", 0,
13131293 			RK3399_CLKSEL_CON(107), 0,
1314
-			&rk3399_dclk_vop1_fracmux, RK3399_VOP_FRAC_MAX_PRATE),
1294
+			&rk3399_dclk_vop1_fracmux),
13151295 
13161296 	COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_dmyvpll_cpll_gpll_gpll_p, 0,
13171297 			RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS,
....@@ -1325,12 +1305,12 @@
13251305 			RK3399_CLKSEL_CON(53), 8, 5, DFLAGS,
13261306 			RK3399_CLKGATE_CON(12), 9, GFLAGS),
13271307 
1328
-	GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", CLK_IGNORE_UNUSED,
1308
+	GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", CLK_IS_CRITICAL,
13291309 			RK3399_CLKGATE_CON(27), 1, GFLAGS),
13301310 	GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", 0,
13311311 			RK3399_CLKGATE_CON(27), 5, GFLAGS),
13321312 
1333
-	GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", CLK_IGNORE_UNUSED,
1313
+	GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", CLK_IS_CRITICAL,
13341314 			RK3399_CLKGATE_CON(27), 0, GFLAGS),
13351315 	GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", 0,
13361316 			RK3399_CLKGATE_CON(27), 4, GFLAGS),
....@@ -1346,12 +1326,12 @@
13461326 			RK3399_CLKSEL_CON(54), 8, 5, DFLAGS,
13471327 			RK3399_CLKGATE_CON(12), 11, GFLAGS),
13481328 
1349
-	GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", CLK_IGNORE_UNUSED,
1329
+	GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", CLK_IS_CRITICAL,
13501330 			RK3399_CLKGATE_CON(27), 3, GFLAGS),
13511331 	GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "aclk_isp1", 0,
13521332 			RK3399_CLKGATE_CON(27), 8, GFLAGS),
13531333 
1354
-	GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", CLK_IGNORE_UNUSED,
1334
+	GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", CLK_IS_CRITICAL,
13551335 			RK3399_CLKGATE_CON(27), 2, GFLAGS),
13561336 	GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "hclk_isp1", 0,
13571337 			RK3399_CLKGATE_CON(27), 7, GFLAGS),
....@@ -1376,16 +1356,16 @@
13761356 			RK3399_CLKSEL_CON(56), 6, 2, MFLAGS,
13771357 			RK3399_CLKGATE_CON(10), 7, GFLAGS),
13781358 
1379
-	COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, 0,
1359
+	COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, CLK_SET_RATE_PARENT,
13801360 			 RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS),
13811361 
13821362 	/* gic */
1383
-	COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
1363
+	COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IS_CRITICAL,
13841364 			RK3399_CLKSEL_CON(56), 15, 1, MFLAGS, 8, 5, DFLAGS,
13851365 			RK3399_CLKGATE_CON(12), 12, GFLAGS),
13861366 
1387
-	GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 0, GFLAGS),
1388
-	GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 1, GFLAGS),
1367
+	GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(33), 0, GFLAGS),
1368
+	GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(33), 1, GFLAGS),
13891369 	GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 2, GFLAGS),
13901370 	GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 3, GFLAGS),
13911371 	GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 4, GFLAGS),
....@@ -1412,6 +1392,9 @@
14121392 	GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 9, GFLAGS),
14131393 	GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 10, GFLAGS),
14141394 
1395
+	/* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */
1396
+	SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_alive"),
1397
+
14151398 	GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 0, RK3399_CLKGATE_CON(11), 14, GFLAGS),
14161399 	GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", 0, RK3399_CLKGATE_CON(21), 0, GFLAGS),
14171400 
....@@ -1425,7 +1408,7 @@
14251408 			RK3399_CLKSEL_CON(58), 7, 1, MFLAGS),
14261409 	COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", 0,
14271410 			RK3399_CLKSEL_CON(105), 0,
1428
-			RK3399_CLKGATE_CON(13), 9, GFLAGS, 0),
1411
+			RK3399_CLKGATE_CON(13), 9, GFLAGS),
14291412 
14301413 	DIV(0, "clk_test_24m", "xin24m", 0,
14311414 			RK3399_CLKSEL_CON(57), 6, 10, DFLAGS),
....@@ -1497,13 +1480,13 @@
14971480 			RK3399_CLKGATE_CON(13), 11, GFLAGS),
14981481 
14991482 	/* ddrc */
1500
-	GATE(0, "clk_ddrc_lpll_src", "lpll", 0, RK3399_CLKGATE_CON(3),
1483
+	GATE(0, "clk_ddrc_lpll_src", "lpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(3),
15011484 	     0, GFLAGS),
1502
-	GATE(0, "clk_ddrc_bpll_src", "bpll", 0, RK3399_CLKGATE_CON(3),
1485
+	GATE(0, "clk_ddrc_bpll_src", "bpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(3),
15031486 	     1, GFLAGS),
1504
-	GATE(0, "clk_ddrc_dpll_src", "dpll", 0, RK3399_CLKGATE_CON(3),
1487
+	GATE(0, "clk_ddrc_dpll_src", "dpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(3),
15051488 	     2, GFLAGS),
1506
-	GATE(0, "clk_ddrc_gpll_src", "gpll", 0, RK3399_CLKGATE_CON(3),
1489
+	GATE(0, "clk_ddrc_gpll_src", "gpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(3),
15071490 	     3, GFLAGS),
15081491 	COMPOSITE_DDRCLK(SCLK_DDRC, "sclk_ddrc", mux_ddrclk_p, 0,
15091492 		       RK3399_CLKSEL_CON(6), 4, 2, 0, 0, ROCKCHIP_DDRCLK_SIP),
....@@ -1514,10 +1497,10 @@
15141497 	 * PMU CRU Clock-Architecture
15151498 	 */
15161499 
1517
-	GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", 0,
1500
+	GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", CLK_IS_CRITICAL,
15181501 			RK3399_PMU_CLKGATE_CON(0), 1, GFLAGS),
15191502 
1520
-	COMPOSITE_NOGATE(FCLK_CM0S_SRC_PMU, "fclk_cm0s_src_pmu", mux_fclk_cm0s_pmu_ppll_p, 0,
1503
+	COMPOSITE_NOGATE(FCLK_CM0S_SRC_PMU, "fclk_cm0s_src_pmu", mux_fclk_cm0s_pmu_ppll_p, CLK_IS_CRITICAL,
15211504 			RK3399_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS),
15221505 
15231506 	COMPOSITE(SCLK_SPI3_PMU, "clk_spi3_pmu", mux_24m_ppll_p, 0,
....@@ -1530,7 +1513,7 @@
15301513 
15311514 	COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", CLK_SET_RATE_PARENT,
15321515 			RK3399_PMU_CLKSEL_CON(7), 0,
1533
-			&rk3399_pmuclk_wifi_fracmux, RK3399_WIFI_FRAC_MAX_PRATE),
1516
+			&rk3399_pmuclk_wifi_fracmux),
15341517 
15351518 	MUX(0, "clk_timer_src_pmu", mux_pll_p, CLK_IGNORE_UNUSED,
15361519 			RK3399_PMU_CLKSEL_CON(1), 15, 1, MFLAGS),
....@@ -1562,9 +1545,9 @@
15621545 	COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", CLK_SET_RATE_PARENT,
15631546 			RK3399_PMU_CLKSEL_CON(6), 0,
15641547 			RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS,
1565
-			&rk3399_uart4_pmu_fracmux, RK3399_UART_FRAC_MAX_PRATE),
1548
+			&rk3399_uart4_pmu_fracmux),
15661549 
1567
-	DIV(PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLK_IGNORE_UNUSED,
1550
+	DIV(PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLK_IS_CRITICAL,
15681551 			RK3399_PMU_CLKSEL_CON(0), 0, 5, DFLAGS),
15691552 
15701553 	/* pmu clock gates */
....@@ -1579,11 +1562,11 @@
15791562 	GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 3, GFLAGS),
15801563 	GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 4, GFLAGS),
15811564 	GATE(PCLK_SGRF_PMU, "pclk_sgrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 5, GFLAGS),
1582
-	GATE(PCLK_NOC_PMU, "pclk_noc_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 6, GFLAGS),
1565
+	GATE(PCLK_NOC_PMU, "pclk_noc_pmu", "pclk_pmu_src", CLK_IS_CRITICAL, RK3399_PMU_CLKGATE_CON(1), 6, GFLAGS),
15831566 	GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 7, GFLAGS),
15841567 	GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 8, GFLAGS),
15851568 	GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 9, GFLAGS),
1586
-	GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 10, GFLAGS),
1569
+	GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", CLK_IS_CRITICAL, RK3399_PMU_CLKGATE_CON(1), 10, GFLAGS),
15871570 	GATE(PCLK_SPI3_PMU, "pclk_spi3_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 11, GFLAGS),
15881571 	GATE(PCLK_TIMER_PMU, "pclk_timer_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 12, GFLAGS),
15891572 	GATE(PCLK_MAILBOX_PMU, "pclk_mailbox_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 13, GFLAGS),
....@@ -1594,102 +1577,7 @@
15941577 	GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 1, GFLAGS),
15951578 	GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 2, GFLAGS),
15961579 	GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 3, GFLAGS),
1597
-	GATE(HCLK_NOC_PMU, "hclk_noc_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 5, GFLAGS),
1598
-};
1599
-
1600
-static const char *const rk3399_cru_critical_clocks[] __initconst = {
1601
-	/*
1602
-	 * We need to declare that we enable all NOCs which are critical clocks
1603
-	 * always and clearly and explicitly show that we have enabled them at
1604
-	 * clk_summary.
1605
-	 */
1606
-	"aclk_usb3_noc",
1607
-	"aclk_gmac_noc",
1608
-	"pclk_gmac_noc",
1609
-	"pclk_center_main_noc",
1610
-	"aclk_cci_noc0",
1611
-	"aclk_cci_noc1",
1612
-	"clk_dbg_noc",
1613
-	"hclk_vcodec_noc",
1614
-	"aclk_vcodec_noc",
1615
-	"hclk_vdu_noc",
1616
-	"aclk_vdu_noc",
1617
-	"hclk_iep_noc",
1618
-	"aclk_iep_noc",
1619
-	"hclk_rga_noc",
1620
-	"aclk_rga_noc",
1621
-	"aclk_center_main_noc",
1622
-	"aclk_center_peri_noc",
1623
-	"aclk_perihp_noc",
1624
-	"hclk_perihp_noc",
1625
-	"pclk_perihp_noc",
1626
-	"hclk_sdmmc_noc",
1627
-	"aclk_emmc_noc",
1628
-	"aclk_perilp0_noc",
1629
-	"hclk_perilp0_noc",
1630
-	"hclk_m0_perilp_noc",
1631
-	"hclk_perilp1_noc",
1632
-	"hclk_sdio_noc",
1633
-	"hclk_sdioaudio_noc",
1634
-	"pclk_perilp1_noc",
1635
-	"aclk_vio_noc",
1636
-	"aclk_hdcp_noc",
1637
-	"hclk_hdcp_noc",
1638
-	"pclk_hdcp_noc",
1639
-	"pclk_edp_noc",
1640
-	"aclk_vop0_noc",
1641
-	"hclk_vop0_noc",
1642
-	"aclk_vop1_noc",
1643
-	"hclk_vop1_noc",
1644
-	"aclk_isp0_noc",
1645
-	"hclk_isp0_noc",
1646
-	"aclk_isp1_noc",
1647
-	"hclk_isp1_noc",
1648
-	"aclk_gic_noc",
1649
-
1650
-	/* other critical clocks */
1651
-	"aclk_gic",
1652
-	"aclk_gic_noc",
1653
-	"aclk_hdcp_noc",
1654
-	"hclk_hdcp_noc",
1655
-	"pclk_hdcp_noc",
1656
-	"pclk_perilp0",
1657
-	"pclk_perilp0",
1658
-	"hclk_perilp0",
1659
-	"pclk_perilp1",
1660
-	"pclk_perihp",
1661
-	"hclk_perihp",
1662
-	"aclk_perihp",
1663
-	"aclk_perilp0",
1664
-	"hclk_perilp1",
1665
-	"aclk_dmac1_perilp",
1666
-	"aclk_emmc_noc",
1667
-	"gpll_aclk_perilp0_src",
1668
-	"gpll_aclk_perihp_src",
1669
-	"aclk_vio_noc",
1670
-
1671
-	/* ddrc */
1672
-	"sclk_ddrc"
1673
-	"pclk_vio",
1674
-	"pclk_vio_grf",
1675
-	"pclk_perihp_grf",
1676
-};
1677
-
1678
-static const char *const rk3399_pmucru_critical_clocks[] __initconst = {
1679
-	/*
1680
-	 * We need to declare that we enable all NOCs which are critical clocks
1681
-	 * always and clearly and explicitly show that we have enabled them at
1682
-	 * clk_summary.
1683
-	 */
1684
-	"pclk_noc_pmu",
1685
-	"hclk_noc_pmu",
1686
-
1687
-	/* other critical clocks */
1688
-	"ppll",
1689
-	"pclk_pmu_src",
1690
-	"fclk_cm0s_src_pmu",
1691
-	"clk_timer_src_pmu",
1692
-	"pclk_rkpwm_pmu",
1580
+	GATE(HCLK_NOC_PMU, "hclk_noc_pmu", "fclk_cm0s_src_pmu", CLK_IS_CRITICAL, RK3399_PMU_CLKGATE_CON(2), 5, GFLAGS),
16931581 };
16941582 
16951583 static void __iomem *rk3399_cru_base;
....@@ -1727,7 +1615,7 @@
17271615 {
17281616 	struct rockchip_clk_provider *ctx;
17291617 	void __iomem *reg_base;
1730
-	struct clk *clk;
1618
+	struct clk **clks;
17311619 
17321620 	reg_base = of_iomap(np, 0);
17331621 	if (!reg_base) {
....@@ -1743,14 +1631,7 @@
17431631 		iounmap(reg_base);
17441632 		return;
17451633 	}
1746
-
1747
-	/* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */
1748
-	clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_alive", 0, 1, 1);
1749
-	if (IS_ERR(clk))
1750
-		pr_warn("%s: could not register clock pclk_wdt: %ld\n",
1751
-			__func__, PTR_ERR(clk));
1752
-	else
1753
-		rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
1634
+	clks = ctx->clk_data.clks;
17541635 
17551636 	rockchip_clk_register_plls(ctx, rk3399_pll_clks,
17561637 				   ARRAY_SIZE(rk3399_pll_clks), -1);
....@@ -1758,16 +1639,13 @@
17581639 	rockchip_clk_register_branches(ctx, rk3399_clk_branches,
17591640 				  ARRAY_SIZE(rk3399_clk_branches));
17601641 
1761
-	rockchip_clk_protect_critical(rk3399_cru_critical_clocks,
1762
-				      ARRAY_SIZE(rk3399_cru_critical_clocks));
1763
-
17641642 	rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
1765
-			mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
1643
+			4, clks[PLL_APLLL], clks[PLL_GPLL],
17661644 			&rk3399_cpuclkl_data, rk3399_cpuclkl_rates,
17671645 			ARRAY_SIZE(rk3399_cpuclkl_rates));
17681646 
17691647 	rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb",
1770
-			mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),
1648
+			4, clks[PLL_APLLB], clks[PLL_GPLL],
17711649 			&rk3399_cpuclkb_data, rk3399_cpuclkb_rates,
17721650 			ARRAY_SIZE(rk3399_cpuclkb_rates));
17731651 
....@@ -1806,9 +1684,6 @@
18061684 	rockchip_clk_register_branches(ctx, rk3399_clk_pmu_branches,
18071685 				  ARRAY_SIZE(rk3399_clk_pmu_branches));
18081686 
1809
-	rockchip_clk_protect_critical(rk3399_pmucru_critical_clocks,
1810
-				  ARRAY_SIZE(rk3399_pmucru_critical_clocks));
1811
-
18121687 	rockchip_register_softrst(np, 2, reg_base + RK3399_PMU_SOFTRST_CON(0),
18131688 				  ROCKCHIP_SOFTRST_HIWORD_MASK);
18141689 
....@@ -1818,3 +1693,60 @@
18181693 				       &rk3399_clk_panic_block);
18191694 }
18201695 CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);
1696
+
1697
+#ifdef MODULE
1698
+struct clk_rk3399_inits {
1699
+	void (*inits)(struct device_node *np);
1700
+};
1701
+
1702
+static const struct clk_rk3399_inits clk_rk3399_pmucru_init = {
1703
+	.inits = rk3399_pmu_clk_init,
1704
+};
1705
+
1706
+static const struct clk_rk3399_inits clk_rk3399_cru_init = {
1707
+	.inits = rk3399_clk_init,
1708
+};
1709
+
1710
+static const struct of_device_id clk_rk3399_match_table[] = {
1711
+	{
1712
+		.compatible = "rockchip,rk3399-cru",
1713
+		.data = &clk_rk3399_cru_init,
1714
+	},  {
1715
+		.compatible = "rockchip,rk3399-pmucru",
1716
+		.data = &clk_rk3399_pmucru_init,
1717
+	},
1718
+	{ }
1719
+};
1720
+MODULE_DEVICE_TABLE(of, clk_rk3399_match_table);
1721
+
1722
+static int clk_rk3399_probe(struct platform_device *pdev)
1723
+{
1724
+	struct device_node *np = pdev->dev.of_node;
1725
+	const struct of_device_id *match;
1726
+	const struct clk_rk3399_inits *init_data;
1727
+
1728
+	match = of_match_device(clk_rk3399_match_table, &pdev->dev);
1729
+	if (!match || !match->data)
1730
+		return -EINVAL;
1731
+
1732
+	init_data = match->data;
1733
+	if (init_data->inits)
1734
+		init_data->inits(np);
1735
+
1736
+	return 0;
1737
+}
1738
+
1739
+static struct platform_driver clk_rk3399_driver = {
1740
+	.probe		= clk_rk3399_probe,
1741
+	.driver		= {
1742
+		.name	= "clk-rk3399",
1743
+		.of_match_table = clk_rk3399_match_table,
1744
+		.suppress_bind_attrs = true,
1745
+	},
1746
+};
1747
+module_platform_driver(clk_rk3399_driver);
1748
+
1749
+MODULE_DESCRIPTION("Rockchip RK3399 Clock Driver");
1750
+MODULE_LICENSE("GPL");
1751
+MODULE_ALIAS("platform:clk-rk3399");
1752
+#endif /* MODULE */